1. A heterogeneous computing platform based on artificial intelligence comprises a bottom heterogeneous hardware platform, a system software layer and an application software layer, wherein the system software layer runs on the bottom heterogeneous hardware platform, the application software layer develops and applies on the system software layer, and the bottom heterogeneous hardware platform consists of a data processing module, a heterogeneous interconnection transmission module, a temperature detection regulation control module, an electromagnetic compatibility collision design module, a power consumption management energy consumption control module, a satellite-borne environment host adaptation module, a CPU main control unit, an FPGA acceleration unit, an IPU, a DSP processing unit and a fault tolerance and fault recovery module;

the system software layer comprises an intelligent algorithm library and middleware, a task scheduling strategy and a software and hardware partitioning mechanism are set, parallel processing and heterogeneous computing are supported, and a parallel programming framework is adopted for adaptation;

the application software layer provides modeling and analysis of the artificial intelligence application calculation process and a characteristic description and data flow analysis interface of the artificial intelligence application.

2. The heterogeneous computing platform based on artificial intelligence according to claim 1, wherein the data processing module comprises a basic module subsystem, a temperature management subsystem and a power consumption control interface subsystem, the basic module subsystem comprises a storage module, a clock module, an intelligent chip, an IO module and a power module, the intelligent chip is connected with the storage module, the clock module, the IO module and the power module, and the basic module subsystem is connected with the temperature management subsystem and the power consumption control interface subsystem.

3. The heterogeneous computing platform based on artificial intelligence according to claim 1 or 2, wherein the platform system software layer completes task scheduling and task allocation through a task scheduling module, and completes device caching, onboard memory management and Docker instance-application mapping tasks through a load balancing module.

4. The artificial intelligence based heterogeneous computing platform according to claim 1 or 3, wherein the on-platform tasks include software tasks defined as tasks running on a general purpose processor and hardware tasks defined as tasks running on a heterogeneous computing unit.

5. The artificial intelligence based heterogeneous computing platform according to claim 4, wherein the execution time of each hardware task is substantially fixed, and the execution process comprises three stages of input data transmission, task execution and output data transmission.

6. The artificial intelligence based heterogeneous computing platform according to claim 4, wherein the hardware tasks do not normally support task preemption, once a hardware task starts executing, the heterogeneous computing unit is exclusively owned by the hardware task from the time the task sends data until a computing result returns, and other tasks cannot obtain the usage right of the heterogeneous computing unit.

7. The artificial intelligence based heterogeneous computing platform according to claim 4, wherein the hardware tasks have no capability of direct communication therebetween, the direct communication of the hardware tasks requires hardware support of the platform, and the heterogeneous computing units need a direct hardware path therebetween, so as to complete transmission of signals and data.

8. The artificial intelligence based heterogeneous computing platform of claim 1, further comprising a memory management module that performs virtual address space to physical address space translation via page table structures; when a heterogeneous compute core or data transfer bus requires off-chip on-board memory, the page table structure provides an address to the memory management component.

9. The artificial intelligence based heterogeneous computing platform of claim 8, the heterogeneous task execution flow of the platform being as follows:

after a task is created, a software task unit and a hardware task unit are respectively bound, the task is divided into a software task load and a hardware task load, the software task load is executed through software and is checked, the hardware task load is respectively completed hardware task creation and hardware execution and is checked after control and write-back operation, and the hardware task creation and the hardware execution are completed through scheduling.

10. The artificial intelligence based heterogeneous computing platform according to claim 9, wherein the hardware task load can be controlled by the heterogeneous computing unit through hardware execution or by the heterogeneous computing unit directly after the hardware execution.

Background

At present, a single commercial chip is difficult to adapt to the requirement. The method is not enough to support the application of artificial intelligence quickly, efficiently and with low power consumption, and a set of heterogeneous computing system is needed to support the demand of heterogeneous computing. In the traditional application, the application of some special scenes has the problems of large data volume, difficult rapid processing and the like, and simultaneously has great requirements on safety and reliability. .

Disclosure of Invention

In order to overcome the defects of the prior art, the invention needs to solve the technical problems that the special requirements of different load data processing applications are met, certain universality is realized, the characteristics of standardization, modularization and expandability are realized, the reconfigurable and fault-tolerant capability is realized, and the application requirements of special space environments are met. The constructed processing platform can quickly realize different types of data processing application requirements through simple module combination.

Aiming at the defects in the prior art, the invention provides an artificial intelligence-based heterogeneous computing platform which comprises a bottom heterogeneous hardware platform, a system software layer and an application software layer, wherein the system software layer runs on the bottom heterogeneous hardware platform, the application software layer develops and applies on the system software layer, and the bottom heterogeneous hardware platform consists of a data processing module, a heterogeneous interconnection transmission module, a temperature detection and regulation control module, an electromagnetic compatibility collision design module, a power consumption management energy consumption control module, a satellite-borne environment host adaptation module, a CPU (central processing unit) main control unit, an FPGA (field programmable gate array) acceleration unit, an IPU (internet protocol unit), a DSP (digital signal processor) processing unit and a fault tolerance and fault recovery module;

the system software layer comprises an intelligent algorithm library and middleware, a task scheduling strategy and a software and hardware partitioning mechanism are set, parallel processing and heterogeneous computing are supported, and a parallel programming framework is adopted for adaptation;

the application software layer provides modeling and analysis of the artificial intelligence application calculation process and a characteristic description and data flow analysis interface of the artificial intelligence application.

Preferably, the data processing module is composed of a basic module subsystem, a temperature management subsystem and a power consumption control interface subsystem, wherein the basic module subsystem is composed of a storage module, a clock module, an intelligent chip, an IO module and a power module, the intelligent chip is respectively connected with the storage module, the clock module, the IO module and the power module, and the basic module subsystem is respectively connected with the temperature management subsystem and the power consumption control interface subsystem.

Preferably, the platform system software layer completes task scheduling and task allocation through the task scheduling module, and completes device caching, onboard memory management and Docker instance-application mapping tasks through the load balancing module.

Preferably, the tasks on the platform include software tasks and hardware tasks, the software tasks are defined as tasks running on a general-purpose processor, and the hardware tasks are defined as tasks running on heterogeneous computing units.

Preferably, the execution time of each hardware task is basically fixed, and the execution process comprises three stages of input data transmission, task execution and output data transmission.

Preferably, the hardware tasks generally do not support task preemption, and once a hardware task starts to execute, the heterogeneous computing unit is monopolized by the hardware task from the time the task sends data until a computing result returns, and other tasks cannot obtain the use right of the heterogeneous computing unit.

Preferably, the hardware tasks do not have the capability of direct communication, the direct communication of the hardware tasks needs the hardware support of the platform, and the heterogeneous computing units need a direct hardware path, so as to complete the transmission of signals and data.

Preferably, the platform further comprises a memory management module, which completes the conversion from the virtual address space to the physical address space through the page table structure; when a heterogeneous compute core or data transfer bus requires off-chip on-board memory, the page table structure provides an address to the memory management component.

Preferably, the heterogeneous task operation flow of the platform is as follows:

after a task is created, a software task unit and a hardware task unit are respectively bound, the task is divided into a software task load and a hardware task load, the software task load is executed through software and is checked, the hardware task load is respectively completed hardware task creation and hardware execution and is checked after control and write-back operation, and the hardware task creation and the hardware execution are completed through scheduling.

Preferably, the hardware task load may be controlled by the heterogeneous computing unit, or may be directly controlled after the execution of the hardware.

Compared with the prior art, the invention realizes heterogeneous computation based on artificial intelligence, adopts the design of a dual-redundancy exchange switch type interconnection system architecture, supports a system architecture of dynamic expansion and parallel processing, and comprises a hardware system architecture, a software platform design and an internal bus design. By adding the redundant link and the fault detection circuit, when a single computing module or a data link has a fault, the node forwarding table of the switching module is reconfigured to carry out topology reconstruction on the parallel system, so that the system has stronger fault tolerance and fault isolation capability.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention will be briefly described below, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 illustrates a block diagram of an artificial intelligence based heterogeneous computing platform of the present invention;

FIG. 2 is a block diagram of a single point task management and resource scheduling subsystem of the present invention;

FIG. 3 is a flow chart illustrating the operation of the heterogeneous task of the present invention;

FIG. 4 shows a data processing module hardware architecture diagram of the present invention.

Detailed Description

Features and exemplary embodiments of various aspects of the present invention will be described in detail below, and in order to make objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention. It will be apparent to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

As shown in fig. 1, the present invention provides an embodiment of an artificial intelligence based heterogeneous computing platform, which includes a bottom heterogeneous hardware platform, a system software layer and an application software layer, wherein the system software layer runs on the bottom heterogeneous hardware platform, and the application software layer develops an application on the system software layer, and the bottom heterogeneous hardware platform is composed of a data processing module, a heterogeneous interconnection transmission module, a temperature detection and adjustment control module, an electromagnetic compatibility collision design module, a power consumption management and energy consumption control module, a satellite-borne environment host adaptation module, a CPU main control unit, an FPGA acceleration unit, an IPU, a DSP processing unit and a fault tolerance and recovery module;

the system software layer comprises an intelligent algorithm library and middleware, a task scheduling strategy and a software and hardware partitioning mechanism are set, parallel processing and heterogeneous computing are supported, and a parallel programming framework is adopted for adaptation;

the application software layer provides modeling and analysis of the artificial intelligence application calculation process and a characteristic description and data flow analysis interface of the artificial intelligence application.

As shown in fig. 4, the data processing module of this embodiment is composed of a basic module subsystem, a temperature management subsystem, and a power consumption control interface subsystem, where the basic module subsystem includes a storage module, a clock module, an intelligent chip, an IO module, and a power module, the intelligent chip is connected to the storage module, the clock module, the IO module, and the power module, and the basic module subsystem is connected to the temperature management subsystem and the power consumption control interface subsystem. The IO module comprises PCIE and SPI.

As shown in fig. 2, in the embodiment of the heterogeneous computing platform based on artificial intelligence provided by the present invention, a platform system software layer completes task scheduling and task allocation through a task scheduling module, and completes device caching, onboard memory management, and Docker instance-application mapping tasks through a load balancing module. The hardware layer comprises a plurality of intelligent boards including an intelligent board 1, an intelligent board 2, an intelligent board 3 and an intelligent board … …, the intelligent boards correspond to equipment 1, equipment 2, equipment 3 and equipment … … n in a management module of a platform system software layer, each piece of equipment is provided with a cache queue, and the cache queue comprises an on-board memory management submodule and a Docker instance-application mapping table and corresponds to a Docker instance library

In some embodiments, the on-platform tasks include software tasks defined as tasks running on a general purpose processor and hardware tasks defined as tasks running on a heterogeneous computing unit.

In some embodiments, the execution time of each hardware task is basically fixed, and the execution process comprises three stages of input data transmission, task execution and output data transmission.

In some embodiments, the hardware task generally does not support task preemption, once a hardware task starts to execute, the heterogeneous computing unit is monopolized by the hardware task from the time the task sends data until a computing result returns, and other tasks cannot obtain the use right of the heterogeneous computing unit.

In some embodiments, the hardware tasks do not have the capability of direct communication, the direct communication of the hardware tasks requires the hardware support of the platform, and a direct hardware path is required between the heterogeneous computing units, so as to complete the transmission of signals and data.

In some embodiments, the platform further comprises a memory management module that performs translation from virtual address space to physical address space via the page table structure; when a heterogeneous compute core or data transfer bus requires off-chip on-board memory, the page table structure provides an address to the memory management component.

As shown in fig. 3, the present invention provides an embodiment of an artificial intelligence based heterogeneous computing platform heterogeneous task operation flow, which binds a software task unit and a hardware task unit after creating a task, and divides the task into a software task load and a hardware task load, where the software task load is executed by software and completes an inspection, the hardware task load completes hardware task creation and hardware execution respectively, and completes an inspection after control and write-back operations, and the hardware task creation and hardware execution are completed by scheduling. The hardware task load can be controlled by the heterogeneous computing unit, or can be directly controlled after the hardware is executed.

The invention also provides an embodiment of the artificial intelligence-based heterogeneous computing platform, wherein the scheme of the artificial intelligence heterogeneous computing platform adopts a dual-redundancy exchange switch type interconnection architecture design, and a system architecture supporting dynamic expansion and parallel processing comprises a hardware system architecture, a software platform design and an internal bus design.

Generalized high-speed data processing devices employ parallel processing techniques to meet the rapidly growing high-speed data processing demands of the system. The high-speed parallel processing of data is realized in two aspects of parallel architecture hardware and parallel algorithm programming.

Parallel architecture hardware is the basis for implementing high-speed parallel processing. The generalized high-speed data processing equipment adopts a multistage parallel structure: a plurality of computing modules are used for forming a distributed storage Multiple Instruction Multiple Data (MIMD) parallel architecture at a device level; forming heterogeneous parallel computing nodes by using a plurality of processors and an FPGA at a module level; and a multi-core processor is used at the processor chip level, and the operation capability of a single processor is improved by utilizing an on-chip multi-core structure.

In order to obtain maximum universality and expandability, a distributed storage MIMD parallel architecture is adopted at a device level. Each computation module in the equipment has an independent address space, and data interaction and communication are realized among the modules through an internet. In order to realize flexible expansion of a topological structure of a parallel system, an interconnection network is formed by using a high-speed serial bus (SRIO) and a high-speed exchange module. By configuring the node forwarding table of the switching module, the topological structure of the parallel system can be flexibly configured to meet the requirements of different parallel algorithms. Meanwhile, by adding the redundant link and the fault detection circuit, when a single computing module or a single data link has a fault, the node forwarding table of the switching module is reconfigured to carry out topology reconstruction on the parallel system, so that the system has stronger fault tolerance and fault isolation capability.

In this embodiment, the task abstraction oriented to the heterogeneous computing resource abstraction generally includes a general CPU and various heterogeneous computing units, and accordingly, the tasks may be divided into software tasks and hardware tasks according to the types of the tasks, where the software tasks are defined as tasks running on a general processor, and the hardware tasks are defined as tasks running on the heterogeneous computing units. A complete application is composed of a series of tasks, including software tasks and hardware tasks, and calling relations can exist among the tasks. Compared with the common software task, the hardware task on the heterogeneous platform has the following characteristics:

1) the execution time of each hardware task is substantially fixed. The execution process of the hardware task can be divided into three phases: input data transmission, task execution and output data transmission. Wherein the task execution phase is cycle accurate and the time of the input data transfer and the output data transfer depends on the actual data transfer amount and data bandwidth. Applications on heterogeneous computing units that are suitable for acceleration typically satisfy one of two conditions: <1> streaming data application; <2> applications with small data size and computational complexity. The streaming data application usually adopts a mode of executing while transmitting, and the data transmission overhead is hidden in the execution process of the task. For the second kind of tasks, the time required for the task execution phase is usually much longer than the data transmission time, especially in the loosely-coupled heterogeneous platform architecture. The execution time of each hardware task can be considered to be substantially fixed. For streaming applications, such a conclusion can be simply generalized, and it can be considered that each amount of data processed is a task, and the whole streaming application is composed of continuous tasks of the same type, so that each hardware task can be regarded as a basically fixed execution time.

2) To ensure performance and schedulability, hardware tasks typically do not support task preemption. For software tasks, preemption of the software tasks is actually a task scheduling concept, different tasks use processor resources in different time slices according to a scheduling algorithm, and the contexts of the tasks need to be saved when the tasks are scheduled each time, wherein the contexts include information such as register values, stacks and the like. The preemption of the hardware task requires saving the hardware context, such as the value of the internal register of the heterogeneous computing unit, the execution state, and other information, and the overhead of saving the hardware context is usually much larger than that of the software context, depending on the complexity of the heterogeneous computing unit. Moreover, since the formats of the hardware context and the software context are not uniform, different mechanisms are required to be adopted when the task execution is resumed after the preemption. Due to the factors, the hardware task is high in cost for supporting preemption, so the hardware task usually does not support task preemption, that is, once a hardware task starts to execute, the heterogeneous computing unit is monopolized by the hardware task all the time from the time that the task sends data to the time that a computing result returns, and other tasks cannot obtain the use right of the heterogeneous computing unit.

3) There is no direct communication capability between hardware tasks. Direct communication of hardware tasks requires hardware support of a platform, and a direct hardware path is required between heterogeneous computing units, so that transmission of signals and data is completed. The Computing model on the platform satisfying this condition generally employs data flow Computing (Dataflow Computing) or Streaming Computing (Streaming Computing). These two computing models have now formed a relatively complete system, and are generally suitable for developing large applications for a particular function.

Compared with the prior art, the invention realizes heterogeneous computation based on artificial intelligence, adopts the design of a dual-redundancy exchange switch type interconnection system architecture, supports a system architecture of dynamic expansion and parallel processing, and comprises a hardware system architecture, a software platform design and an internal bus design. By adding the redundant link and the fault detection circuit, when a single computing module or a data link has a fault, the node forwarding table of the switching module is reconfigured to carry out topology reconstruction on the parallel system, so that the system has stronger fault tolerance and fault isolation capability.

For convenience of description, the above devices are described as being divided into various units by function, and are described separately. Of course, the functionality of the units may be implemented in one or more software and/or hardware when implementing the present application.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The application may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The application may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.

The memory may include forms of volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium.

Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.

The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.