1. A RRAM-based non-volatile configurable pull-up resistor network, characterized by: the circuit comprises n sub-circuits connected in parallel, namely, the sub-circuit 1 is connected in parallel with the sub-circuit n, wherein n is the number of configurable resistors connected in parallel; the circuit comprises an input port A, an output port B, an enable port EN, resistance configuration value ports K0-Kn, a power supply port VDD and a ground port GND; each sub-circuit comprises RRAMx, one end of the RRAMx is connected with one PMOS transistor of the first unit, the other end of the RRAMx is connected with one PMOS transistor of the second unit, the first unit and the second unit are isomorphs, namely, the first unit and the second unit have the same structure and respectively comprise two current-limiting resistors which are connected in parallel, one current-limiting resistor is connected with one group of PMOS transistors, and the other current-limiting resistor is connected with one group of NMOS transistors; one PMOS transistor in the group of PMOS transistors is connected with an enable EN and a power supply VDD, and the other PMOS transistor is connected with a configuration port Kx; one NMOS transistor of a group of NMOS transistors is connected to ground GND, signal BEN, and the other NMOS transistor is connected to configuration port Kx.

2. The RRAM-based non-volatile configurable pull-up resistor network of claim 1, wherein: the first PMOS transistor and the second PMOS transistor are connected to one end of a first current limiting resistor R1 in a group mode, the first NMOS transistor and the second NMOS transistor are connected to one end of a second current limiting resistor R2 in a group mode, the third PMOS transistor and the fourth PMOS transistor are connected to one end of a third current limiting resistor R3 in a group mode, and the third NMOS transistor and the fourth NMOS transistor are connected to one end of a fourth current limiting resistor R4 in a group mode;

the drain electrode of the first PMOS transistor is connected with the source electrode of the second PMOS transistor, the source electrode of the first PMOS transistor is connected with a power supply VDD, the grid electrode of the first PMOS transistor is connected with a signal EN, and the body of the first PMOS transistor is connected with the power supply VDD;

the drain electrode of the second PMOS transistor is connected with one end of the first current limiting resistor R1, the source electrode of the second PMOS transistor is connected with the drain electrode of the first PMOS transistor, the grid electrode of the second PMOS transistor is connected with the configuration port Kx, and the body of the second PMOS transistor is connected with the power supply VDD;

the drain electrode of the third PMOS transistor is connected with the source electrode of the fourth PMOS transistor, the source electrode of the third PMOS transistor is connected with a power supply VDD, the grid electrode of the third PMOS transistor is connected with a signal EN, and the body of the third PMOS transistor is connected with the power supply VDD;

the drain electrode of the fourth PMOS transistor is connected with one end of the third current-limiting resistor R3, the source electrode of the fourth PMOS transistor is connected with the drain electrode of the third PMOS transistor, the grid electrode of the fourth PMOS transistor is connected with a signal BKx, and the body of the fourth PMOS transistor is connected with a power supply VDD;

the drain electrode of the fifth PMOS transistor is connected with the port P of the RRAMx, the source electrode of the fifth PMOS transistor is connected with the body connection port A, and the grid electrode of the fifth PMOS transistor is connected with a signal BEN;

the drain electrode of the sixth PMOS transistor is connected with the port B, the source electrode and the body of the sixth PMOS transistor are connected with the port Q of the RRAMx, and the grid electrode of the sixth PMOS transistor is connected with the signal BEN;

the drain electrode of the first NMOS transistor is connected with the source electrode of the second NMOS transistor, the source electrode of the first NMOS transistor is connected with the ground GND, the grid electrode of the first NMOS transistor is connected with the signal BEN, and the body of the first NMOS transistor is connected with the ground GND;

the drain electrode of the second NMOS transistor is connected with one end of a second current limiting resistor R2, the source electrode of the second NMOS transistor is connected with the drain electrode of the first NMOS transistor, the grid electrode of the second NMOS transistor is connected with a configuration port Kx, and the body of the second NMOS transistor is connected with the ground GND;

the drain electrode of the third NMOS transistor is connected with the source electrode of the fourth NMOS transistor, the source electrode of the third NMOS transistor is connected with the ground GND, the grid electrode of the third NMOS transistor is connected with the signal BEN, and the body of the third NMOS transistor is connected with the ground GND;

the drain of the fourth NMOS transistor is connected with one end of a fourth current-limiting resistor R4, the source of the fourth NMOS transistor is connected with the drain of the third NMOS transistor, the gate of the fourth NMOS transistor is connected with a signal BKx, and the body of the fourth NMOS transistor is connected with the ground GND;

one end of the first current limiting resistor R1 is connected with the drain of the second PMOS transistor, and the other end is connected with the port P of RRAMx;

one end of the second current limiting resistor R2 is connected with the drain of the second NMOS transistor, and the other end is connected with the port P of the RRAMx;

one end of the third current limiting resistor R3 is connected with the drain electrode of the fourth PMOS transistor, and the other end is connected with the port Q of RRAMx;

one end of the fourth current limiting resistor R4 is connected to the drain of the fourth NMOS transistor, and the other end is connected to the port Q of RRAMx.

3. A RRAM-based non-volatile configurable pull-up resistor network in accordance with claim 2, wherein: a first inverter is included having an input coupled to configuration port Kx and an output coupled to signal BKx, with input configuration Kx passing through the first inverter to generate inverted configuration signal BKx.

4. A RRAM-based non-volatile configurable pull-up resistor network in accordance with claim 3, wherein: the inverter comprises a second inverter, wherein the input end of the second inverter is connected with an input enable EN, the output end of the second inverter is connected with a signal BEN, and the input enable EN generates an inversion enable signal BEN through the second inverter.

5. A RRAM-based non-volatile configurable pull-up resistor network according to claim 3 or 4, wherein: the inverter circuit of the first inverter or the second inverter comprises an inverter PMOS transistor and an inverter NMOS transistor, the source electrode and the body of the inverter PMOS transistor are connected with a power supply VDD, the drain electrode is connected with the drain electrode and the output end OUT of the inverter NMOS transistor, and the grid electrode is connected with the input end IN; the source and the body of the NMOS transistor of the inverter are connected with the ground GND, the drain is connected with the drain of the PMOS transistor and the output end OUT, and the grid is connected with the input end IN.

6. A RRAM-based non-volatile configurable pull-up resistor network in accordance with claim 2, wherein: the port P of the RRAMx is connected with the drain of the fifth PMOS transistor, the other end of the resistor R1 and the other end of the resistor R2; and the port Q of the RRAMx is connected with the source and the body of the sixth PMOS transistor, the other end of the resistor R3 and the other end of the resistor R4.

7. The RRAM-based non-volatile configurable pull-up resistor network of claim 1, wherein: the low resistance state resistance of RRAMx is slightly greater than the resistance of the resistor network required to be configured.

8. The RRAM-based non-volatile configurable pull-up resistor network of claim 1, wherein: the high resistance state resistance value of the RRAMx is not less than 100 times of the low resistance state resistance value.

9. The RRAM-based non-volatile configurable pull-up resistor network of claim 1, wherein: the ratio of the resistance value of the current limiting resistor to the resistance value of the RRAMx low resistance state is between 0.05 and 1.

Background

The configurable pull-up resistor network is a circuit network formed by connecting a plurality of resistors with different resistance values in series with PMOS transistors respectively and then in parallel, can provide the configurable pull-up resistor for an external circuit, and has a basic structure as shown in FIG. 1. The circuit is one of the key circuits of a high-speed serial interface circuit, and is widely applied to the current high-number data transmission integrated circuit. By modifying the configuration value of the resistor, the pull-up resistor of the terminal of the high-speed serial interface can be configured to be an accurate matching resistance value specified by a high-speed data transmission protocol such as 50 omega, 75 omega and the like. Due to differences in manufacturing process deviation and working conditions such as temperature and voltage, the same resistor network has different resistor configuration values when working in different integrated circuits, and the integrated circuit is often calibrated after being powered on to obtain a correct resistor configuration value.

As shown in fig. 2, a conventional configurable pull-up resistor network is provided. The circuit is formed by connecting 4 resistors R, R/2, R/4 and R/8 with half-reduced resistance values in sequence in series with PMOS transistors K0, K1, K2 and K3 respectively and then connecting the resistors in parallel. By changing the resistor configuration values, i.e. configuring the switching states of the PMOS transistors, the resistor network can be made to provide different resistance values from R/15 to R.

However, the current pull-up configurable resistance network cannot store the resistance configuration after the power of the integrated circuit is cut off, and the resistance calibration needs to be performed again after the power is restored to obtain the resistance configuration value. Because the calibration process is time-consuming, integrated circuits such as high-speed serial circuits using configurable pull-up resistor networks are slow to start.

Disclosure of Invention

Aiming at the technical problems in the prior art, the invention provides the bipolar RRAM-based nonvolatile configurable pull-up resistor network which is simple in structure, convenient to use and good in use effect.

In order to solve the technical problems, the invention adopts the following technical scheme:

a nonvolatile configurable pull-up resistance network based on a bipolar RRAM comprises n sub-circuits connected in parallel, namely, the n sub-circuits are formed by connecting sub-circuit 1 to sub-circuit n in parallel, wherein n is the number of the configurable resistors connected in parallel; the pull-up resistor network comprises an input port A, an output port B, an enable port EN, resistor configuration value ports K0-Kn, a power supply port VDD and a ground port GND. Each sub-circuit comprises RRAMx, one end of the RRAMx is connected with the first unit and one PMOS transistor, and the other end of the RRAMx is connected with the second unit and one PMOS transistor; the first unit and the second unit are isomorphs; the structure is basically the same, and the two current-limiting resistors are connected in parallel; one current-limiting resistor is connected with one group of PMOS transistors, and the other current-limiting resistor is connected with one group of NMOS transistors; one PMOS transistor in the group of PMOS transistors is connected with an enable EN and a power supply VDD, and the other PMOS transistor is connected with a configuration port Kx; one NMOS transistor of a group of NMOS transistors is connected to ground GND, signal BEN, and the other NMOS transistor is connected to configuration port Kx.

Preferably, the first PMOS transistor and the second PMOS transistor are connected to one end of the first current limiting resistor R1, and the first NMOS transistor and the second NMOS transistor are connected to one end of the second current limiting resistor R2. The third PMOS transistor and the fourth PMOS transistor are connected to one end of the third current limiting resistor R3, and the third NMOS transistor and the fourth NMOS transistor are connected to one end of the fourth current limiting resistor R4.

The drain electrode of the first PMOS transistor is connected with the source electrode of the second PMOS transistor, the source electrode of the first PMOS transistor is connected with a power supply VDD, the grid electrode of the first PMOS transistor is connected with a signal EN, and the body of the first PMOS transistor is connected with the power supply VDD.

The drain electrode of the second PMOS transistor is connected with one end of the first current limiting resistor R1, the source electrode of the second PMOS transistor is connected with the drain electrode of the first PMOS transistor, the grid electrode of the second PMOS transistor is connected with the configuration port Kx, and the body of the second PMOS transistor is connected with the power supply VDD.

The drain electrode of the third PMOS transistor is connected with the source electrode of the fourth PMOS transistor, the source electrode of the third PMOS transistor is connected with a power supply VDD, the grid electrode of the third PMOS transistor is connected with a signal EN, and the body of the third PMOS transistor is connected with the power supply VDD.

The drain of the fourth PMOS transistor is connected with one end of the third current limiting resistor R3, the source of the fourth PMOS transistor is connected with the drain of the third PMOS transistor, the gate of the fourth PMOS transistor is connected with the signal BKx, and the body of the fourth PMOS transistor is connected with the power supply VDD.

The drain of the fifth PMOS transistor is connected with the port P of RRAMx, the source and the body of the fifth PMOS transistor are connected with the port A, and the gate of the fifth PMOS transistor is connected with the signal BEN.

The drain of the sixth PMOS transistor is connected to port B, the source and bulk of the sixth PMOS transistor are connected to port Q of RRAMx, and the gate of the sixth PMOS transistor is connected to signal BEN.

The drain electrode of the first NMOS transistor is connected with the source electrode of the second NMOS transistor, the source electrode of the first NMOS transistor is connected with the ground GND, the grid electrode of the first NMOS transistor is connected with the signal BEN, and the body of the first NMOS transistor is connected with the ground GND.

The drain of the second NMOS transistor is connected to one end of the second current limiting resistor R2, the source of the second NMOS transistor is connected to the drain of the first NMOS transistor, the gate of the second NMOS transistor is connected to the configuration port Kx, and the body of the second NMOS transistor is connected to the ground GND.

The drain electrode of the third NMOS transistor is connected with the source electrode of the fourth NMOS transistor, the source electrode of the third NMOS transistor is connected with the ground GND, the grid electrode of the third NMOS transistor is connected with the signal BEN, and the body of the third NMOS transistor is connected with the ground GND.

The drain of the fourth NMOS transistor is connected to one end of the fourth current limiting resistor R4, the source of the fourth NMOS transistor is connected to the drain of the third NMOS transistor, the gate of the fourth NMOS transistor is connected to the signal BKx, and the body of the fourth NMOS transistor is connected to the ground GND.

One end of the first current limiting resistor R1 is connected to the drain of the second PMOS transistor, and the other end is connected to the port P of the RRAM.

One end of the second current limiting resistor R2 is connected to the drain of the second NMOS transistor, and the other end is connected to the port P of the RRAM.

One end of the third current limiting resistor R3 is connected to the drain of the fourth PMOS transistor, and the other end is connected to the port Q of the RRAM.

One end of the fourth current limiting resistor R4 is connected to the drain of the fourth NMOS transistor, and the other end is connected to the port Q of the RRAM.

Preferably, the first inverter has an input connected to configuration port Kx and an output connected to signal BKx. The input configuration Kx generates an inverted configuration signal BKx through a first inverter.

Preferably, the second inverter has an input terminal connected to the input enable EN and an output terminal connected to the signal BEN. The input enable EN generates the inverted enable signal BEN through the second inverter.

Preferably, the port P of the RRAM connects the drain of the fifth PMOS transistor, the other end of the resistor R1, and the other end of the resistor R2. The port Q of the RRAM connects the source and body of the sixth PMOS transistor, the other end of the resistor R3, and the other end of the resistor R4.

Preferably, the inverter circuit includes one inverter PMOS transistor and one inverter NMOS transistor, as shown in fig. 5. The source and the bulk of the PMOS transistor of the inverter are connected with a power supply VDD, the drain is connected with the drain of the NMOS transistor of the inverter and an output end OUT, and the grid is connected with an input end IN. The source and the body of the NMOS transistor of the inverter are connected with the ground GND, the drain is connected with the drain of the PMOS transistor and the output end OUT, and the grid is connected with the input end IN.

Preferably, the low resistance state of RRAMx is slightly larger than the desired configuration of the resistor network.

Preferably, the high resistance state value of RRAMx is not less than 100 times the low resistance state value.

Preferably, the ratio of the resistance values of the first current limiting resistor R1, the second current limiting resistor R2, the third current limiting resistor R3 and the fourth current limiting resistor R4 to the resistance value of RRAMx in the low resistance state is between 0.05 and 1.

Compared with the prior art, the nonvolatile configurable pull-up resistor network based on the bipolar RRAM has the advantages of simple structure, convenience in use and good use effect, can still maintain the configured resistor during power failure and after power-on again, does not need a recalibration process, and can greatly accelerate the starting speed of integrated circuits such as high-speed serial circuits and the like using the configurable pull-up resistor network.

Drawings

Fig. 1 is a schematic diagram of a configurable pull-up resistor network.

Fig. 2 is a schematic diagram of the structural principle of a conventional configurable pull-up resistor network.

Fig. 3 is a schematic diagram of the structural principle of the configurable pull-up resistor network in a specific application example of the invention.

Fig. 4 is a schematic diagram of the structural principle of the sub-circuit x in the specific application example of the present invention.

FIG. 5 is a schematic diagram of the structure of an inverter in a specific application example of the present invention.

Detailed Description

The invention will be described in further detail below with reference to the drawings and specific examples.

A RRAM (Resistive random access Memory) is a nonvolatile Memory device that stores data information by changing its own resistance, and has two ports. The bipolar RRAM refers to a RRAM having a characteristic that the RRAM is in a high resistance state before a certain voltage is applied between two ports for the first time after manufacturing the RRAM, and the direction of the first applied voltage is in a positive voltage direction. When a certain positive voltage is applied between the two ports of the RRAM, the resistance of the RRAM is reduced, and a low-resistance state is presented; when a certain negative voltage is applied between two ports of the RRAM, the resistance of the RRAM increases, and a high resistance state is presented. After power down, the resistance of the bipolar RRAM remains unchanged.

As shown in fig. 3, based on the above principle, the present invention provides a nonvolatile configurable pull-up resistor network based on a bipolar RRAM, which includes n sub-circuits connected in parallel, that is, the sub-circuit 1 is connected in parallel to the sub-circuit n, where n is the number of configurable resistors connected in parallel; the pull-up resistor network comprises an input port A, an output port B, an enable port EN, resistor configuration value ports K0-Kn, a power supply port VDD and a ground port GND.

As shown in fig. 4, each sub-circuit includes RRAMx having one end connected to the first cell and one PMOS transistor and the other end connected to the second cell and one PMOS transistor; the first unit and the second unit are isomorphs, namely the structures are basically the same, and each unit comprises two current-limiting resistors connected in parallel, wherein one current-limiting resistor is connected with one group of PMOS transistors, and the other current-limiting resistor is connected with one group of NMOS transistors. One PMOS transistor in the group of PMOS transistors is connected with an enable EN and a power supply VDD, and the other PMOS transistor is connected with a configuration port Kx; one NMOS transistor of a group of NMOS transistors is connected to ground GND, signal BEN, and the other NMOS transistor is connected to configuration port Kx.

In the present embodiment, each sub-circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first current limiting resistor R1, a second current limiting resistor R2, a third current limiting resistor R3, a fourth current limiting resistor R4, a first inverter, a second inverter, and RRAMx. The ports of each subcircuit comprise a power supply VDD, a ground GND, an enable EN, a configuration port Kx, an input port A and an output port B. x is any natural number from 1 to n.

The first PMOS transistor and the second PMOS transistor are connected to one end of the first current limiting resistor R1, and the first NMOS transistor and the second NMOS transistor are connected to one end of the second current limiting resistor R2. The third PMOS transistor and the fourth PMOS transistor are connected to one end of the third current limiting resistor R3, and the third NMOS transistor and the fourth NMOS transistor are connected to one end of the fourth current limiting resistor R4.

The drain electrode of the first PMOS transistor is connected with the source electrode of the second PMOS transistor, the source electrode of the first PMOS transistor is connected with a power supply VDD, the grid electrode of the first PMOS transistor is connected with a signal EN, and the body of the first PMOS transistor is connected with the power supply VDD.

The drain electrode of the second PMOS transistor is connected with one end of the first current limiting resistor R1, the source electrode of the second PMOS transistor is connected with the drain electrode of the first PMOS transistor, the grid electrode of the second PMOS transistor is connected with the configuration port Kx, and the body of the second PMOS transistor is connected with the power supply VDD.

The drain electrode of the third PMOS transistor is connected with the source electrode of the fourth PMOS transistor, the source electrode of the third PMOS transistor is connected with a power supply VDD, the grid electrode of the third PMOS transistor is connected with a signal EN, and the body of the third PMOS transistor is connected with the power supply VDD.

The drain of the fourth PMOS transistor is connected with one end of the third current limiting resistor R3, the source of the fourth PMOS transistor is connected with the drain of the third PMOS transistor, the gate of the fourth PMOS transistor is connected with the signal BKx, and the body of the fourth PMOS transistor is connected with the power supply VDD.

The drain of the fifth PMOS transistor is connected with the port P of RRAMx, the source and the body of the fifth PMOS transistor are connected with the port A, and the gate of the fifth PMOS transistor is connected with the signal BEN.

The drain of the sixth PMOS transistor is connected to port B, the source and bulk of the sixth PMOS transistor are connected to port Q of RRAMx, and the gate of the sixth PMOS transistor is connected to signal BEN.

The drain electrode of the first NMOS transistor is connected with the source electrode of the second NMOS transistor, the source electrode of the first NMOS transistor is connected with the ground GND, the grid electrode of the first NMOS transistor is connected with the signal BEN, and the body of the first NMOS transistor is connected with the ground GND.

The drain of the second NMOS transistor is connected to one end of the second current limiting resistor R2, the source of the second NMOS transistor is connected to the drain of the first NMOS transistor, the gate of the second NMOS transistor is connected to the configuration port Kx, and the body of the second NMOS transistor is connected to the ground GND.

The drain electrode of the third NMOS transistor is connected with the source electrode of the fourth NMOS transistor, the source electrode of the third NMOS transistor is connected with the ground GND, the grid electrode of the third NMOS transistor is connected with the signal BEN, and the body of the third NMOS transistor is connected with the ground GND.

The drain of the fourth NMOS transistor is connected to one end of the fourth current limiting resistor R4, the source of the fourth NMOS transistor is connected to the drain of the third NMOS transistor, the gate of the fourth NMOS transistor is connected to the signal BKx, and the body of the fourth NMOS transistor is connected to the ground GND.

One end of the first current limiting resistor R1 is connected to the drain of the second PMOS transistor, and the other end is connected to the port P of the RRAM.

One end of the second current limiting resistor R2 is connected to the drain of the second NMOS transistor, and the other end is connected to the port P of the RRAM.

One end of the third current limiting resistor R3 is connected to the drain of the fourth PMOS transistor, and the other end is connected to the port Q of the RRAM.

One end of the fourth current limiting resistor R4 is connected to the drain of the fourth NMOS transistor, and the other end is connected to the port Q of the RRAM.

The first inverter has an input connected to configuration port Kx and an output connected to signal BKx. The input configuration Kx generates an inverted configuration signal BKx through a first inverter.

The input end of the second inverter is connected with the input enable EN, and the output end of the second inverter is connected with the signal BEN. The input enable EN generates the inverted enable signal BEN through the second inverter.

The port P of the RRAM is connected to the drain of the fifth PMOS transistor, the other end of the resistor R1, and the other end of the resistor R2.

The port Q of the RRAM connects the source and body of the sixth PMOS transistor, the other end of the resistor R3, and the other end of the resistor R4.

In a specific application example, the inverter circuit preferably includes an inverter PMOS transistor and an inverter NMOS transistor, as shown in fig. 5. The source and the bulk of the PMOS transistor of the inverter are connected with a power supply VDD, the drain is connected with the drain of the NMOS transistor of the inverter and an output end OUT, and the grid is connected with an input end IN. The source and the body of the NMOS transistor of the inverter are connected with the ground GND, the drain is connected with the drain of the PMOS transistor and the output end OUT, and the grid is connected with the input end IN.

In a specific application example, the low resistance state resistance of RRAMx is preferably slightly greater than the desired configuration of the resistor network.

In a specific application example, the high resistance state value of RRAMx is preferably not less than 100 times the low resistance state value.

In a specific application example, the ratio of the resistance values of the first current limiting resistor R1, the second current limiting resistor R2, the third current limiting resistor R3 and the fourth current limiting resistor R4 to the resistance value of the RRAMx low resistance state is preferably between 0.05 and 1.

According to the non-volatile configurable pull-up resistor network, RRAM of each internal sub-circuit is in a high-resistance state before data is written for the first time, and the sub-circuit can be considered to be disconnected from the resistor network because the RRAM high-resistance state resistance is far larger than the required configured resistance of the resistor network. In order to ensure the correct subsequent writing of the configuration resistor, the RRAM of each sub-circuit needs to be initialized with 1.

RRAMx write "1" initialization procedure for sub-circuit x is as follows, all sub-circuits can be initialized at the same time. x is any natural number from 1 to n.

Step S101: the input enable EN is set to a high level (logic "1"), and the input configuration Kx is set to a high level (logic "1") or a low level (logic "0").

Step S102: power up is applied to power supply VDD. At this time, the first PMOS transistor and the third PMOS transistor are turned off, the first NMOS transistor and the third NMOS transistor are turned off, the fifth PMOS transistor and the sixth PMOS transistor are turned on, and since RRAMx is in a high resistance state, the sub-circuit x is disconnected from the resistor network.

Step S103: input configuration Kx is set to high (logic "1").

Step S104: the input enable EN is set to be low level, and the time T is kept. At this time, since EN is low (logic "0"), the first PMOS transistor is turned on, the second PMOS transistor is turned off, the first NMOS transistor and the second NMOS transistor are turned on, the third PMOS transistor and the fourth PMOS transistor are turned on, the third NMOS transistor is turned on, and the fourth NMOS transistor is turned off, so that the port P of RRAMx is grounded to GND through the second current limiting resistor R2, the port Q of RRAM is connected to the power supply VDD through the third current limiting resistor R3, RRAM is changed from a high resistance state to a low resistance state, and the positive voltage direction is Q to P.

Step S105: and setting the input enable EN to be high level, and finishing initialization. At this time, the first PMOS transistor and the third PMOS transistor are turned off, the first NMOS transistor and the third NMOS transistor are turned off, the fifth PMOS transistor and the sixth PMOS transistor are turned on, and since the RRAM is in a low resistance state, the sub-circuit x is connected to the resistance network.

The working process of the nonvolatile configurable pull-up resistor network is as follows:

for the sub-circuit x, if the configuration signal Kx is at a high level (logic "1"), when the enable signal EN is changed from a high level to a low level and maintained for the holding time T, the first PMOS transistor is turned on, the second PMOS transistor is turned off, the first NMOS transistor and the second NMOS transistor are turned on, the third PMOS transistor and the fourth PMOS transistor are turned on, the third NMOS transistor is turned on, and the fourth NMOS transistor is turned off.

The port P of the RRAM is grounded GND through a second current limiting resistor R2, the port Q of the RRAM is connected with a power supply VDD through a third current limiting resistor R3, the voltage direction is Q to P, and the voltage direction is consistent with the positive voltage direction, so that the RRAM is changed into a low-resistance state;

then, after the enable signal EN is converted from the low level to the high level, the first PMOS transistor and the third PMOS transistor are turned off, the first NMOS transistor and the third NMOS transistor are turned off, the fifth PMOS transistor and the sixth PMOS transistor are turned on, and the sub-circuit x is connected to the resistor network.

For the sub-circuit x, if the configuration signal Kx is at a low level (logic "0"), when the enable signal EN is changed from a high level to a low level and maintained for the holding time T, the first PMOS transistor and the second PMOS transistor are turned on, the first NMOS transistor is turned on, the second NMOS transistor is turned off, the third PMOS transistor is turned on, the fourth PMOS transistor is turned off, the third NMOS transistor and the fourth NMOS transistor are turned on, so that the port P of the RRAM is connected to the power supply VDD through the first current limiting resistor R1, the port Q of the RRAM is connected to the ground GND through the fourth current limiting resistor R4, the voltage direction is P to Q, and the voltage direction is opposite to the positive voltage direction, the RRAM is at a high resistance state; and after the enable signal EN is converted from low level to high level, the first PMOS transistor and the third PMOS transistor are cut off, the first NMOS transistor and the third NMOS transistor are cut off, the fifth PMOS transistor and the sixth PMOS transistor are switched on, and the sub-circuit x is connected to the resistance network.

If the circuit is powered off, the resistance of the RRAM in each sub-circuit is kept unchanged, and the resistance network can still keep the correct resistance value after the circuit is powered on.

The low level holding time T of the enable signal EN is a time to ensure a correct transition of the resistive state of the RRAM.

The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may be made by those skilled in the art without departing from the principle of the invention.