The SRAM dynamic array power supply control circuit is characterized by comprising at least one output voltage selector, wherein the output voltage selector is composed of a first MOS (metal oxide semiconductor) tube and a second MOS tube which are connected through a current output end, and the current input end of the first MOS tube is connected with the second MOS tubeFirst level terminal V_DDThe current input end of the second MOS tube is connected with a second level end V_CCAnd the current output ends of the two MOS tubes are used as the output ends of the output voltage selector and are connected with a power line of the SRAM storage unit.

2. The SRAM dynamic array power control circuit of claim 1, comprising a first output voltage selector, a second output voltage selector, and a third output voltage selector,

in the first output voltage selector, the grid electrode of the first MOS tube is connected with the grid electrode of the second MOS tube through an inverter, and the grid electrode of the first MOS tube is also connected with the output end of a first AND gate (133);

in the second output voltage selector, the grid of the first MOS tube is connected with the output end of the first NAND gate (136); the grid of the second MOS tube is connected with the output end of a second NAND gate (137),

in the third output voltage selector, the grid of the first MOS tube is connected with the output end of a third NAND gate (138); the output end of a fourth NAND gate (139) of the grid of the second MOS tube is connected,

the first input end of the first AND gate (133) is connected with a word line WL and the second input end of the second AND gate (135), the write command input end is connected with the second input end of the first AND gate (133) through an inverter, and the write command input end is also connected with the first input end of the second AND gate;

the output end of the second AND gate (135) is connected with the second input end of the first NAND gate (136), the second input end of the second NAND gate (137), the second input end of the third NAND gate (138) and the second input end of the fourth NAND gate (139);

the first input end of the first NAND gate (136), the first input end of the second NAND gate (137), the first input end of the third NAND gate (138) and the first input end of the fourth NAND gate (139) are respectively connected with respective configuration points.

3. The SRAM dynamic array power control circuit of claim 1, wherein the first MOS transistor and the second MOS transistor are PMOS transistors.

4. The SRAM dynamic array power control circuit of claim 3, wherein the substrate of each MOS transistor is coupled to a respective source terminal.

Background

In a common 6-transistor memory cell, in order to ensure the stability of the read operation without changing the data stored in the read cell, the internal node level of the memory cell must be kept below the inversion threshold of the inverter, so the access transistor is sufficiently weak; in a write operation, the access pipe is strong enough to flip the inverter in the memory cell to change the data stored therein. In order to ensure both read stability and write stability, the size of the MOS transistor in the memory cell needs to be carefully selected.

The threshold voltage variation due to random doping fluctuations, in addition to the large number of cells on the chip, and the perturbation is increasing. This disturbance affects the stability of the read, write, and retention operations of the SRAM.

In order to solve the problem of reading, writing and remaining margin which is very easy to be disturbed, the following three methods are commonly used in the prior art:

(1) the structure of the traditional storage unit is changed into a more stable 7-tube or 8-tube structure, but the method can greatly increase the area and power consumption, and is particularly obvious in large-capacity SRAM;

(2) read and write assist circuits are added, but these circuits can compromise other performance of the circuit while improving single performance. For example, document [1] proposes a word line step-down driving circuit to assist the read operation, but the read current of the cell is greatly reduced, so that the chip performance is limited;

(3) double-rail power supply, and document [2] proposes a double-rail power supply circuit to assist read-write operation, but does not propose a specific circuit implementation; document [3] proposes a dual-rail power supply circuit in which binary coding changes the power supply of a cell, but in which the stability of the memory cell is reduced.

Reference documents:

[1]M.Yabuuchi，et al.A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations.[C]//IEEE International Solid-State Circuits Conference2007.18.3

[2]J.Pille,et al,Implementation of the CELL Broadband Engine in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V.[C]//IEEE International Solid-State Circuits Conference2007.18.1

[3]H.Mair,et al,A 65-nm Mobile Multimedia Applications Processor with an Adaptive Power Management Scheme to Compensate for Variations.[J]Symposium on VLSI Circuit Digest.2007.21-5

disclosure of Invention

The invention aims to solve the technical problem of providing an SRAM dynamic array power supply control circuit with the characteristics of high stability and low power consumption.

The technical scheme adopted by the invention for solving the technical problems is that the SRAM dynamic array power supply control circuit is characterized by comprising at least one output voltage selector, wherein the output voltage selector is connected with the output voltage selectorThe output voltage selector is composed of a first MOS tube and a second MOS tube which are connected with each other at a current output end, wherein the current input end of the first MOS tube is connected with a first level end V_DDThe current input end of the second MOS tube is connected with a second level end V_CCAnd the current output ends of the two MOS tubes are used as the output ends of the output voltage selector and are connected with a power line of the SRAM storage unit.

Further, the SRAM dynamic array power supply control circuit comprises a first output voltage selector, a second output voltage selector and a third output voltage selector,

in the first output voltage selector, the grid electrode of the first MOS tube is connected with the grid electrode of the second MOS tube through an inverter, and the grid electrode of the first MOS tube is also connected with the output end of the first AND gate;

in the second output voltage selector, the grid of the first MOS tube is connected with the output end of the first NAND gate; the grid of the second MOS tube is connected with the output end of the second NAND gate,

in the third output voltage selector, the grid of the first MOS tube is connected with the output end of the third NAND gate; the output end of the fourth NAND gate of the grid of the second MOS tube is connected,

the first input end of the first AND gate is connected with a word line WL and the second input end of the second AND gate, the write command input end is connected with the second input end of the first AND gate through an inverter, and the write command input end is also connected with the first input end of the second AND gate;

the output end of the second AND gate is connected with the second input end of the first NAND gate, the second input end of the second NAND gate, the second input end of the third NAND gate and the second input end of the fourth NAND gate;

the first input end of the first NAND gate, the first input end of the second NAND gate, the first input end of the third NAND gate and the first input end of the fourth NAND gate are respectively connected with respective configuration points.

Furthermore, the first MOS tube and the second MOS tube are both PMOS tubes.

The invention provides a dynamic array power supply control circuit. During read operation, the power supply V of the memory array_CCBRAMUsing a high voltage V_DD(ii) a In a write operation, bySelection of configuration points, V_CCBRAMIs biased to be between V_DDAnd a low voltage V_CCThe level between the two circuits reduces the driving capability of the phase inverter in the memory cell and can ensure that the unselected cells can normally keep internal data; in the hold state, V_CCBRAMBy using V_CC. In addition, the invention adopts the multi-threshold CMOS combined design technology, so that the invention improves the performance and reduces the power consumption. The current power supply voltage of the array is determined by the operation mode (reading, writing and maintaining) of the SRAM, the unit current of reading operation is not reduced, the stability can be improved, the power consumption is reduced, and the portability is good.

Drawings

Fig. 1 is a circuit diagram of embodiment 1 of the present invention.

Fig. 2 is a timing diagram of the present invention.

FIG. 3 is V_CCBRAMSchematic diagram of configurable voltages.

Fig. 4 is a circuit diagram of embodiment 2 of the present invention.

Fig. 5 is a circuit diagram of embodiment 3 of the present invention.

Fig. 6 is a circuit diagram of embodiment 4 of the present invention.

Detailed Description

Example 1

Fig. 1 shows the connection relationship and the hierarchical structure of two storage units 101 and 102. Each storage cell holds a bit of data, connected to a corresponding complementary bit line. Cell 101 corresponds to bit lines 119(BL <0>), 120 (BLN <0 >); cell 102 corresponds to bit lines 121(BL < n >), 122(BLN < n >). The memory cells depicted in the schematic represent any number of cells as 101, 102. The number of memory cells connected on a word line indicates that a word has several bytes (n +1 are shown in the figure), and does not affect the circuit implementation.

Each memory cell includes a pair of access transistors for reading or writing data, and a pair of cross-coupled inverters formed of four MOS transistors for holding data. In the unit 101, the four MOS transistors are transistors 103, 104, 105, and 106; in the cell 102, the four MOS transistors are transistors 109, 110, 111, and 112, respectively. Taking unit 101 as an example: transistor 103(PMOS) device and transistor 104(NMOS) form a first inverter, and transistor 105(PMOS) device and transistor 106 (NMOS) form a second inverter. The input and the output of the two inverters are connected to form a latching structure. The nodes inside the latch structure are named Q, QB, respectively, and the internal connection lines are named 115, 116, respectively. As shown in the figure, the cell 102 has a similar structure. Each memory cell has a pair of access transistors connecting an internal node and a bit line, and in the cell 101, the pair of MOS transistors are transistors 107 and 108; in cell 102, the pair of MOS transistors are transistors 113 and 114, respectively. The gate terminals of the access pipes 107, 108, 113, 114 are connected to a common word line WL labeled 147.

The source terminal of the PMOS transistor of the inverter in the memory cell is not always connected to the supply voltage V in the conventional memory cell manner_DD(130 in the figure) but is connected to a special voltage V_CCBRAMDesignated 123 in the figure. In order to prevent the substrate bias effect, the substrates of all the MOS tubes are connected to the respective source terminal voltage.

Device 132 is an inverter having as its input a WRITE signal (WRITE command input) labeled 146, the output of which is connected as an input to the first and gate 133 along with the word line WL signal. An output terminal 140 of the first and gate 133 is connected to a gate terminal of the transistor 124 (first MOS transistor) and an input terminal of the inverter 134. The source terminal of transistor 124 is connected to a low voltage V_CCLabeled 131 in the figure; the source terminal of the transistor 125 (second MOS transistor) is connected to the high voltage V_DDAnd a gate terminal is connected to the output 141 of the inverter 134. Signals of the WRITE commands WRITE and WL are input to the second and gate 135. The outputs of the 4 nand gate devices (136, 137, 138, 139) and the and gate 135 are connected, respectively having configuration points OE0, OE1, OE2, OE3, the outputs being connected to the gate terminals of the transistors 126, 127, 128, 129, respectively. The source terminals of transistors 126 and 128 are connected to V_CC(ii) a The source terminals of transistors 127 and 129 are connected to V_DD. By selecting different configurations OE [0: 3]]Can be variably connected to V_CCOr V_DDOf the transistors of (2) so that V_CCBRAMIs biased to V_DDAnd V_CCIn betweenLevel, hereinafter connected to V_DDThe PMOS tube is PV_DDIs connected to V_CCThe PMOS tube is PV_CC。

In a read operation, both bit lines are initially floating high, WL is raised, the WRITE signal remains low, transistor 125 is turned on, V_CCBRAMIs connected to V_DD. Without loss of generality, assume that Q is initially 0, and thus QB is initially 1. Taking unit 101 as an example: when WL goes high, transistor 104 pulls down bit line BL through transistor 107<0>. At the same time, the voltage at the point Q tends to rise due to the current injected by the transistor 107, but this rising voltage is not sufficient to flip the second inverter composed of the transistors 105 and 106.

In the hold operation, both WL and WRITE signals are held low, and the AND gate 133 outputs a low level, so that the transistor 124 is turned on, V_CCBRAMIs connected to V_CC。

In a WRITE operation, both WL and WRITE signals are asserted, and AND gate 133 outputs a low level, so that transistor 124 is turned on and connected to V_CC(ii) a At the same time, the AND gate 135 outputs a high level, so the NAND gate with the OE configuration point high outputs a low level, and the corresponding PMOS is turned on. By changing the point of deployment, PV_DDAnd PV_CCThe gate width ratio of (a) is changed. From V_DDFlow direction V_CCCan be converted into V according to the transconductance ratio thereof_CCBRAMBiased at V_DDAnd V_CCNine voltage values in between. Although the gate width ratio is [0: 3]]、[0:2]、[0:1]When, V_CCBRAMThe voltage values are the same, but the currents which can be provided for the array are different in magnitude, the OE configuration needs to be adjusted according to actual measurement conditions, and the grid width ratio is [ 1: 1]、[2:2]The same applies.

In conventional architectures, if one bit line is to be written into a large number of cells, the bit line driver will not be able to supply the required current. Furthermore, the current required for a large number of cell flips may exceed the limits that the power supply can provide due to voltage drop, current density, etc. By lowering V_CCBRAMThe following two objectives can be achieved: firstly, the weak access pipe in the storage unit can easily turn over the inverter; second, the transient current required to change the value of a memory cell can be significantly reduced. When V is_CCBRAMIs lower than the threshold voltages of NMOS and PMOS in the inverter, cell flipping becomes abnormally easy. However, in order to prevent other cells from being disturbed and erroneously flipped, the transistor 124 is fixedly connected to V during the write operation of the present invention_CC。

The CMOS combined design of the multi-threshold tube comprises the following steps:

NMOS transistors of the logic gates 133, 134, 136, 137, 138 and 139 adopt low-threshold transistors to speed up PV_DDAnd PV_CCConducting (all low threshold tubes); the PMOS tube in the transistor adopts a high-threshold tube to reduce leakage current; meanwhile, all the memory cells in the array circuit adopt high-threshold tubes to reduce power consumption.

Most processes change the threshold by twice or three times the thickness of the oxide layer, and the process of the invention changes the threshold by threshold bias, namely, adjusting the ion implantation concentration of the channel of a process device.

Fig. 2 shows the configuration signals OE [0: and 3, a read, write and hold operation timing chart of the circuit is 0100.

During the time period 0-t 1, the circuit is in hold state, only transistor 124 is on, V_CCBRAMAt a low voltage V_CC(ii) a At t1, the WRITE enable WRITE goes high, but since word line WL is not yet turned on, V_CCBRAMStill maintain a low voltage V_CC；

At t2, when the word line WL goes high, the BL line goes high, the circuit enters a write "1" operation, the transistor 124 remains on, and the transistor 143 corresponding to the OE1 enters an on state, so the array power supply V_CCBRAMA voltage of V_DDAnd V_CCIntermediate level ofThe phase inverter is relatively weak, data is successfully written in through the access pipe, the voltage of the QB point is reduced to 0, and the voltage of the Q point is increased to the high level of the storage unit at the moment

At t3, WL is turned offTransistor 143 is turned off, and only transistors 124 and V are turned on_CCAre connected to each other by V_CCBRAMDown to a low voltage V_CC；

At t4, WL turns on again, BL line is low, circuit enters write "0" operation, transistors 124 and 143 are in conduction, V_CCBRAMIs composed ofThe phase inverter is relatively weak, data is successfully written in through the access tube, the voltage of a point Q is reduced to 0, and the voltage of a point QB is increased to the high level of the storage unit at the moment

At t5, word line WL is turned off and transistor 143 is turned off, with only transistors 124 and V_CCAre connected to each other by V_CCBRAMDown to a low voltage V_CC；

At t6, the WRITE signal is turned off, the circuit enters a hold state, only transistor 124 is still on, and V_CCBRAMMaintaining a low voltage V_CC(ii) a Then both bit lines BL, BLN enter a pre-charge state, both rising to V_DDA voltage;

at t7, WL is turned on, WRITE is still in the OFF state, transistor 124 is turned off, inverter 134 outputs LOW, transistor 125 is turned on, V_CCBRAMIs connected to V_DDThe circuit enters a read state and a high level stored on QB is maintained by the hold stageIs raised to V_DD. The low level "0" stored on Q is read onto bit line BL, BL falls to 0, the high level stored on QB is read onto bit line BLN, BLN holds V_DDA voltage.

Taking the operation as an example, the average power consumption of the circuit adopting the invention is reduced by 10.2% compared with the average power consumption of the circuit adopting the traditional single-rail power supply, and it can be seen that although the power supply part of the power supply mostly adopts a low-threshold tube, the increase of the power consumption can be controlled by a high-threshold tube used in cooperation with the low-threshold tube.

Because the strength and the weakness of the access pipe do not influence the writing operation any more, the size of the access pipe can be made small enough, thereby providing larger reading operation margin, reducing the parasitic capacitance on one word line and accelerating the response speed of the memory unit.

FIG. 3 shows a view of V in the present invention_CCBRAMAlthough PV_DDAnd PV_CCHas different bias voltages of gate terminal and substrate, but V_CCBRAMAlmost proportional to the gate width ratio. Due to V_CCBRAMThe voltage is not affected by system variation because the grid width ratio of the parallel PMOS tubes is determined.

Example 2

Referring to the circuit shown in FIG. 4, the array power supply is lowered to a low voltage V only during a WRITE operation, i.e., both WL and WRITE signals are high_CCWhile in the hold and read operation, the array power supply is V_DD。

Example 3

Referring to fig. 5, another implementation of the circuit is shown, which differs in that during a write operation, the power supply of the circuit array is floating, and the write operation is very easy, but this implementation makes the internal nodes of the memory cells very vulnerable to disturbance by other signals, which may cause false flips.

Example 4

Referring to fig. 6, under any operation, the array power supply size can be self-configured according to the test result, and the difference from the circuit shown is that the array power supply for the read operation and the hold operation cannot be fixed. It is proposed that with the illustrated circuit, the voltages for the read operation and the hold operation are fixed, and the occurrence of a malfunction can be prevented.

The principles of the present invention may also be applied to varying the word line voltage level to ensure the correctness of the operation, and will not be described in detail herein.