1. An integrated circuit comprising a top layer (1), characterized in that: the lower wall of the top layer (1) is fixedly connected with four insulating layers (2), the lower wall of the insulating layer (2) at the bottom is fixedly connected with a substrate (3), a base library (4) is installed in the top layer (1), a metal core wire (5) is fixedly connected in the insulating layer (2) at the upper part, an active shield (6) is installed in the insulating layer (2) at the bottom, and an IC component (7) is installed in the substrate (3);

the top layer (1), the insulating layer (2) and the substrate (3) are used for providing a safe installation space for each functional component of the integrated circuit;

the base class library (4) supports various operation common programming operations and is used for providing a common programming framework for various algorithm devices of the IC component (7) and the active shielding (6);

the metal core wire (5) is used for electrically connecting all functional parts of the integrated circuit, so that information transmission is facilitated;

the active mask (6) is used to inject a random bit sequence in the top of the IC and to check that the random bit sequence arrives after passing through the functional components of the integrated circuit, verifying the dense wires of circuit integrity;

the IC component (7) is used for encrypting and storing sensitive data and implementing security protection.

2. An integrated circuit according to claim 1, wherein: the IC component (7) comprises a shield controller (8), the shield controller (8) comprising an uncovering unit (9) and a masking unit (10).

3. An integrated circuit according to claim 1, wherein: the output end of the active shield (6) is connected with the input end of a shield controller (8), and the output end of the shield controller (8) is connected with the input end of the active shield (6).

4. An integrated circuit according to claim 1, wherein: the input end of the shielding controller (8) is connected with a true random number generator (11), the output end of the shielding controller (8) is provided with an A public key (13), the output end of the A public key (13) is connected with an exclusive-OR gate (15), the input end of the shielding controller (8) is connected with a key storage device (12), the output end of the key storage device (12) is provided with a B public key (14), the output end of the B public key (14) is connected with the input end of the exclusive-OR gate (15), the output end of the exclusive-OR gate (15) is connected with a data processor (17), the output end of the data processor (17) is connected with a central processor (18), the output end of the central processor (18) is connected with the input end of the data processor (17), the output end of the data processor (17) is connected with an encryption memory (16), the output of the encryption memory (16) is connected to the input of a data processor (17), the exclusive-or gate (15) is used for performing an exclusive-or operation, the true random number generator (11) is used for providing the true random bits (22) to the masking controller (8), the data processor (17) is used for encrypting the content of the encryption memory (16) by using an encryption key and decrypting the content of the encryption memory (16) by using a corresponding decryption key, the encryption memory (16) is used for storing an a public key (13) and a B public key (14), and the central processor (18) is capable of operating and controlling the data processor (17).

5. An integrated circuit according to claim 2, wherein: the input end of the exposing unit (9) is connected with a protection source (25), the output end of the exposing unit (9) is connected with the input end of the active shield (6), the output end of the active shield (6) is connected with the input end of the masking unit (10), the output end of the masking unit (10) is provided with an A public key (13), the masking controller (8) can mask the input value provided to the active shield (6) by using a true random bit (22) and expose the output value of the active shield (6), the output value can be regarded as a qualitative mapping of the input value as long as the wire in the active shield (6) is not damaged and is marked as the protection source (25), the protection source (25) can be stored in the encryption memory (16), namely, as long as the wire in the active shield (6) is intact, the input value transmitted by the wire can generate a predicted output value, the size of the output value may match the size of the required decryption key.

6. An integrated circuit according to claim 1, wherein: the active mask (6) comprises three slices (19), the three slices (19) comprise a combinational logic and memory A (20) and a combinational logic and non-A memory (21), the upper and lower mask lines of the IC component (7) are positioned between the combinational logic and memory A (20) and the combinational logic and non-A memory (21) transmission bits, the three slices (19) are respectively marked as a slice A (1901), a slice B (1902) and a slice C (1903), the output end of the mask controller (8) is connected with the input end of the slice A (1901), the output end of the slice A (1901) is connected with the input end of the slice B (1902), the output end of the slice B (1902) is connected with the input end of the slice C (1903), the output end of the slice C (1903) is connected with the input end of the mask controller (8), the output end of the mask controller (8) is provided with a linear slice function (26) and a true random bit (22) The combinational logic and memory A (20) is used for providing serial data and control signals, the combinational logic and non-A memory (21) is used for providing serial data and optional control signals, when the mask controller (8) operates, the combinational logic performs conversion on the serial data under the control of the control signals, thereby implementing a linear function, the intermediate data can be stored in the memories of the combinational logic and memory A (20) and the combinational logic and non-A memory (21), and the data can be shifted through the slice (19), namely, the process is the process performed by the shift register.

7. An integrated circuit according to claim 6, wherein: the output end of the true random bit (22) is connected with a buffer (23), the output end of the buffer (23) is connected with a pseudo random number generator A (2401), the output end of the pseudo random number generator A (2401) is connected with the input end of a linear slice function (26), the output end of the pseudo random number generator A (2401) is connected with an exclusive-or gate A (1501), the output end of the linear slice function (26) is connected with an exclusive-or gate B (1502), the input end of the exclusive-or gate B (1502) is connected with the output end of an active shield (6), the output end of the protection source (25) is connected with a pseudo random number generator B (2402), the output end of the pseudo random number generator B (2402) is provided with an N-bit encryption function (28), the input end of the N-bit encryption function (28) is connected with an N-bit counter (27), and the output end of the N-bit encryption function (28) is connected with the input end of the exclusive-or gate A (1501), the output end of the exclusive-OR gate A (1501) is connected with the input end of the active shield (6), the output end of the exclusive-OR gate B (1502) is provided with a hash function (29), the output end of the hash function (29) is connected with the input end of the A public key (13), and the hash function (29) is convenient for effectively testing whether the active shield (6) is damaged or not, namely determining whether the integrated circuit is tampered or not.

8. An integrated circuit according to any of claims 1-7, wherein: the method for protecting the integrated circuit further comprises the following specific steps:

the method comprises the following steps: assuming that N is the number of serial bits of a slice (19) and M is the number of the slices (19), a single pass may be defined as M steps of the pseudo-random number generator A (2401) and the pseudo-random number generator B (2402);

step two: reloading the values of the pseudo-random number generator a (2401) and the pseudo-random number generator B (2402) on each pass, i.e. at each step both pseudo-random number generator a (2401) and pseudo-random number generator B (2402) generate a new random value for the slice (19);

step three: during testing, the N-bit counter (27) is reset to an initial value, and then the N-bit counter (27) generates a new value during each pass;

step four: the active mask (6) has a serial data input, a serial data output and can be seen as a shift register with M stages, i.e. each stage in the active mask (6) comprises one slice (19), which slice (19) is configured to shift N transition bits towards the next slice (19);

step five: the buffer (23), the pseudo random number generator B (2402) and the linear slicing function (26) do not operate on any data related to the protection source (25), but only on the data of the true random bits (22), so the buffer (23), the pseudo random number generator B (2402) and the linear slicing function (26) are used to mask the input value to the active mask (6) and reveal the output value of the active mask (6), the N-bit encryption function (28) is used to diversify the N-bit counter (27) value depending on the protection source (25) data;

step six: the output of the N-bit encryption function (28) is used to determine the input to the active mask (6) which is masked at xor gate a (1501) by the output of pseudo-random number generator B (2402), then xor gate a (1501) outputs a random input for the active mask (6), and similarly, the output of the active mask (6) is random and revealed at xor gate B (1502), i.e. the output of xor gate B (1502) is used as a deterministic input to the hash function (29), effectively testing whether the active mask (6) has been corrupted, i.e. determining whether the integrated circuit has been tampered with.

Background

An integrated circuit is a microelectronic device or component. It adopts a certain process to make the required elements of transistor, resistor, capacitor and inductor, etc. and wiring interconnection in a circuit be made on a small piece or several small pieces of semiconductor chip or medium substrate, then packaged in a tube shell, in which all the elements are formed into a whole body.

With the rapid development of the electronic industry, more and more integrated circuits are applied to various communication and electronic devices, a large amount of private information and secret data are often stored in the integrated circuits, in order to protect the sensitive data and prevent unauthorized reading and storing behaviors, a protective shielding layer is mostly placed in the upper area of a circuit interconnection part in the prior art, when a reading probe is inserted by others privately, a metal trace is damaged, signals do not flow in the shielding layer any more, therefore, the circuit can detect intrusion and generate an alarm signal, and the way has low protection performance and poor applicability to the intrusion behaviors without inserting the reading probe; a few protection technologies carry out verification encryption on the integrated circuit for many times, but when an encryption program is written, the operation is very complex, the time is consumed, the technical content is high, and the popularization and the use are difficult.

Disclosure of Invention

To this end, the present invention provides an integrated circuit and a method for protecting the integrated circuit, through the arrangement of a data processor, an IC component is configured to use an access key to read the content in an encrypted memory, the access key can access the content of a memory cell through a password or other codes, encrypt and decrypt the content in the encrypted memory, can strongly prevent unauthorized reading and storing actions, and has strong security, through the arrangement of an active mask and an xor gate, when the active mask is damaged, the a public key output by a mask controller is an error result, the xor gate is also incorrect, although an attacker can detect the internal signal of the integrated circuit, but can not correctly decrypt the content in the encrypted memory, can not acquire sensitive data, and the integrated circuit has strong practicability, double protection, high security and simple operation, the method is suitable for the encryption storage requirements of various integrated circuits, is convenient to popularize and solves the problems of poor information intrusion behavior protection and poor protectiveness in the prior art.

In order to achieve the above purpose, the invention provides the following technical scheme: an integrated circuit comprises a top layer, wherein the lower wall of the top layer is fixedly connected with four insulating layers, the lower wall of the bottom insulating layer is fixedly connected with a substrate, a base library is installed in the top layer, the three layers of the upper insulating layer are fixedly connected with metal core wires, an active shield is installed in the bottom insulating layer, and an IC assembly is installed in the substrate;

the top layer, the insulating layer and the substrate are used for providing a safe installation space for each functional component of the integrated circuit;

the base class library supports various operation common programming operations and is used for providing a common programming framework for IC components and a plurality of actively shielded algorithm devices;

the metal core wire is used for electrically connecting all functional parts of the integrated circuit, so that the information transmission is facilitated;

the active mask is used to inject a random bit sequence in the top of the IC and to check that the random bit sequence arrives after passing through the various features of the integrated circuit, verifying the dense wires of circuit integrity;

the IC component is used for encrypting and storing sensitive data and implementing security protection.

Further, the IC assembly includes a shield controller including an exposing unit and a masking unit.

Further, the output end of the active shield is connected with the input end of the shield controller, and the output end of the shield controller is connected with the input end of the active shield.

Further, the input end of the shielding controller is connected with a true random number generator, the output end of the shielding controller is provided with a public key A, the output end of the public key A is connected with an exclusive-OR gate, the input end of the shielding controller is connected with a key storage device, the output end of the key storage device is provided with a public key B, the output end of the public key B is connected with the input end of the exclusive-OR gate, the output end of the exclusive-OR gate is connected with a data processor, the output end of the data processor is connected with a central processing unit, the output end of the central processing unit is connected with the input end of the data processor, the output end of the data processor is connected with an encryption memory, the output end of the encryption memory is connected with the input end of the data processor, the exclusive-OR gate is used for executing exclusive-OR operation, the true random number generator is used for providing true random bits to the shielding controller, the data processor is used for encrypting the content of the encryption memory by using the encryption key and decrypting the content of the encryption memory by using the corresponding decryption key, the encryption memory is used for storing the public key A and the public key B, and the central processor can carry out operation control on the data processor.

Further, the input end of the exposing unit is connected with a protection source, the output end of the exposing unit is connected with the input end of the active shield, the output end of the active shield is connected with the input end of the masking unit, the output end of the masking unit is provided with a public key A, the masking controller can use true random bits to mask the input value provided to the active shield and expose the output value of the active shield, the output value can be regarded as a qualitative mapping of the input value as long as the wires in the active shield are not damaged and is marked as a protection source, the protection source can be stored in the encryption memory, namely, as long as the wires in the active shield are intact, the input value transmitted by the wires can generate a predicted output value, and the size of the output value can be matched with the size of a required decryption key.

Further, the active mask includes three slices, three of the slices include combinational logic and memory a and combinational logic and non-a memory, the upper and lower mask lines of the IC assembly are located between the combinational logic and memory a and combinational logic and non-a memory transmission bits, the three slices are respectively referred to as slice a, slice B and slice C, the output end of the mask controller is connected with the input end of slice a, the output end of slice a is connected with the input end of slice B, the output end of slice B is connected with the input end of slice C, the output end of slice C is connected with the input end of the mask controller, the output end of the mask controller is provided with a linear slice function and a true random bit, the combinational logic and memory a is used for providing serial data and control signals, the combinational logic and non-a memory is used for providing serial data and optionally control signals, when the mask controller operates, the combinational logic performs conversion on the serial data under the control of the control signal, thereby implementing a linear function, the intermediate data may be stored in the memories of the combinational logic and memory a and the combinational logic and non-a memory, and the data may be shifted by slicing, i.e., this process is a process performed by a shift register.

Furthermore, the output end of the true random bit is connected with a buffer, the output end of the buffer is connected with a pseudo random number generator A, the output end of the pseudo random number generator A is connected with the input end of a linear slice function, the output end of the pseudo random number generator A is connected with an XOR gate A, the output end of the linear slice function is connected with an XOR gate B, the input end of the XOR gate B is connected with the output end of an active shield, the output end of the protection source is connected with a pseudo random number generator B, the output end of the pseudo random number generator B is provided with an N-bit encryption function, the input end of the N-bit encryption function is connected with an N-bit counter, the output end of the N-bit encryption function is connected with the input end of the XOR gate A, the output end of the XOR gate A is connected with the input end of the active shield, and the output end of the XOR gate B is provided with a hash function, the output end of the hash function is connected with the input end of the A public key, and the hash function is convenient for effectively testing whether the active shielding is damaged or not, namely determining whether the integrated circuit is tampered or not.

The invention also includes a method for protecting an integrated circuit, comprising the steps of:

the method comprises the following steps: assuming that N is the number of serial bits of a slice and M is the number of slices, then a single pass may be defined as M steps of pseudo-random number generator A and pseudo-random number generator B;

step two: reloading the numerical values of the pseudo-random number generator A and the pseudo-random number generator B during each pass, namely, generating a new random value for the slice by the pseudo-random number generator A and the pseudo-random number generator B in each step;

step three: during testing, resetting the N-bit counter to an initial value, and generating a new value by the N-bit counter when the N-bit counter passes each time;

step four: the active mask has a serial data input, a serial data output, and can be viewed as a shift register with M stages, i.e., each stage in the active mask includes a slice configured to shift the next slice by N transition bits;

step five: the buffer, pseudo-random number generator B and linear slice function do not operate on any data related to the protection source, but only on data of true random bits, so the buffer, pseudo-random number generator B and linear slice function are used to mask the input values to the active mask and reveal the output values of the active mask, the N-bit encryption function is used to diversify the N-bit counter values depending on the protection source data;

step six: the output of the N-bit encryption function is used to determine the input of the active mask which is masked at xor gate a by the output of the pseudo-random number generator B, then xor gate a outputs the random input for the active mask, and similarly the output of the active mask is random and revealed at xor gate B, i.e. the output of xor gate B is used as a deterministic input to the hash function, which effectively tests whether the active mask has been corrupted, i.e. determines whether the integrated circuit has been tampered with.

The invention has the following advantages:

1. through the arrangement of the data processor, compared with the prior art, the IC component is configured to read the content in the encrypted memory by using the access key, the access key can access the content in the memory unit through a password or other codes, the content in the encrypted memory is encrypted and decrypted, the unauthorized reading and storing behaviors can be powerfully prevented, and the safety is strong;

2. compared with the prior art, the invention has the advantages that the active shielding and the exclusive-OR gate are arranged, when the active shielding is damaged, the A public key output by the shielding controller is an error result, the exclusive-OR gate is incorrect, although an attacker can detect the internal signal of the integrated circuit, the attacker cannot correctly decrypt the content in the encryption memory, and cannot acquire sensitive data, so that the practicability is strong, the dual protection is realized, the safety is high, the operation is simple, the method is suitable for the encryption memory requirements of various integrated circuits, and the popularization is convenient.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It should be apparent that the drawings in the following description are merely exemplary, and that other embodiments can be derived from the drawings provided by those of ordinary skill in the art without inventive effort.

The structures, ratios, sizes, and the like shown in the present specification are only used for matching with the contents disclosed in the specification, so as to be understood and read by those skilled in the art, and are not used to limit the conditions that the present invention can be implemented, so that the present invention has no technical significance, and any structural modifications, changes in the ratio relationship, or adjustments of the sizes, without affecting the effects and the achievable by the present invention, should still fall within the range that the technical contents disclosed in the present invention can cover.

FIG. 1 is a schematic diagram of an integrated circuit structure according to the present invention;

FIG. 2 is a block diagram of an IC package according to the present invention;

FIG. 3 is a block diagram of a shield controller according to the present invention;

FIG. 4 is a block diagram of an active shield control architecture of the present invention;

FIG. 5 is a block diagram of an integrated circuit implementation of the present invention;

FIG. 6 is a block diagram of the public key output structure of the invention A;

FIG. 7 is a block diagram of a slicing structure according to the present invention;

FIG. 8 is a block diagram of the intra-slice connection configuration of the present invention;

FIG. 9 is a block diagram of the shield controller and slice connection configuration of the present invention;

FIG. 10 is a block diagram of an active masking implementation data structure of the present invention.

In the figure: 1. a top layer; 2. an insulating layer; 3. a substrate; 4. a base class library; 5. a metal core wire; 6. active shielding; 7. an IC component; 8. a shield controller; 9. exposing a unit; 10. a masking unit; 11. a true random number generator; 12. a key storage device; 13. a public key; 14. b, a public key; 15. an exclusive-or gate; 1501. an exclusive-OR gate A; 1502. an exclusive-or gate B; 16. an encryption memory; 17. a data processor; 18. a central processing unit; 19. slicing; 1901. slicing A; 1902. slicing B; 1903. slicing C; 20. combinational logic and memory a; 21. combinational logic and non-A memory; 22. true random bits; 23. a buffer; 2401. a pseudo-random number generator A; 2402. a pseudo-random number generator B; 25. a protection source; 26. a linear slice function; 27. an N-bit counter; 28. an N-bit encryption function; 29. a hash function.

Detailed Description

The present invention is described in terms of particular embodiments, other advantages and features of the invention will become apparent to those skilled in the art from the following disclosure, and it is to be understood that the described embodiments are merely exemplary of the invention and that it is not intended to limit the invention to the particular embodiments disclosed. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to the attached drawings 1-10 of the specification, the integrated circuit of the embodiment comprises a top layer 1, wherein four insulating layers 2 are fixedly connected to the lower wall of the top layer 1, a substrate 3 is fixedly connected to the lower wall of the insulating layer 2 at the bottom, a base library 4 is installed in the top layer 1, a metal core wire 5 is fixedly connected in the insulating layer 2 at the upper three layers, an active shield 6 is installed in the insulating layer 2 at the bottom, and an IC assembly 7 is installed in the substrate 3;

the top layer 1, the insulating layer 2 and the substrate 3 are used for providing a safe installation space for each functional component of the integrated circuit;

the base class library 4 supports various operation common programming operations for providing a common programming framework for a plurality of algorithm devices of the IC component 7 and the active shield 6;

the metal core wire 5 is used for electrically connecting all functional parts of the integrated circuit, so that information transmission is facilitated;

the active mask 6 is used to inject a random bit sequence in the top of the IC and to check that the random bit sequence arrives after passing through the various functional components of the integrated circuit, verifying the dense wires of circuit integrity;

the IC component 7 is used to encrypt and store sensitive data and to implement security protection.

Further, the IC assembly 7 comprises a shielding controller 8, and the shielding controller 8 comprises an exposing unit 9 and a masking unit 10.

Further, the output end of the active shield 6 is connected with the input end of the shield controller 8, and the output end of the shield controller 8 is connected with the input end of the active shield 6.

Further, the input end of the shielding controller 8 is connected with a true random number generator 11, the output end of the shielding controller 8 is provided with a public key a 13, the output end of the public key a 13 is connected with an exclusive or gate 15, the input end of the shielding controller 8 is connected with a key storage device 12, the output end of the key storage device 12 is provided with a public key B14, the output end of the public key B14 is connected with the input end of the exclusive or gate 15, the output end of the exclusive or gate 15 is connected with a data processor 17, the output end of the data processor 17 is connected with a central processor 18, the output end of the central processor 18 is connected with the input end of the data processor 17, the output end of the data processor 17 is connected with an encryption memory 16, the output end of the encryption memory 16 is connected with the input end of the data processor 17, the exclusive or gate 15 is used for executing exclusive or operation, the true random number generator 11 is configured to provide the true random bits 22 to the masking controller 8, the data processor 17 is configured to encrypt contents of the encryption memory 16 using an encryption key and decrypt contents of the encryption memory 16 using a corresponding decryption key, the encryption memory 16 is configured to store an a public key 13 and a B public key 14, and the central processor 18 is configured to operatively control the data processor 17.

Further, the input of the disclosure unit 9 is connected to a protection source 25, the output of the disclosure unit 9 is connected to the input of the active shield 6, the output of the active shield 6 is connected to the input of the masking unit 10, the output of the masking unit 10 is provided with a public key a 13, the masking controller 8 can mask the input value provided to the active shield 6 using the true random bits 22 and reveal the output value of the active shield 6, the output value can be regarded as a qualitative mapping of the input value as the protection source 25 as long as the wires in the active shield 6 are not damaged, the protection source 25 can be stored in the encryption memory 16, that is, the input value transmitted through the wires in the active shield 6 can generate a predicted output value, and the size of the output value can match the size of the required decryption key.

Further, the active mask 6 includes three slices 19, three of the slices 19 each include combinational logic and memory a20 and combinational logic and non-a memory 21, the upper and lower mask lines of the IC package 7 are located between the combinational logic and memory a20 and the combinational logic and non-a memory 21 transmission bits, three of the slices 19 are respectively referred to as slice a1901, slice B1902 and slice C1903, the output terminal of the mask controller 8 is connected to the input terminal of slice a1901, the output terminal of slice a1901 is connected to the input terminal of slice B1902, the output terminal of slice B1902 is connected to the input terminal of slice C1903, the output terminal of slice C1903 is connected to the input terminal of the mask controller 8, the output terminal of the mask controller 8 is provided with a linear slice function 26 and a true random bit 22, the combinational logic and memory a20 is used for providing serial data and control signals, the combinational logic and non-a memory 21 is used to provide serial data and optionally control signals, the combinational logic performs conversion on the serial data under the control of the control signals when the mask controller 8 operates, thereby implementing a linear function, intermediate data can be stored in the memories of the combinational logic and memory a20 and the combinational logic and non-a memory 21, and the data can be shifted through the slice 19, i.e., this process is a process performed by a shift register.

Further, the output end of the true random bit 22 is connected to a buffer 23, the output end of the buffer 23 is connected to a pseudo random number generator a2401, the output end of the pseudo random number generator a2401 is connected to the input end of a linear slice function 26, the output end of the pseudo random number generator a2401 is connected to an xor gate a1501, the output end of the linear slice function 26 is connected to an xor gate B1502, the input end of the xor gate B1502 is connected to the output end of an active mask 6, the output end of the protection source 25 is connected to a pseudo random number generator B2402, the output end of the pseudo random number generator B2402 is provided with an N-bit encryption function 28, the input end of the N-bit encryption function 28 is connected to an N-bit counter 27, the output end of the N-bit encryption function 28 is connected to the input end of the xor gate a1501, the output end of the xor gate a1501 is connected to the input end of the active mask 6, the output of the xor gate B1502 is provided with a hash function 29, the output of the hash function 29 is connected to the input of the public a key 13, and the hash function 29 facilitates effectively testing whether the active shield 6 has been damaged, i.e. determining whether the integrated circuit has been tampered with.

The invention also includes a method for protecting an integrated circuit, comprising the steps of:

the method comprises the following steps: assuming that N is the number of serial bits of a slice 19 and M is the number of such slices 19, a single pass may be defined as M steps of the pseudo-random number generator A2401 and pseudo-random number generator B2402;

step two: the values of the pseudo-random number generator a2401 and the pseudo-random number generator B2402 are reloaded each time they pass, i.e. at each step both the pseudo-random number generator a2401 and the pseudo-random number generator B2402 generate new random values for the slice 19;

step three: during testing, the N-bit counter 27 is reset to an initial value, and then the N-bit counter 27 generates a new value when the test passes each time;

step four: the active mask 6 has a serial data input, a serial data output, and can be viewed as a shift register with M stages, i.e., each stage in the active mask 6 includes one slice 19, the slice 19 being configured to shift N transition bits to the next slice 19;

step five: the buffer 23, the pseudo-random number generator B2402 and the linear slice function 26 do not operate on any data related to the protection source 25, but only on the data of the true random bits 22, so the buffer 23, the pseudo-random number generator B2402 and the linear slice function 26 serve to mask the input value to the active mask 6 and reveal the output value of the active mask 6, the N-bit encryption function 28 serves to diversify the N-bit counter 27 value depending on the protection source 25 data, the IC component 7 is configured to enable reading of the contents in the encrypted memory 16 using an access key that can, by means of a password or other code, enable access to the contents of the memory cell, encrypt and decrypt the contents in the encrypted memory 16, enable strong protection against unauthorized reading of the memory behavior, strong security;

step six: the output of the N-bit encryption function 28 is used to determine the input of the active mask 6, which is masked by the output of the pseudo-random number generator B2402 at the xor gate a1501, the xor gate a1501 outputs a random input for the active mask 6, and similarly, the output of the active mask 6 is random and is revealed at the xor gate B1502, that is, the output of the xor gate B1502 is used as a deterministic input for the hash function 29, which can effectively test whether the active mask 6 has been damaged, that is, determine whether the integrated circuit has been tampered with, when the active mask 6 is damaged, the a public key 13 output by the mask controller 8 is a false result, the xor gate 15 is also incorrect, and although an attacker can detect the internal signal of the integrated circuit, but cannot correctly decrypt the contents in the encryption memory 16, cannot acquire sensitive data, and therefore, the practicability is strong, double protection, high security, and operation is simple, the method is suitable for the encryption storage requirements of various integrated circuits and is convenient to popularize.

Although the invention has been described in detail above with reference to a general description and specific examples, it will be apparent to one skilled in the art that modifications or improvements may be made thereto based on the invention. Accordingly, such modifications and improvements are intended to be within the scope of the invention as claimed.