1. A self-adaptive resource allocation layout and wiring method of a storage and computation integrated framework is characterized in that:

the method comprises the following steps in sequence:

reading a blif netlist file containing logic gate information, and setting an initial value of a storage and calculation integrated framework consisting of a plurality of storage and calculation interchange processing units;

step two, solving an objective function by adopting a simulated annealing algorithm, executing layout and wiring of the storage and calculation integrated framework by combining an A-algorithm, and finally obtaining the optimal layout and wiring mode and the resource utilization rate of each storage and calculation interchange processing unit, wherein the objective function is a Cost_iMinimum:

Cost_i＝(C-A(i))×P(i)+C×R(i)

in the above formula, C is the length of the critical path, a (i) is the longest path length containing the logic primitive i, p (i) is the placement cost of the logic primitive i, r (i) is the routing cost of the logic primitive i, C_lFor storing the amount of logical resources used in the interchange processing unit, C_iFor storing the number of interconnection resources used in the interchange of processing units, N_pIs a very large positive number, U_tCalculating the resource utilization rate of the interchange processing unit for the storage of the logic primitive i;

and step three, judging whether the resource utilization rate of each storage and calculation interchange processing unit meets the requirement, if not, adjusting the number of the storage and calculation interchange processing units in the storage and calculation integrated framework and then returning to the step two, and if so, outputting the total number of the storage and calculation interchange processing units in the storage and calculation integrated framework, the number of the storage and calculation interchange processing units on the key path and the layout and wiring mode of each storage and calculation interchange processing unit.

2. The method of claim 1, wherein the method comprises:

the second step comprises the following steps in sequence:

2.1, generating an initial layout of the storage-computation integrated architecture by adopting a simulated annealing algorithm, and generating routing paths of all networks by an A-x algorithm to obtain an initial cost;

2.2, solving an objective function in the annealing process, and realizing the layout and the wiring of each memory exchange processing unit by adopting an A-algorithm;

2.3, updating the cost and the temperature according to an annealing strategy;

and 2.4, finishing annealing to obtain the optimal layout and wiring mode and the resource utilization rate of each memory interchange processing unit.

3. The method of claim 1 or 2, wherein the method comprises:

in the second step, the resource utilization rate R of each memory interchange processing unit is calculated by using the following formula:

in the above equation, N is the total amount of hardware resources in the memory swap processing unit.

4. The method of claim 1 or 2, wherein the method comprises:

the third step comprises the following steps in sequence:

3.1, judging whether a storage and calculation interchange processing unit with the resource utilization rate more than 100% exists in each storage and calculation interchange processing unit, if so, increasing the number of the storage and calculation interchange processing units in the storage and calculation integrated framework and then returning to the step two, and if not, entering the step 3.2;

and 3.2, judging whether the storage and calculation interchange processing units with the resource utilization rate smaller than a set threshold exist in each storage and calculation interchange processing unit, if so, reducing the number of the storage and calculation interchange processing units in the storage and calculation integrated framework and then returning to the step two, and if not, outputting the total number of the storage and calculation interchange processing units in the storage and calculation integrated framework, the number of the storage and calculation interchange processing units on the key path and the layout and wiring mode of each storage and calculation interchange processing unit.

5. The method of claim 1 or 2, wherein the method comprises:

in the first step, the initial value setting method of the storage and computation integrated framework comprises the following steps: the hardware resource allocation of each memory interchange processing unit in the memory and computation integrated architecture is firstly set, and then the number of the memory and computation interchange processing units is given.

6. The method of claim 1 or 2, wherein the method comprises:

in the first step, the blif netlist file containing the logic gate information is generated by the following method:

the method comprises the steps of firstly taking a circuit written by a Verilog language as input, reading a file by adopting an ODIN II tool and analyzing the file to generate a netlist file in a blif format, then reading the generated netlist file by using an ABC logic synthesis and optimization tool, compiling and optimizing the netlist file to generate a blif netlist file containing logic gate information.

7. An adaptive resource allocation placement and routing system for a storage-computing integrated architecture, comprising:

the system comprises a place and route module (1), the place and route module (1) is used for executing the method of claim 1.

8. The adaptive resource allocation placement and routing system of a computing-integrated architecture of claim 7, wherein:

the system also comprises a front-end analysis module (2) and a logic synthesis module (3), wherein the signal output end of the front-end analysis module (2) is connected with the signal input end of the layout and wiring module (1) through the logic synthesis module (3);

the front-end analysis module (2) is used for reading and analyzing a circuit written in Verilog language through an ODIN II tool to generate a netlist file in a blif format;

and the logic synthesis module (3) is used for reading the generated netlist file in the blif format by using an ABC logic synthesis and optimization tool, and generating the blif netlist file containing logic gate information after compiling and optimizing.

Background

With the rapid development of applications such as scientific computing, internet of things, big data, artificial intelligence and the like, the application types are differentiated, and the computing access characteristics are different from those of the data-intensive applications, even in the same application, the computing access characteristics at different stages are also greatly different. Due to the hardening of hardware implementation, a unified computing architecture is conventionally adopted for different applications, and when the unified computing architecture is applied to different types of applications or different stages of the same application, the efficiency may drop rapidly.

With the development of memristor devices, a computationally integrated architecture of non-von structures was proposed to address the above-mentioned problems. The storage and calculation integrated architecture realizes that the same circuit unit has one of three roles of calculation, storage and interconnection at different moments through online configuration. By designing an algorithm, the proportion of storage and calculation resources in the framework can be adjusted on line, and efficient processing of data-intensive and calculation-intensive tasks is realized. However, the physical structure of the integrated computing architecture is significantly different from that of the conventional computing architecture, so that the existing layout and routing algorithm developed for the conventional computing architecture cannot be applied to the layout and routing task of the integrated computing architecture, which limits the development of the application program for the integrated computing architecture.

Disclosure of Invention

The present invention is directed to overcome the above problems in the prior art, and provides a method and system for adaptive resource allocation, placement and routing applicable to a storage-computation-integrated architecture.

In order to achieve the above purpose, the invention provides the following technical scheme:

a self-adaptive resource allocation layout and wiring method of a storage and computation integrated framework sequentially comprises the following steps:

reading a blif netlist file containing logic gate information, and setting an initial value of a storage and calculation integrated framework consisting of a plurality of storage and calculation interchange processing units;

step two, solving an objective function by adopting a simulated annealing algorithm, executing layout and wiring of the storage and calculation integrated framework by combining an A-algorithm, and finally obtaining the optimal layout and wiring mode and the resource utilization rate of each storage and calculation interchange processing unit, wherein the objective function is a Cost_iMinimum:

Cost_i＝(C-AG))XP(i)+CXR(i)

in the above formula, C is the length of the critical path, a (i) is the longest path length containing the logic primitive i, p (i) is the placement cost of the logic primitive i, r (i) is the routing cost of the logic primitive i, C_lFor storing the amount of logical resources used in the interchange processing unit, C_iFor storing the number of interconnection resources used in the interchange of processing units, N_pIs a very large positive number, U_tCalculating the resource utilization rate of the interchange processing unit for the storage of the logic primitive i;

and step three, judging whether the resource utilization rate of each storage and calculation interchange processing unit meets the requirement, if not, adjusting the number of the storage and calculation interchange processing units in the storage and calculation integrated framework and then returning to the step two, and if so, outputting the total number of the storage and calculation interchange processing units in the storage and calculation integrated framework, the number of the storage and calculation interchange processing units on the key path and the layout and wiring mode of each storage and calculation interchange processing unit.

The second step comprises the following steps in sequence:

2.1, generating an initial layout of the storage-computation integrated architecture by adopting a simulated annealing algorithm, and generating routing paths of all networks by an A-x algorithm to obtain an initial cost;

2.2, solving an objective function in the annealing process, and realizing the layout and the wiring of each memory exchange processing unit by adopting an A-algorithm;

2.3, updating the cost and the temperature according to an annealing strategy;

and 2.4, finishing annealing to obtain the optimal layout and wiring mode and the resource utilization rate of each memory interchange processing unit.

In the second step, the resource utilization rate R of each memory interchange processing unit is calculated by using the following formula:

in the above equation, N is the total amount of hardware resources in the memory swap processing unit.

The third step comprises the following steps in sequence:

3.1, judging whether a storage and calculation interchange processing unit with the resource utilization rate more than 100% exists in each storage and calculation interchange processing unit, if so, increasing the number of the storage and calculation interchange processing units in the storage and calculation integrated framework and then returning to the step two, and if not, entering the step 3.2;

and 3.2, judging whether the storage and calculation interchange processing units with the resource utilization rate smaller than a set threshold exist in each storage and calculation interchange processing unit, if so, reducing the number of the storage and calculation interchange processing units in the storage and calculation integrated framework and then returning to the step two, and if not, outputting the total number of the storage and calculation interchange processing units in the storage and calculation integrated framework, the number of the storage and calculation interchange processing units on the key path and the layout and wiring mode of each storage and calculation interchange processing unit.

In the first step, the initial value setting method of the storage and computation integrated framework comprises the following steps: the hardware resource allocation of each memory interchange processing unit in the memory and computation integrated architecture is firstly set, and then the number of the memory and computation interchange processing units is given.

In the first step, the blif netlist file containing the logic gate information is generated by the following method:

the method comprises the steps of firstly taking a circuit written by a Verilog language as input, reading a file by adopting an ODIN II tool and analyzing the file to generate a netlist file in a blif format, then reading the generated netlist file by using an ABC logic synthesis and optimization tool, compiling and optimizing the netlist file to generate a blif netlist file containing logic gate information.

An adaptive resource allocation placement and routing system of a storage-integrated architecture comprises a placement and routing module, and the placement and routing module is used for executing the method.

The system also comprises a front-end analysis module and a logic synthesis module, wherein the signal output end of the front-end analysis module is connected with the signal input end of the layout and wiring module through the logic synthesis module;

the front-end analysis module is used for reading and analyzing a circuit written in Verilog language through an ODIN II tool to generate a netlist file in a blif format;

the logic synthesis module is used for reading the generated netlist file in the blif format by using an ABC logic synthesis and optimization tool, compiling and optimizing the netlist file to generate a blif netlist file containing logic gate information.

Compared with the prior art, the invention has the beneficial effects that:

1. the invention relates to a self-adaptive resource allocation layout and wiring method of a storage and calculation integrated framework, which comprises the steps of firstly reading a blif netlist file containing logic gate information, setting an initial value of the storage and calculation integrated framework consisting of a plurality of storage and exchange processing units, then solving an objective function by adopting a simulated annealing algorithm, executing layout and wiring of the storage and calculation integrated framework by combining an A algorithm to obtain the optimal layout and wiring mode and the resource utilization rate of each storage and exchange processing unit, finally judging whether the resource utilization rate of each storage and exchange processing unit meets the requirement or not, and if so, outputting the total number of the storage and exchange processing units in the storage and calculation integrated framework, the number of the storage and exchange processing units on a key path and the layout and wiring mode of each storage and exchange processing unit, wherein the method simultaneously adopts the A algorithm to execute a layout and wiring task in the simulated annealing algorithm and can finely divide hardware resources of each storage and exchange processing unit according to the actual usage method, therefore, the self-adaptive partition of the hardware resources in the storage and computation integrated architecture is realized, and the utilization rate of the hardware resources in the storage and computation interchange architecture is improved. Therefore, the invention realizes the self-adaptive partition of hardware resources in the storage and computation integrated architecture and improves the utilization rate.

2. The self-adaptive resource allocation layout and wiring method of the storage and computation integrated framework directly takes the blif netlist file subjected to logic synthesis and optimization as input, and compared with the traditional layout and wiring method for frameworks such as FPGA (field programmable gate array), the method omits a packaging step, so that the logic use condition in the storage and computation interchange processing unit can be adjusted according to the granularity of logic primitives rather than complex logic clusters, and finer-grained control on resource partitioning is realized. Therefore, the invention realizes finer-grained control of the resource partition.

Drawings

FIG. 1 is a circuit diagram of a memory integrated architecture.

FIG. 2 is a diagram illustrating adaptive resource partitioning according to the present invention.

Fig. 3 is a block diagram of the system of the present invention.

Detailed Description

The present invention will be further described with reference to the following detailed description and accompanying drawings.

Referring to fig. 1 and fig. 2, a method for allocating, laying out and routing adaptive resources of a storage-integration framework sequentially includes the following steps:

reading a blif netlist file containing logic gate information, and setting an initial value of a storage and calculation integrated framework consisting of a plurality of storage and calculation interchange processing units;

step two, solving an objective function by adopting a simulated annealing algorithm, executing layout and wiring of the storage and calculation integrated framework by combining an A-algorithm, and finally obtaining the optimal layout and wiring mode and the resource utilization rate of each storage and calculation interchange processing unit, wherein the objective function is a Cost_iMinimum:

Cost_i＝(C-A(i))XP(i)+CxR(i)

in the above formula, C is the length of the critical path, a (i) is the longest path length containing the logic primitive i, p (i) is the placement cost of the logic primitive i, r (i) is the routing cost of the logic primitive i, C_lFor storing the amount of logical resources used in the interchange processing unit, C_iFor storing the number of interconnection resources used in the interchange of processing units, N_pIs a very large positive number, U_tCalculating the resource utilization rate of the interchange processing unit for the storage of the logic primitive i;

and step three, judging whether the resource utilization rate of each storage and calculation interchange processing unit meets the requirement, if not, adjusting the number of the storage and calculation interchange processing units in the storage and calculation integrated framework and then returning to the step two, and if so, outputting the total number of the storage and calculation interchange processing units in the storage and calculation integrated framework, the number of the storage and calculation interchange processing units on the key path and the layout and wiring mode of each storage and calculation interchange processing unit.

The second step comprises the following steps in sequence:

2.1, generating an initial layout of the storage-computation integrated architecture by adopting a simulated annealing algorithm, and generating routing paths of all networks by an A-x algorithm to obtain an initial cost;

2.2, solving an objective function in the annealing process, and realizing the layout and the wiring of each memory exchange processing unit by adopting an A-algorithm;

2.3, updating the cost and the temperature according to an annealing strategy;

and 2.4, finishing annealing to obtain the optimal layout and wiring mode and the resource utilization rate of each memory interchange processing unit.

In the second step, the resource utilization rate R of each memory interchange processing unit is calculated by using the following formula:

in the above equation, N is the total amount of hardware resources in the memory swap processing unit.

The third step comprises the following steps in sequence:

3.1, judging whether a storage and calculation interchange processing unit with the resource utilization rate more than 100% exists in each storage and calculation interchange processing unit, if so, increasing the number of the storage and calculation interchange processing units in the storage and calculation integrated framework and then returning to the step two, and if not, entering the step 3.2;

and 3.2, judging whether the storage and calculation interchange processing units with the resource utilization rate smaller than a set threshold exist in each storage and calculation interchange processing unit, if so, reducing the number of the storage and calculation interchange processing units in the storage and calculation integrated framework and then returning to the step two, and if not, outputting the total number of the storage and calculation interchange processing units in the storage and calculation integrated framework, the number of the storage and calculation interchange processing units on the key path and the layout and wiring mode of each storage and calculation interchange processing unit.

In the first step, the initial value setting method of the storage and computation integrated framework comprises the following steps: the hardware resource allocation of each memory interchange processing unit in the memory and computation integrated architecture is firstly set, and then the number of the memory and computation interchange processing units is given.

In the first step, the blif netlist file containing the logic gate information is generated by the following method:

the method comprises the steps of firstly taking a circuit written by a Verilog language as input, reading a file by adopting an ODIN II tool and analyzing the file to generate a netlist file in a blif format, then reading the generated netlist file by using an ABC logic synthesis and optimization tool, compiling and optimizing the netlist file to generate a blif netlist file containing logic gate information.

Referring to fig. 3, an adaptive resource allocation placement and routing system of a storage-integrated architecture includes a placement and routing module 1, and the placement and routing module 1 is used for executing the method.

The system also comprises a front-end analysis module 2 and a logic synthesis module 3, wherein the signal output end of the front-end analysis module 2 is connected with the signal input end of the layout and wiring module 1 through the logic synthesis module 3;

the front-end analysis module 2 is used for reading and analyzing a circuit written in Verilog language through an ODIN II tool to generate a netlist file in a blif format;

the logic synthesis module 3 is configured to read the generated netlist file in the blif format by using an ABC logic synthesis and optimization tool, and generate a blif netlist file including logic gate information after compiling and optimizing the netlist file.

The principle of the invention is illustrated as follows:

the invention provides a self-adaptive resource allocation layout and wiring method capable of self-adaptively adjusting and storing fine-grained circuit component functions in an integrated framework according to the change of application requirements. The method can fully utilize hardware resources in the storage and computation integrated framework, fully exert the characteristics of the hardware structure, and reduce the consumption of the storage and computation integrated framework such as power consumption, area, time delay and the like during algorithm processing.

In the objective function, the target function is,

the present invention sets p (i) as a function of the utilization of the memory interchange processing unit that placed the logical primitive i. Specifically, when the resource utilization rate of the memory interchange processing unit where the logic primitive i is placed is less than 100%, p (i) is the reciprocal of the sum of the numbers of the logic and interconnection resources used in the current memory interchange processing unit; and when the resource utilization rate of the memory interchange processing unit for placing the logic primitive i exceeds 100%, P (i) is a very large positive number.

Example 1:

referring to fig. 1 and fig. 2, a method for allocating, laying out and routing adaptive resources of a storage and computation integrated architecture sequentially includes the following steps:

1. taking a circuit written by a Verilog language as input, reading and analyzing the file by adopting an ODIN II tool, and generating a netlist file in a blif format;

2. reading the generated netlist file by using an ABC logic synthesis and optimization tool, compiling and optimizing the netlist file to generate a blif netlist file containing logic gate information;

3. reading a blif netlist file containing logic gate information, and setting an initial value of a storage and calculation integrated framework consisting of a plurality of storage and calculation interchange processing units, wherein the initial value comprises the steps of firstly setting the hardware resource configuration of each storage and calculation interchange processing unit in the storage and calculation integrated framework, and then setting the number of the storage and calculation interchange processing units;

4. generating an initial layout of the storage-computation integrated architecture by adopting a simulated annealing algorithm, and generating routing paths of all networks by an A-algorithm to obtain an initial cost;

5. solving an objective function in the annealing process, and realizing the layout and the wiring of each memory-computation interchange processing unit by adopting an A-star algorithm, wherein the objective function is a Cost_iMinimum:

Cost_i＝(C-A(i))XP(i)+CXR(i)

in the above formula, C is the length of the critical path, A (i) is the inclusion logicLongest path length of primitive i, P (i) placement cost of logical primitive i, R (i) routing cost of logical primitive i, C_lFor storing the amount of logical resources used in the interchange processing unit, C_iFor storing the number of interconnection resources used in the interchange of processing units, N_pIs a very large positive number, U_tCalculating the resource utilization rate of the interchange processing unit for the storage of the logic primitive i;

6. updating the temperature according to the cost of the annealing strategy;

7. and after the annealing is finished, obtaining the optimal layout and wiring mode and the resource utilization rate of each storage and exchange processing unit, wherein the resource utilization rate R of each storage and exchange processing unit is obtained by adopting the following formula:

in the above formula, N is the total amount of hardware resources in the memory interchange processing unit;

8. judging whether a storage and calculation interchange processing unit with the resource utilization rate larger than 100% exists in each storage and calculation interchange processing unit, if so, increasing the number of the storage and calculation interchange processing units in the storage and calculation integrated framework and then returning to the step 3, and if not, entering the step 8;

9. and judging whether the storage interchange processing units with the resource utilization rate less than 50 percent exist in each storage interchange processing unit, if so, reducing the number of the storage interchange processing units in the storage and calculation integrated framework and returning to the step 3, and if not, outputting the total number of the storage interchange processing units in the storage and calculation integrated framework, the number of the storage interchange processing units on the key path and the layout and wiring mode of each storage interchange processing unit.

Example 2:

referring to fig. 3, a self-adaptive resource allocation layout and wiring system of a storage and computation integrated architecture includes a layout and wiring module 1, a front-end analysis module 2, and a logic synthesis module 3, where a signal output end of the front-end analysis module 2 is connected to a signal input end of the layout and wiring module 1 through the logic synthesis module 3;

the front-end analysis module 2 executes the step 1 of the embodiment 1;

the logic synthesis module 3 is used for executing the step 2 in the embodiment 1;

the place and route module 1 is used for executing steps 3-9 described in embodiment 1.