1. A dual-system starting method based on a multi-core processor is characterized by comprising the following steps:

responding to a system starting instruction, determining a system mirror image starting address in system engineering in an embedded framework according to the incidence relation between a system identifier and the system mirror image starting address, and loading the system mirror image into each core of the processor respectively;

calling a bootstrap program to respectively initialize each core of a processor and a tightly coupled memory of the processor, and closing a memory refreshing operation and a processor resetting operation of the processor;

and according to the equipment tree file, allocating the peripheral resources of the processor to each core of the processor, and respectively operating the system on each core of the processor.

2. The method of claim 1, wherein determining a system image boot address in system engineering in an embedded framework according to an association relationship between a system identifier and the system image boot address, and loading the system image into each core of the processor, respectively, comprises:

determining a first system image starting address associated with a first system in the system engineering of the embedded architecture, and loading the first system image into a first core of the processor;

determining a second system image starting address associated with a second system in the system engineering of the embedded architecture, and loading the second system image into a second core of the processor; and the first system image starting address is different from the second system image starting address.

3. The method of claim 1, wherein allocating peripheral resources of the processor to cores of the processor according to a device tree file comprises:

according to the interrupt controller distribution information of the equipment tree file, taking an interrupt controller as a peripheral resource commonly used by each core of the processor;

and taking the tightly coupled memory as an external resource independently used by each core of the processor according to the tightly coupled memory allocation information of the equipment tree file.

4. The method of claim 3, wherein after said using an interrupt controller as a peripheral resource for common use by cores of said processor, said method further comprises:

determining a target core in the processor according to the initialization main body information of the interrupt controller preset in the equipment tree file, and initializing the interrupt controller by using the target core so that the interrupt controller can send the generated interrupt number to the target core; wherein the target core is a core of the processor.

5. The method of claim 3, wherein the tightly coupled memory further stores an interrupt vector table for each core of the processor.

6. The method of claim 2, wherein the first system and the second system employ an OpenAMP architecture or a shared memory mechanism for inter-core communication.

7. The method of claim 1, wherein the first system and the second system are both VxWorks systems and the processor is a dual core Cortex-R5.

8. A dual-system starting device based on a multi-core processor is characterized by comprising:

the system mirror image determining module is used for responding to a system starting instruction, determining a system mirror image starting address in system engineering in an embedded framework according to the incidence relation between a system identifier and the system mirror image starting address, and loading the system mirror image into each core of the processor respectively;

the initialization module is used for calling a bootstrap program to respectively initialize each core of the processor and the tightly coupled memory of the processor, and closing the memory refresh operation and the processor reset operation of the processor;

and the peripheral resource allocation module is used for allocating the peripheral resources of the processor to each core of the processor according to the equipment tree file and respectively operating the system on each core of the processor.

9. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out a dual system boot method based on a multicore processor according to any of claims 1 to 7.

10. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the dual system boot method based on multicore processors according to any of claims 1 to 7 when executing the computer program.

Background

With the development of an Advanced Driver Assistance System (Advanced Driver Assistance System) and the increasing of the number of vehicle-mounted sensors, the spatial complexity and the time complexity of an algorithm are increased, the requirement of software on a hardware platform is higher and higher, the utilization rate of the software on the hardware is improved under the same hardware platform, and the System can run better.

The Cortex-R5 processor provides a high-performance solution for real-time application in the automobile market, and the vehicle microcontroller adopts the dual-core Cortex-R5, so that the raw material purchasing and developing cost can be reduced, the system-level real-time behavior is enhanced, and the system safety is improved. The Zynqmp chip for the vehicle comprises two heterogeneous Cortex-R5 kernel hardware and an AMP (asymmetric multi-process) mode supporting a VxWorks operating system, but the VxWorks system can only run on a single core on the Cortex-R5 at present, and waste of hardware resources is caused.

Disclosure of Invention

The embodiment of the application provides a dual-system starting method based on a multi-core processor, which can realize that two systems can be operated independently on the multi-core processor at the same time, thereby improving the utilization rate of hardware resources and improving the system performance.

In a first aspect, an embodiment of the present application provides a dual system starting method based on a multi-core processor, where the method includes:

responding to a system starting instruction, determining a system mirror image starting address in system engineering in an embedded framework according to the incidence relation between a system identifier and the system mirror image starting address, and loading the system mirror image into each core of the processor respectively;

calling a bootstrap program to respectively initialize each core of a processor and a tightly coupled memory of the processor, and closing a memory refreshing operation and a processor resetting operation of the processor;

and according to the equipment tree file, allocating the peripheral resources of the processor to each core of the processor, and respectively operating the system on each core of the processor.

In a second aspect, an embodiment of the present application provides a dual system boot apparatus based on a multi-core processor, where the apparatus includes:

the system mirror image determining module is used for responding to a system starting instruction, determining a system mirror image starting address in system engineering in an embedded framework according to the incidence relation between a system identifier and the system mirror image starting address, and loading the system mirror image into each core of the processor respectively;

the initialization module is used for calling a bootstrap program to respectively initialize each core of the processor and the tightly coupled memory of the processor, and closing the memory refresh operation and the processor reset operation of the processor;

and the peripheral resource allocation module is used for allocating the peripheral resources of the processor to each core of the processor according to the equipment tree file and respectively operating the system on each core of the processor.

In a third aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements a dual system boot method based on a multi-core processor according to an embodiment of the present application.

In a fourth aspect, an embodiment of the present application provides an electronic device, which includes a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor executes the computer program to implement the dual system booting method based on a multi-core processor according to the embodiment of the present application.

According to the technical scheme provided by the embodiment of the application, in response to a system starting instruction, according to the incidence relation between a system identifier and a system image starting address, the system image starting address is determined in system engineering in an embedded framework, the system image is loaded into each core of a processor respectively, a bootstrap program is called to initialize each core of the processor and a tightly coupled memory of the processor respectively, the memory refreshing operation and the processor resetting operation of the processor are closed, the peripheral resources of the processor are distributed to each core of the processor according to a device tree file, and the system is operated on each core of the processor respectively. According to the embodiment of the application, the operating systems are respectively configured for the cores of the processor, the operating systems are respectively guided, and the peripheral resources are configured for the operating systems, so that two systems can be independently operated on the multi-core processor at the same time, the utilization rate of hardware resources is improved, and the system performance is improved.

Drawings

FIG. 1 is a flowchart of a dual system boot method based on a multi-core processor according to an embodiment of the present disclosure;

FIG. 2 is a flowchart of a dual system booting method based on a multi-core processor according to a second embodiment of the present application;

fig. 3 is a schematic structural diagram of a dual system starting apparatus based on a multi-core processor according to a third embodiment of the present application;

fig. 4 is a schematic structural diagram of an electronic device according to a fifth embodiment of the present application.

Detailed Description

The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application. It should be further noted that, for the convenience of description, only some of the structures related to the present application are shown in the drawings, not all of the structures.

Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, many of the steps can be performed in parallel, concurrently or simultaneously. In addition, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figure. The processes may correspond to methods, functions, procedures, subroutines, and the like.

Example one

Fig. 1 is a flowchart of a dual system starting method based on a multi-core processor according to an embodiment of the present application, where the embodiment is applicable to a case where operating systems are respectively run on cores of the dual-core processor. The method can be executed by the dual-system starting device based on the multi-core processor, which can be realized by software and/or hardware, and can be integrated in the electronic equipment running the system.

As shown in fig. 1, the dual system booting method based on a multi-core processor includes:

s110, responding to a system starting instruction, determining a system mirror image starting address in system engineering in an embedded framework according to the incidence relation between a system identification and the system mirror image starting address, and loading the system mirror image into each core of the processor respectively.

The system starting instruction refers to an instruction for triggering the operating system to start, and optionally, the system starting instruction is a signal for completing power-on or reset of the processor. The system identifier is information that can uniquely identify one operating system, and is used to distinguish different operating systems, and optionally, the system identifier includes: system type, version number, system name, and system storage information. The system mirror image is a single file which is made of a specific series of files according to a certain format, so that a user can conveniently download and use the system mirror image, the system mirror image can be identified by specific software, and the system mirror image comprises: system files, boot files, partition table information, and the like. The system image boot address refers to an entry address for reading a system image boot code.

Each system has a corresponding system image, and there is an association relationship between the system identifier and the system image start address, that is, in the case that the information of either one of the system identifier and the system image start address is known, the information of the other can be determined.

In an optional embodiment, determining a system image boot address in system engineering in an embedded framework according to an association relationship between a system identifier and the system image boot address, and loading the system image to each core of the processor respectively includes: determining a first system image starting address associated with a first system in the system engineering of the embedded architecture, and loading the first system image into a first core of the processor; determining a second system image starting address associated with a second system in the system engineering of the embedded architecture, and loading the second system image into a second core of the processor; and the first system image starting address is different from the second system image starting address.

The method comprises the steps of establishing an incidence relation between a system identifier and a system mirror image starting address, specifically, establishing a system project corresponding to an embedded architecture for each operating system in a workbench IDE environment, wherein the system project comprises a system mirror image, and the system project has the corresponding mirror image starting address. In an alternative embodiment, the first system and the second system are both VxWorks systems and the processor is a dual core Cortex-R5. The VxWorks is an embedded real-time operating system and is a key component of an embedded development environment. The embedded real-time operating system has good continuous development capability, a high-performance kernel and a friendly user development environment, and occupies a place in the field of embedded real-time operating systems. The method is widely applied to the fields with high-precision technologies such as communication, military, aviation, aerospace and the like and extremely high real-time requirements by virtue of good reliability and excellent real-time performance.

Illustratively, VxWorks is run on a dual-core Cortex-R5 processor, for convenience, two cores of the dual-core Cortex-R5 processor are respectively called core 1 and core 2, specifically, VxWorks systems are respectively run on the core 1 and the core 2, the two operating systems are called a first system and a second system, the first system and the second system respectively correspond to a first system mirror image starting address and a second system mirror image starting address, the first system mirror image starting address is different from the second system mirror image starting address, and the first system mirror image are respectively loaded into the core 1 and the core 2 according to the first system mirror image starting address and the second system mirror image starting address. It should be noted that the above exemplary contents are only used to explain the embodiment of the present invention, and do not limit the embodiment of the present invention, and the first system and the second system may be any operating system that can run on an embedded device, such as a Linux system, and may be determined according to practical situations, and are not limited herein. Similarly, the multi-core processor is not limited to a dual core Cortex-R5 processor.

S120, calling a bootstrap program to respectively initialize each core of the processor and the tightly coupled memory of the processor, and closing the memory refreshing operation and the processor resetting operation of the processor.

The system image includes a boot program, which is a program for booting an operating system. The booting process is a process that a computer starts inputting, and the booting process is a process that a device inputs a small amount of instructions and data after the computer is started, and then the instructions and the data are input into other programs. Optionally, the bootstrap program is U-Boot (universal Boot loader), the U-Boot is a Bootloader that is commonly used in an embedded system, the Bootloader is a section of program that is executed before an operating system runs, and a hardware device and a mapping table of a memory space can be initialized through the Bootloader, so that a proper software and hardware environment is established, and preparation is made for finally calling an operating system kernel. The U-Boot can support various embedded operating system kernels, can support a plurality of processor series, and has high reliability and stability.

Running the operating system in AMP mode requires a separate boot program to boot the operating system running on each core in the processor. Therefore, when the operating system is started, a corresponding bootstrap program needs to be set for each operating system running on the multi-core processor, the bootstrap program comprises an initialization code and a bootstrap code, and the bootstrap program is called to initialize each core of the processor and the tightly coupled memory of the processor respectively.

When the multi-core processor is a Cortex-R5 dual-core processor, only one R5 core can be guided due to the default of the U-Boot issued by the government, and a plurality of R5 cores which are not supported can be guided. Therefore, corresponding initialization code and Boot code need to be added to the other R5 core of the Cortex-R5 processor in the U-Boot released by the government to complete the initialization of the dual cores of the Cortex-R5 processor.

Because the operating system must operate by using the peripheral resources of the processor, and because the peripheral resources owned by each core of the processor are the same and fixed, the probability of resource conflict is high in the process of starting and operating the dual operating system, and the Tightly Coupled Memory (TCM) is an on-chip fast Memory area and has the same performance as the on-chip cache. But TCM can be completely program controlled with better predictability than statistically multiplexed caching. In the case of a multi-core processor running dual systems, TCM is a very important peripheral resource. Therefore, it is necessary to initialize the TCM simultaneously with the initialization of each core of the processor. Since the U-Boot does not include relevant code for initializing the Tightly Coupled Memory (TCM) of the processor, it is necessary to add code for initializing the TCM to the U-Boot. In addition, in order to ensure that the dual system can be normally started and run to avoid system reset, a memory refresh operation (Dcache flush) of the processor and a processor reset (R5 cpu reset) operation are performed.

S130, according to the device tree file, distributing the peripheral resources of the processor to each core of the processor, and respectively operating the system on each core of the processor.

In the AMP mode, the operating systems on the two cores of the multi-core processor are operated independently, but the peripheral resources owned by the two cores in one processor are the same and fixed, so as to avoid resource conflict between the two operating systems, and therefore, the peripheral resources of the processor need to be reasonably allocated. Wherein, the peripheral resources include: processor, controller, access memory, tightly coupled memory, serial communication port, and integrated circuit bus. When the peripheral resources of the processor are allocated, a part of the peripheral resources such as the shared memory and the double data rate access memory can be used as the resources commonly used by the cores, and the rest of the resources such as the controller, the serial communication port and the integrated circuit bus can be used as the resources which are respectively and independently used.

According to the device tree file, the peripheral resources of the processor are allocated to the cores of the processor, specifically, the device tree files of the two systems can be modified respectively, and the peripheral resources which can be used by the cores of the processor are allocated. Where the device tree holds device information that exists in the system, the operating system builds this tree by using information obtained by the driver and other components when booting, and updates this tree when devices are added or deleted.

According to the technical scheme provided by the embodiment of the application, in response to a system starting instruction, according to the incidence relation between a system identifier and a system image starting address, the system image starting address is determined in system engineering in an embedded framework, the system image is loaded into each core of a processor respectively, a bootstrap program is called to initialize each core of the processor and a tightly coupled memory of the processor respectively, the memory refreshing operation and the processor resetting operation of the processor are closed, the peripheral resources of the processor are distributed to each core of the processor according to a device tree file, and the system is operated on each core of the processor respectively. According to the embodiment of the application, the operating systems are respectively configured for the cores of the processor, the operating systems are respectively guided, and the peripheral resources are configured for the operating systems, so that two systems can be independently operated on the multi-core processor at the same time, the utilization rate of hardware resources is improved, and the system performance is improved.

Example two

Fig. 2 is a flowchart of a dual system boot method based on a multi-core processor according to a second embodiment of the present application. The present embodiment is further optimized on the basis of the above-described embodiments. Specifically, the allocating, according to the device tree file, the peripheral resources of the processor to each core of the processor includes: according to the interrupt controller distribution information of the equipment tree file, taking an interrupt controller as a peripheral resource commonly used by each core of the processor; and taking the tightly coupled memory as an external resource independently used by each core of the processor according to the tightly coupled memory allocation information of the equipment tree file.

As shown in fig. 2, the dual system booting method based on the multi-core processor includes:

s210, responding to a system starting instruction, determining a system mirror image starting address in system engineering in an embedded framework according to the incidence relation between a system identifier and the system mirror image starting address, and loading the system mirror image into each core of the processor respectively.

S220, calling a bootstrap program to respectively initialize each core of the processor and the tightly coupled memory of the processor, and closing the memory refreshing operation and the processor resetting operation of the processor.

And S230, according to the interrupt controller distribution information of the equipment tree file, taking an interrupt controller as a peripheral resource commonly used by each core of the processor.

The device tree file includes allocation information of the interrupt controllers (GICs), and the allocation of the interrupt controllers can be modified by modifying the device tree file. The GIC can be initialized only once after the processor is powered on, the GIC is used as a peripheral resource commonly used by all cores of the processor, one core is selected from all the cores of the processor to initialize the GIC after the processor is powered on, and the GIC is the peripheral resource commonly used by all the cores of the processor because any one core of the processor can initialize the GIC.

In an optional embodiment, after the taking the interrupt controller as a peripheral resource commonly used by the cores of the processor, the method further includes: determining a target core in the processor according to the initialization main body information of the interrupt controller preset in the equipment tree file, and initializing the interrupt controller by using the target core so that the interrupt controller can send the generated interrupt number to the target core; wherein the target core is a core of the processor.

The interrupt controller initialization main body information refers to information for determining the core for initializing the GIC at this time after the processor is powered on. The interrupt controller initialization subject information is determined by the relevant technical personnel according to the actual situation and is written into the device tree file in advance, and is not limited herein. And determining a target core in the processor according to the initialization main body information of the interrupt controller, and finishing the work of initializing the interrupt controller by using the target core. After the interrupt number generated by the specified device is sent to the target core initialized for the time by the interrupt controller.

Illustratively, core 1 is selected as a target core from two cores, i.e., core 1 and core 2, of a dual-core Cortex-R5 processor, the GIC can be initialized only once after the processor is powered on, and if the code for initializing the GIC by core 2 exists, the GIC needs to be deleted.

In order to solve the problem of address conflict of the interrupt vector table during the startup and operation of the dual system, in an optional embodiment, the tightly coupled memory further stores the interrupt vector table of each core of the processor. Because the VxWorks system defaults to placing the interrupt vector table in a shared Memory (OCM, On Chip Memory) commonly used by two cores of the dual-core Cortex-R5, the address use of the interrupt vector tables of the two systems is conflicted, namely the interrupt vector table of one system is covered by the interrupt vector table of the other system, the problem can be solved by placing the interrupt vector table in a TCM Memory, and the TCM is a Memory space which is respectively and independently used by the two cores of the Cortex-R5, so that the situation that one table is covered by the other table cannot be caused.

S240, according to the tight coupling memory allocation information of the equipment tree file, taking the tight coupling memory as a peripheral resource independently used by each core of the processor.

In order to improve the working efficiency of the processor and the stability of system operation, two independently operating systems on the multi-core processor can carry out inter-core communication in the system operation process. In an optional embodiment, the first system and the second system use an OpenAMP architecture or a shared memory mechanism for inter-core communication. The OpenAMP architecture is an event-type communication mechanism, and occupies less system resources, and correspondingly, the data throughput of the mechanism is smaller; the shared memory mechanism is a polling communication mechanism, the data throughput is large, but the occupied system resource amount is large, and two inter-core communication modes can be selected according to actual situations and are not limited herein.

According to the embodiment of the application, the interrupt controller is used as the peripheral resource commonly used by each core of the processor according to the interrupt controller distribution information of the equipment tree file, the interrupt vector table is stored in the tightly coupled memory, and the peripheral resource of the multi-core processor is reasonably distributed to each core of the processor, so that the normal starting and running of the dual systems are ensured, the resource conflict generated by the two systems is avoided, the two systems can be independently run on the multi-core processor at the same time, the utilization rate of hardware resources is improved, and the system performance is improved.

EXAMPLE III

Fig. 3 is a dual system starting apparatus based on a multi-core processor according to a third embodiment of the present application, where the present embodiment is applicable to a case where operating systems are respectively run on cores of the dual-core processor. The device can be realized by software and/or hardware, and can be integrated in electronic equipment such as an intelligent terminal.

As shown in fig. 3, the apparatus may include: a system image determination module 310, an initialization module 320, and a peripheral resource allocation module 330.

A system image determining module 310, configured to determine a system image starting address in a system engineering in an embedded framework according to an association relationship between a system identifier and the system image starting address in response to a system starting instruction, and load the system image into each core of the processor respectively;

an initialization module 320, configured to invoke a boot program to initialize each core of a processor and a tightly coupled memory of the processor, and close a memory refresh operation and a processor reset operation of the processor;

the peripheral resource allocation module 330 is configured to allocate, according to the device tree file, peripheral resources of the processor to each core of the processor, and run a system on each core of the processor.

According to the technical scheme provided by the embodiment of the application, in response to a system starting instruction, according to the incidence relation between a system identifier and a system image starting address, the system image starting address is determined in system engineering in an embedded framework, the system image is loaded into each core of a processor respectively, a bootstrap program is called to initialize each core of the processor and a tightly coupled memory of the processor respectively, the memory refreshing operation and the processor resetting operation of the processor are closed, the peripheral resources of the processor are distributed to each core of the processor according to a device tree file, and the system is operated on each core of the processor respectively. According to the embodiment of the application, the operating systems are respectively configured for the cores of the processor, the operating systems are respectively guided, and the peripheral resources are configured for the operating systems, so that two systems can be independently operated on the multi-core processor at the same time, the utilization rate of hardware resources is improved, and the system performance is improved.

Optionally, the system image determining module 310 includes:

a first system image starting address determining submodule, configured to determine a first system image starting address associated with a first system in system engineering of the embedded architecture, and load the first system image into a first core of the processor;

a second system image starting address determining submodule for determining a second system image starting address associated with a second system in the system engineering of the embedded architecture and loading the second system image into a second core of the processor; and the first system image starting address is different from the second system image starting address.

Optionally, the peripheral resource allocation module 330 includes: the first peripheral resource allocation submodule is used for taking an interrupt controller as a peripheral resource commonly used by cores of the processor according to the interrupt controller allocation information of the equipment tree file;

and the second external resource allocation submodule is used for taking the tightly coupled memory as an external resource independently used by each core of the processor according to the tightly coupled memory allocation information of the equipment tree file.

Optionally, the apparatus further comprises: an interrupt controller initialization module, configured to determine a target core in the processor according to interrupt controller initialization main body information preset in the device tree file after the interrupt controller is used as a peripheral resource commonly used by each core of the processor, and initialize the interrupt controller by using the target core, so that the interrupt controller sends a generated interrupt number to the target core; wherein the target core is a core of the processor.

Optionally, the tightly coupled memory further stores an interrupt vector table of each core of the processor.

Optionally, the first system and the second system use an OpenAMP architecture or a shared memory mechanism for inter-core communication.

Optionally, the first system and the second system are both VxWorks systems, and the processor is a dual-core Cortex-R5.

The dual-system starting device based on the multi-core processor provided by the embodiment of the invention can execute the dual-system starting method based on the multi-core processor provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of executing the dual-system starting method based on the multi-core processor.

Example four

The fourth embodiment of the present application further provides a storage medium containing computer-executable instructions, where the computer-executable instructions are executed by a computer processor to perform a dual system boot method based on a multi-core processor, and the method includes:

responding to a system starting instruction, determining a system mirror image starting address in system engineering in an embedded framework according to the incidence relation between a system identifier and the system mirror image starting address, and loading the system mirror image into each core of the processor respectively;

calling a bootstrap program to respectively initialize each core of a processor and a tightly coupled memory of the processor, and closing a memory refreshing operation and a processor resetting operation of the processor;

and according to the equipment tree file, allocating the peripheral resources of the processor to each core of the processor, and respectively operating the system on each core of the processor.

Storage media refers to any of various types of memory electronics or storage electronics. The term "storage medium" is intended to include: mounting media such as CD-ROM, floppy disk, or tape devices; computer system memory or random access memory such as DRAM, DDR RAM, SRAM, EDO RAM, Lanbas (Rambus) RAM, etc.; non-volatile memory such as flash memory, magnetic media (e.g., hard disk or optical storage); registers or other similar types of memory elements, etc. The storage medium may also include other types of memory or combinations thereof. In addition, the storage medium may be located in the computer system in which the program is executed, or may be located in a different second computer system connected to the computer system through a network (such as the internet). The second computer system may provide the program instructions to the computer for execution. The term "storage medium" may include two or more storage media that may reside in different unknowns (e.g., in different computer systems connected by a network). The storage medium may store program instructions (e.g., embodied as a computer program) that are executable by one or more processors.

Of course, the storage medium containing the computer-executable instructions provided in the embodiments of the present application is not limited to the dual system booting operation based on the multi-core processor described above, and may also perform related operations in the dual system booting method based on the multi-core processor provided in any embodiment of the present application.

EXAMPLE five

An embodiment of the present invention provides an electronic device, where the dual system starting apparatus based on a multi-core processor provided in the embodiment of the present invention may be integrated in the electronic device, and the electronic device may be configured in a system, or may be a device that executes part or all of functions in the system. Fig. 4 is a schematic structural diagram of an electronic device according to a fifth embodiment of the present application. As shown in fig. 4, the present embodiment provides an electronic device 400, which includes: one or more processors 420; the storage device 410 is configured to store one or more programs, and when the one or more programs are executed by the one or more processors 420, the one or more processors 420 implement the dual system boot method based on a multi-core processor according to the embodiment of the present application, the method includes:

responding to a system starting instruction, determining a system mirror image starting address in system engineering in an embedded framework according to the incidence relation between a system identifier and the system mirror image starting address, and loading the system mirror image into each core of the processor respectively;

calling a bootstrap program to respectively initialize each core of a processor and a tightly coupled memory of the processor, and closing a memory refreshing operation and a processor resetting operation of the processor;

and according to the equipment tree file, allocating the peripheral resources of the processor to each core of the processor, and respectively operating the system on each core of the processor.

Of course, it can be understood by those skilled in the art that the processor 420 also implements the technical solution of the dual system booting method based on the multi-core processor provided in any embodiment of the present application.

The electronic device 400 shown in fig. 4 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiments of the present application.

As shown in fig. 4, the electronic device 400 includes a processor 420, a storage device 410, an input device 430, and an output device 440; the number of the processors 420 in the electronic device may be one or more, and one processor 420 is taken as an example in fig. 4; the processor 420, the storage device 410, the input device 430, and the output device 440 in the electronic apparatus may be connected by a bus or other means, and are exemplified by a bus 450 in fig. 4.

The storage device 410 is a computer-readable storage medium, and can be used to store software programs, computer-executable programs, and module units, such as program instructions corresponding to the dual system booting method based on multi-core processor in the embodiment of the present application.

The storage device 410 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal, and the like. Further, the storage 410 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some examples, storage 410 may further include memory located remotely from processor 420, which may be connected via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The input means 430 may be used to receive input numbers, character information, or voice information, and to generate key signal inputs related to user settings and function control of the electronic device. The output device 440 may include a display screen, speakers, or other electronic equipment.

The dual-system starting device, the medium and the electronic equipment based on the multi-core processor, which are provided by the embodiment, can execute the dual-system starting method based on the multi-core processor, which is provided by any embodiment of the application, and have corresponding functional modules and beneficial effects for executing the method. Technical details that are not described in detail in the above embodiments may be referred to a dual system boot method based on a multi-core processor provided in any embodiment of the present application.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present application and the technical principles employed. It will be understood by those skilled in the art that the present application is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the application. Therefore, although the present application has been described in more detail with reference to the above embodiments, the present application is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present application, and the scope of the present application is determined by the scope of the appended claims.