1. A method for realizing a PLC high-speed differential backplane bus by using an efficient coding and decoding rule is characterized by comprising the following steps:

step 1, a PLC backboard bus adopts LVDS differential data lines to transmit data frames;

step 2, adding CRC32 check code to the data frame;

step 3, carrying out 8B/10B coding on the data in the data frame and then carrying out bottom layer data transmission;

and 4, performing CRC32 check on the received data frame by the PLC, wherein the data frame can be received only when the data check is passed, otherwise, the data frame can be discarded.

2. The method for realizing the PLC high-speed differential backplane bus according to the claim 1, wherein the data frame is composed of a synchronization header, a K code, service data and a CRC32 check code.

3. The method of claim 2, wherein the K code is used to identify the start and end of a data frame.

4. The method according to claim 1, wherein the LVDS differential data lines provide a transmission rate of 40M for the backplane bus.

5. The method according to claim 1, wherein the LVDS differential data reception and transmission are implemented by an FPGA internal circuit.

6. The method for realizing the PLC high-speed differential backplane bus according to the claim 1, wherein the step 3 can prevent the level transmitted on the differential line from appearing to be "1" or "0" continuously exceeding 5 clock cycles.

7. The method according to claim 4, wherein the LVDS differential data lines provide a backplane bus with a transmission rate of 40M.

Background

The PLC and the distributed IO are widely applied to various industries such as metallurgy, automobile, electric power, petrifaction, environmental protection, intelligent agriculture and the like. The backplane bus is a very key technology of PLC and distributed IO, and through the backplane bus, a user can flexibly configure IO modules according to actual project requirements.

The traditional backboard bus adopts an SPI technology, the transmission rate of the technology is low, and in some application scenes with large interference, the backboard bus is easily interfered, so that the IO module is abnormal.

Disclosure of Invention

The invention aims to provide a method for realizing a PLC high-speed differential backplane bus by using an efficient coding and decoding rule so as to solve the problems in the background technology.

In order to achieve the purpose, the invention provides the following technical scheme:

a method for realizing a PLC high-speed differential backplane bus by using efficient coding and decoding rules comprises the following steps:

step 1, a PLC backboard bus adopts LVDS differential data lines to transmit data frames;

step 2, adding CRC32 check code to the data frame;

step 3, carrying out 8B/10B coding on the data in the data frame and then carrying out bottom layer data transmission;

and 4, performing CRC32 check on the received data frame by the PLC, wherein the data frame can be received only when the data check is passed, otherwise, the data frame can be discarded.

As a further technical scheme of the invention: the data frame is composed of a synchronization header, a K code, service data and a CRC32 check code.

As a further technical scheme of the invention: the K code is used to identify the start and end of a data frame.

As a further technical scheme of the invention: the LVDS differential data lines provide a backplane bus with a transmission rate of 40M.

As a further technical scheme of the invention: LVDS differential data receiving and sending are realized by an FPGA internal circuit.

As a further technical scheme of the invention: step 3 enables the level transmitted on the differential line not to appear as a "1" or a "0" for more than 5 clock cycles in succession.

As a further technical scheme of the invention: the LVDS differential data lines provide a backplane bus with a transmission rate of 40M.

Compared with the prior art, the invention has the beneficial effects that: the invention adopts the high-speed backboard bus of the technology to provide a method for expanding the high-speed low-delay IO module for PLC or distributed IO. And can be stably and reliably applied to some severe interference environments.

Drawings

FIG. 1 is a LVDS differential circuit diagram;

FIG. 2 is a diagram of a data frame structure;

fig. 3 is a data transmission physical layer link diagram.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Example 1: referring to fig. 1-3, a method for implementing a PLC high-speed differential backplane bus according to an efficient encoding and decoding rule includes the following steps:

step 1, a PLC backboard bus adopts LVDS differential data lines to transmit data frames; the VDS differential data line provides 40M transmission rate for the backboard bus, which is 10 times of the transmission rate of the traditional backboard bus; the data frame is composed of a synchronization header, a K code, service data and a CRC32 check code, wherein the K code is used for identifying the start and end of the data frame, and the data frame is as shown in fig. 2;

step 2, adding CRC32 check code to the data frame;

step 3, carrying out 8B/10B coding on the data in the data frame and then carrying out bottom layer data transmission; the level transmitted on the differential line can not generate 1 or 0 continuously exceeding 5 clock cycles, and the anti-interference capability of the backplane bus is greatly improved;

and 4, performing CRC32 check on the received data frame by the PLC, wherein the data frame can be received only when the data check is passed, otherwise, the data frame can be discarded.

Example 2: on the basis of embodiment 1, the LVDS differential data reception and transmission are both realized by an internal circuit of the FPGA without peripheral expansion of a related circuit, which not only saves cost and reduces system power consumption, but also reduces the fault probability of the system, and the LVDS differential circuit is shown in fig. 1.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.