1. A system for managing communications between a host device and a terminal device, the system comprising:

a programmable input/output port associated with the host device, the host device capable of connecting to a plurality of different types of end devices via the programmable input/output port and a cable, the plurality of different types of end devices respectively associated with different types of protocols;

a port manager to:

detecting a signal from a terminal device interface associated with the terminal device;

determining a type of the terminal device based on the detected signal; and

directing the programmable input/output port to present signals corresponding to a protocol associated with the determined type of the end device to allow the host device to communicate with the end device.

2. The system of claim 1, wherein the programmable input/output port is to present different signals corresponding to different protocols respectively associated with different types of end devices.

3. The system of claim 1, wherein the programmable input/output port comprises a programmable terminal to present the signal.

4. The system of claim 3, further comprising a programmable logic device for programming the programmable terminal to present the signal.

5. The system of claim 4, wherein the port manager is to instruct the programmable logic device to program the programmable terminal to present the signal corresponding to the protocol associated with the determined type of the end device.

6. The system of claim 1, wherein the plurality of different types of terminal devices are respectively associated with different types of terminal device interfaces, the different types of terminal device interfaces including at least one of a non-volatile memory express (NVME) backplane, a peripheral component interconnect express (PCIe) slot, and an Open Computing Project (OCP) slot.

7. The system of claim 1, wherein the host device comprises a Central Processing Unit (CPU).

8. The system of claim 7, wherein the terminal device comprises another CPU.

9. A method of managing communication between a host device and a terminal device, comprising:

detecting a signal from an end device interface associated with the end device, the end device being connected to the host device via a cable and a programmable input/output port associated with the host device, the host device being connectable to a plurality of different types of end devices, the plurality of different types of end devices being respectively associated with different types of protocols;

determining a type of the terminal device based on the detected signal; and

directing the programmable input/output port to present signals corresponding to a protocol associated with the determined type of the end device to allow the host device to communicate with the end device.

10. The method of claim 9, wherein the programmable input/output port presents different signals corresponding to different protocols respectively associated with different types of end devices.

11. The method of claim 9, wherein the programmable input/output port comprises a programmable terminal to present the signal.

12. The method of claim 11, wherein directing the programmable input/output port to present signals corresponding to a protocol associated with the determined type of the end device comprises: instructing a programmable logic device to program the terminal to present the signal.

13. The method of claim 9, wherein the plurality of different types of devices are respectively associated with different types of terminal device interfaces comprising at least one of a non-volatile memory express (NVME) backplane, a peripheral component interconnect express (PCIe) slot, and an Open Computing Project (OCP) slot.

14. The method of claim 9, wherein the host device comprises a Central Processing Unit (CPU).

15. The method of claim 14, wherein the terminal device comprises another CPU.

16. A non-transitory computer-readable storage medium comprising computer-executable instructions stored thereon, which, when executed by a processor, cause the processor to manage communication between a host device and a terminal device by:

detecting a signal from an end device interface associated with the end device, the end device being connected to the host device via a cable and a programmable input/output port associated with the host device, the host device being connectable to a plurality of different types of end devices via a cable and a programmable input/output port associated with the host device, the plurality of different types of end devices being respectively associated with different types of protocols;

determining a type of the terminal device based on the detected signal; and

directing the programmable input/output port to present signals corresponding to a protocol associated with the determined type of the end device to allow the host device to communicate with the end device.

17. The non-transitory computer readable storage medium of claim 16, wherein the programmable input/output port is to present different signals corresponding to different protocols respectively associated with different types of end devices.

18. The non-transitory computer readable storage medium of claim 16, wherein the programmable input/output port includes a programmable terminal, and directing the programmable input/output port to present a signal corresponding to a protocol associated with the determined type of the end device comprises instructing a programmable logic device to program the terminal to present the signal.

19. The non-transitory computer-readable storage medium of claim 16, wherein the plurality of different types of devices are respectively associated with different types of terminal device interfaces, the different types of terminal device interfaces including at least one of a non-volatile memory express (NVME) backplane, a peripheral component interconnect express (PCIe) slot, and an Open Computing Project (OCP) slot.

20. The non-transitory computer readable storage medium of claim 15, wherein the host device comprises a Central Processing Unit (CPU) and the terminal device comprises another CPU.

Background

The computing system may be configurable to provide communication between the host device and a desired number of end devices. This configuration typically occurs at the device level.

Drawings

The disclosure is best understood from the following detailed description when read with the accompanying drawing figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a perspective view of an assembly including a host device and a terminal device interface according to one or more examples.

Fig. 2 illustrates pin assignments of a cable from the viewpoint of a programmable I/O port, according to one or more examples.

Figure 3 conceptually illustrates a system for managing communication between a host device and a terminal device via a Peripheral Component Interconnect Express (PCIe) slot, in accordance with one or more examples.

Figure 4A conceptually illustrates a system for managing communication between a host device and a terminal device via an Open Computing Project (OCP) Network Interface Card (NIC) slot, according to one or more examples.

Figure 4B conceptually illustrates a system for managing communications between a host device and a terminal device via respective OCP NIC slots, according to one or more examples.

Figure 5 conceptually illustrates a system for managing communication between a host device and an end device via a Non-volatile Memory Express Backplane (NVMe BP), according to one or more examples.

Figures 6A-6C conceptually illustrate a system for managing communication between a host device and one or more respective end devices via an interconnection processor link, according to one or more examples.

Fig. 7 is a flow diagram that describes a method for managing communications between a host device and a terminal device in accordance with one or more examples.

Figure 8 conceptually illustrates a computing device with which the port managers shown in figures 3-6C can be implemented, according to one or more examples.

Detailed Description

Examples of the subject matter claimed below will now be disclosed. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions may be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort, even if complex and time-consuming, would be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.

Many computing systems include host devices that communicate with different types of terminal devices using different respective communication protocols. As used herein, the term "host device" refers to, but is not limited to, a computing device that includes a processing unit. Examples of host devices may be central processing units, servers, blade servers, or any other device or equipment that includes controllers, processing resources, and so forth. The term "end device" refers to, but is not limited to, any device adapted to communicate with a host device including a processing unit. Examples of terminal devices include, but are not limited to, memory modules, hard drives or solid state drives, network connection devices (e.g., WiFi or ethernet cards), graphics processors, other computing devices, and the like.

In many computing systems, the host device is supported by a printed circuit board. The terminal device is connected to the host device via traces on the printed circuit board. Such connections are limited in flexibility due to the mounting of the traces on the printed circuit board.

In some cases, the host device and the terminal device are connected using a cable to allow high-speed data communication. The cable connects an input/output (I/O) port associated with the host device to a different end device. As used herein, the term "input/output (I/O) port" refers to a receptacle that includes a terminal into which one end of a cable is inserted. The I/O ports are in turn connected to a host device via appropriate connections (e.g., electrical contacts or a bus). The cable includes an I/O port connector at one end for connecting the cable to an I/O port, and a terminal device interface connector at the other end for connecting the cable to a terminal device interface. As used herein, the term "end device interface" refers to hardware into which a cable is plugged, such as an I/O slot, backplane, or I/O port connector. The terminal device interface, in turn, is connected to the terminal device via any suitable connection (e.g., electrical contacts or a bus).

Many computing systems use different I/O ports that are dedicated to different end device interfaces associated with different types of end devices, respectively, to allow a host device to communicate with the different types of end devices. The computing system switches between different I/O ports to allow the host device to communicate with different types of end devices. Switching between different I/O ports using dedicated I/O ports and switches requires space on the motherboard and increases the cost of the computing system.

To mitigate at least some of these problems, according to one or more examples disclosed herein, a host device is allowed to communicate using a single programmable I/O port and different types of end devices associated with different protocols. Based on the type of end device connected to the host device, the I/O port is directed to present signals corresponding to a protocol associated with the end device. Rather than switching between I/O ports, the I/O ports are suitably programmed to allow the host device to communicate with the end device using a protocol associated with the end device.

According to some examples, a system for managing communication between a host device and a terminal device is provided. The system includes a programmable input/output (I/O) port associated with a host device. The host device may be connected to a plurality of different types of end devices via cables and programmable I/O ports. A plurality of different types of terminal devices are respectively associated with different types of protocols. The system also includes a port manager that detects a signal from a terminal device interface associated with the terminal device and determines a type of the terminal device based on the detected signal. The port manager also directs the programmable I/O port to present signals corresponding to a protocol associated with the determined type of end device to allow the host device to communicate with the end device.

According to other examples, a method for managing communication between a host device and a terminal device is provided. The host device may be connected to a plurality of different types of end devices via cables and programmable I/O ports. A plurality of different types of terminal devices are respectively associated with different types of protocols. A signal is detected from a terminal device interface associated with a terminal device. The type of the terminal device is determined based on the detected signal. Directing the programmable I/O port to present a signal corresponding to a protocol associated with the determined type of end device to allow the host device to communicate with the end device.

According to other examples, a non-transitory computer-readable storage medium includes computer-executable instructions stored thereon that, when executed by a processor, cause the processor to manage communication between a host device and a terminal device. The host device may be connected to a plurality of different types of end devices via cables and programmable I/O ports. A plurality of different types of terminal devices are respectively associated with different types of protocols. The instructions, when executed, cause the processor to detect a signal from a terminal device interface associated with a terminal device. The instructions also cause the processor to determine a type of the end device based on the detected signal and direct the programmable I/O port to present a signal corresponding to a protocol associated with the determined type of the end device to allow the host device to communicate with the end device.

Fig. 1 is a perspective view of an assembly including a host device and a terminal device according to one or more examples. In the example shown in fig. 1, the assembly 100 includes one or more host devices 110 supported by a computing portion 105 of the motherboard referred to as a "computing Printed Circuit Board (PCB)". The assembly also includes one or more programmable I/O ports 120 associated with the host device 110.

The assembly 100 also includes a plurality of different types of terminal device interfaces 130, 140, and 150 supported by the motherboard. The end device interfaces are associated with a plurality of different types of end devices 135, 145, and 155, respectively, that may be supported by or connected to the motherboard. In the example shown in fig. 1, terminal device interface 130 is a peripheral component interconnect express (PCIe) slot associated with terminal device 135 (e.g., a graphics processor). The end device interface 140 is an Open Computing Project (OCP) Network Interface Card (NIC) slot associated with an end device 145 (e.g., an ethernet or Wifi card). Terminal equipment interface 150 is a high speed nonvolatile memory backplane (NVME-BP) associated with terminal equipment 155 that may include storage equipment. It should be understood that there may be other types of terminal device interfaces to connect to other types of terminal devices.

Host device 110 may be connected to a plurality of different types of end devices 135, 145, 155 via cables (not shown), programmable I/O ports 120, and end device interfaces 130, 140, and 150, respectively. Described in further detail below with reference to fig. 2-6C.

The assembly 100 also includes a system management portion 115 of the motherboard referred to as a "management PCB". The system management portion 115 may support management devices, such as programmable logic devices and port managers (not shown) for managing communications between the host device 110 and the end devices 135, 145, and 155. The programmable logic device and the port manager are described in further detail below with reference to fig. 3-6C.

Referring now to the details of the cable connecting the programmable I/O port 120 to the end device interface of fig. 2 (with continued reference to fig. 1), fig. 2 is a pin assignment 200 for the cable connecting the programmable I/O port (e.g., the programmable I/O port 120 shown in fig. 1) to the end device interface (e.g., the end device interfaces 130, 140, and 150 shown in fig. 1). Each of the programmable I/O ports 120 includes a receptacle for receiving a cable that connects the programmable I/O port 120 to an end device interface. According to one example, the programmable I/O port 120 includes programmable terminals (also referred to as "pins"). Terminals are "programmable" in the sense that they may present different signals based on instructions from a programmable logic device, as described in further detail below. The pin assignment 200 shown in fig. 2 is an example of a signal that may be presented by a terminal of a programmable I/O port to an I/O port connector on an end of a cable (not shown), as described in more detail with reference to fig. 3-6C.

In fig. 2, column 202 indicates the terminals on the programmable I/O port 120 that present the signals, columns 205 and 210 indicate the order of contact of the terminals (indicating the order in which the terminals are in contact with the I/O port connector at the end of the cable), column 215 indicates the signals presented by the programmable I/O port 120 to the B-side of the I/O port connector at the end of the cable, and column 220 indicates the signals presented by the programmable I/O port 120 to the a-side of the I/O port connector at the end of the cable.

In the example shown in FIG. 2, the pin assignment 200 is for a Small Form Factor (SFF) cable, such as a standard SFF-TA-10023C cable with signals to be presented to PCIe x16 slots. It should be understood that this pin assignment is provided for illustrative purposes, and that other pin assignments for other types of cables may be used.

According to some examples, the signal presented by the programmable I/O port according to the pin assignment may be considered a default signal that is presented if no signal from an end device interface outside of the PCIe slot is detected. However, in the event a signal is detected from another type of end device interface other than a PCIe slot, a terminal of a programmable I/O port (e.g., programmable I/O port 120 shown in fig. 1) can be programmed to present a signal corresponding to a protocol associated with the end device associated with the detected signal. This can be understood with reference to fig. 3-5 described below.

Figure 3 conceptually illustrates a system 300 for managing communications between a host device and an end device via a PCIe slot, in accordance with one or more examples. The system 300 includes a programmable I/O port 305.

Referring to FIG. 3, programmable I/O port 305 is associated with a host device (not shown), such as host device 110 shown in FIG. 1. The system 300 includes a terminal device interface 320 associated with a terminal device (also not shown), such as the terminal device 135 shown in fig. 1. The system 300 also includes a cable 330 for connecting the end device interface 320 and the programmable I/O port 305. The cable 330 includes an I/O port connector 310 at one end for connecting to the programmable I/O port 305, and a terminal device interface connector 325 at the other end for connecting to the terminal device interface 320.

The system 300 further includes a processor for communicating via an inter-integrated circuit (I2C or I)²C cable) port manager 340 that detects signals from end device interface 320. Port manager 340 may determine the type of end device based on the detected signal.

In some examples, port manager 340 may have motherboard specification data stored in memory that specifies what types of terminal device interfaces are mounted on the motherboard and the mounting locations of those terminal device interfaces. When a signal is detected from the end device interface, the port manager 340 uses the stored specification data to determine the type of connected end device. For example, when a signal is detected from a PCIe slot, port manager 340 determines, based on the specification data, that the detected signal is from a PCIe slot and that the type of end device is a PCIe device. Port manager 340 directs programmable I/O port 305 to present signals corresponding to the protocol associated with the determined type of end device to allow the host device to communicate with the end device via cable 330 and end device interface 320.

The programmable I/O port 305 includes programmable terminals for presenting signals to the cable 330 via the I/O port connector 310. The programmable terminals are programmed by a programmable logic device 350 included in the system 300. The port manager 340 is operable to instruct the programmable logic device 350 to program the programmable terminals of the programmable I/O port 305 to present signals corresponding to the protocol associated with the determined type of end device to the I/O port connector 310.

According to one or more examples, the port manager 340 instructs the programmable logic device 350 to program a programmable terminal (not otherwise shown) of the programmable I/O port 305 by providing an instruction corresponding to a select statement in the programmable logic device 350. The selection statement may define how the programmable logic device 350 programs the programmable I/O port 305. For example, if the port manager 340 provides the instruction "00," the programmable logic device 350 programs the programmable terminals of the programmable I/O port 305 to present a first set of signals. On the other hand, if the port manager 340 provides the instruction "01," the programmable logic device 350 programs the programmable terminals of the programmable I/O port 305 to present a different set of signals. The programmable logic device 350 "programs" the terminals by causing the programmable terminals of the programmable I/O ports to output signals corresponding to the protocol associated with the determined type of terminal device.

In the example system 300 shown in FIG. 3, end device interface 320 is a PCIe slot and end device interface connector 325 is a PCIe I/O connector. For purposes of illustration, the port manager 340 is shown instructing the programmable logic device 350 to send signals "PRSNT 2 #", "CLKREQ," and "PWR _ BRAKE #" to the programmable I/O port 305 to program the programmable I/O port 305 to present these signals. Assuming that the PCIe slot is the "default" end device interface (for which the I/O port has been programmed to present signals via cable 330), port manager 340 may not instruct programmable logic device 350 to program the programmable I/O port to present signals. That is, for the default case of a PCIe slot, programmable I/O port 305 would present signals "PRSNT 2 #", "CLKREQ," and "PWR _ BRAKE #", on the a side of terminal 54, the B side of terminal 2, and the a side of the terminal, respectively, without programming by programmable logic device 350.

In the example system 300 shown in fig. 3, the cable 330 is a 16-way (x16) cable. However, it should be understood that a double 8-way (x8) cable may be used instead.

Fig. 4A conceptually illustrates a system 400A for managing communications between a host device and a terminal device via an OCP NIC slot, according to one or more examples. The system 400A includes a programmable I/O port 405. Programmable I/O port 405 is associated with a host device (not shown), such as host device 110 shown in fig. 1. System 400A includes a terminal device interface 420 associated with a terminal device (also not shown), such as terminal device 145 shown in fig. 1. The system 400 also includes a cable 430 for connecting the end device interface 420 and the programmable I/O port 405. The cable 430 includes an I/O port connector 410 at one end for connecting to the programmable I/O port 405, and a terminal device interface connector 425 at the other end for connecting to the terminal device interface 420.

The system 400A also includes a port manager 440 connected to the end device interface 420 via an I2C cable. The port manager 440 is configured to detect a signal from the end device interface 420 and determine the type of end device based on the detected signal. Port manager 440 directs programmable I/O port 405 to present signals corresponding to the protocol associated with the determined type of end device to allow the host device to communicate with the end device via cable 430 and end device interface 420.

The programmable I/O port 405 includes programmable terminals (not otherwise shown) to present signals to the cable 430 via the I/O port connector 410. The programmable terminals are programmed by programmable logic device 450 included in system 400A. The port manager 440 is operable to instruct the programmable logic device 450 to program the programmable terminals of the programmable I/O port 405 to present signals to the I/O port connector 410 corresponding to the protocol associated with the determined type of end device.

In the example system 400A shown in fig. 4A, the end device interface 420 is an OCP slot and the end device interface connector 425 is an OCP I/O connector. Since this is not the default case, port manager 440 instructs programmable logic device 450 to send signals "PAL _ OCP _ CBL _ DETO", "EN _ CLK _100M _ OCP _ NIC _ EN _ N", and "PAL _ OCP _ CBL _ DET 1" to programmable I/O port 405 to program programmable I/O port 405 to present these signals. Thus, programmable I/O port 405 presents signals "PAL _ OCP _ CBL _ DETO", "EN _ CLK _100M _ OCP _ NIC _ EN _ N", and "PAL _ OCP _ CBL _ DET 1" on the a-side of terminal 54, the B-side of terminal 2, and the a-side of terminal 3, respectively.

In the example system 400A shown in fig. 4A, the end device interface 420 is a dual OCP slot connected to the programmable I/O port 405 via a 16-way (x16) cable 430. In another system 400B shown in fig. 4B, respective end device interfaces 420A and 420B are OCP slots connected to programmable I/O port 405 via respective 8-way (x8) cables 430A and 430B. To determine whether to use an x16 cable connection or an x8 cable connection, a cable loop back detection may be performed. That is, the signal "PAL _ OCP _ CBL _ DET" may be sent from the programmable I/O port 405 to the end device interface 420 shown in fig. 4A. If the programmable I/O port 405 detects both "PAL _ OCP _ CBL _ DETO" and "PAL _ OCP _ CBL _ DET 1" from the cable loop back, the host device associated with the programmable I/O port 405 may determine to use the system 400A in FIG. 4A. If the programmable I/O port 405 detects the signal "PAL _ OCP _ CB: _ DETO" but does not detect the signal "PAL _ OCP _ CBL _ DET1," the host device associated with the programmable I/O port may determine to use the system in FIG. 4B.

The system 400B shown in fig. 4B includes dual programmable I/O ports 405A and 405B associated with a host device (not shown), such as the host device 110 shown in fig. 1. System 400B also includes respective terminal device interfaces 420A and 420B associated with terminal devices (also not shown), such as terminal device 145 shown in fig. 1. The system 400B also includes respective cables 430A and 430B for connecting the end device interfaces 420A and 420B to the programmable I/O ports 405A and 405B. Cables 430A and 430B include respective I/O port connectors 410A and 410B at one end for connecting to programmable I/O ports 405A and 405B, and respective end device interface connectors 425A and 425B at the other end for connecting to end device interfaces 420A and 420B.

Like the system 400A shown in fig. 4A, the system 400B also includes a port manager 440 connected to the end device interface by an I2C cable. The port manager 440 detects signals from the end device interfaces 420A and 420B and determines the type of end device based on the detected signals. Port manager 440 is used to direct programmable I/O ports 405A and 405B to present signals corresponding to the protocol associated with the determined type of end device to allow the host device to communicate with the end device via cable 430A and end device interfaces 420A and 420B.

The programmable I/O ports 405A and 405B include programmable terminals to present signals to the respective cables 430A and 430B via the respective I/O port connectors 410A and 410B. The programmable terminals are programmed by programmable logic device 450 included in system 400B. The port manager 440 is operable to instruct the programmable logic device 450 to program the programmable terminals of the programmable I/O ports 405A and 405B to present signals corresponding to the protocol associated with the determined type of end device with which the end device interfaces 420A and 420B are associated to the respective I/O port connectors 410A and 410B.

In the example system 400B shown in fig. 4B, end device interfaces 420A and 420B are OCP slots, and end device interface connectors 425A and 425B are OCP I/O connectors. Since this is not the default case, the port manager 440 instructs the programmable logic device 450 to send the signals "PAL _ OCP _ CBL _ DETO" and "EN _ CLK _100M _ OCP _ NIC _ EN _ N" to the programmable I/O ports 405A and 405B to program the programmable I/O ports 405A and 405B to present these signals. Thus, programmable I/O ports 405A and 405B present signals "PAL _ OCP _ CBL _ DETO" and "EN _ CLK _100M _ OCP _ NIC _ EN _ N" on the a side of terminal 54 and the B side of terminal 2, respectively.

Figure 5 conceptually illustrates a system 500 for managing communication between a host device (not shown) and an end device (also not shown) via NVMe BPs, according to one or more examples. The system 500 shown in FIG. 5 includes a programmable I/O port 505 associated with a host device, such as the host device 110 shown in FIG. 1. System 500 also includes respective terminal device interfaces 520A and 520B, both of which terminal device interfaces 520A and 520B are associated with a terminal device, such as terminal device 155 shown in fig. 1. The system 500 also includes respective cables 530A and 530B for connecting the end device interfaces 520A and 520B to the programmable I/O port 505. Cables 530A and 530B connect at one end to I/O port connector 510 and thus to programmable I/O port 505. Cables 530A and 530B include respective end device interface connectors 525A and 525B at the other end for connection to end device interfaces 520A and 520B. In the example system shown in fig. 5, cables 530A and 530B may be x8 cables.

The system 500 also includes a port manager 540 connected to the end device interfaces 520A and 520B via I2C cables. The port manager 540 is configured to detect signals from the end device interfaces 520A and 520B and determine the type of end device based on the detected signals. Based on the determined type of end device, port manager 540 is operable to direct programmable I/O port 505 to present signals corresponding to a protocol associated with the determined type of end device to allow the host device to communicate with the end device via cables 530A and 530B and end device interfaces 520A and 520B.

The programmable I/O port 505 includes programmable terminals to present signals to the respective cables 530A and 530B via the I/O port connector 510. The programmable terminals are programmed by programmable logic devices 550 included in system 500. The port manager 540 is operable to instruct the programmable logic device 550 to program the programmable terminals of the programmable I/O port 505 to present signals to the I/O port connector 510 corresponding to the protocol associated with the determined type of end device with which the end device interfaces 520A and 520B are associated.

In the example system 500 shown in fig. 5, terminal device interfaces 520A and 520B are NVME backplanes and terminal device interface connectors 525A and 525B are NVME connectors. Since this is not the default case, the port manager 540 instructs the programmable logic device 550 to send the signals "CBL _ DET _ SENSE/SS _ CLK", "SS _ DATA _ OUT", "CBL _ DET _ PULSE/SS _ DATA _ IN", and "SS _ LD" to the programmable I/O port 505 to program the programmable I/O port 505 to present these signals. Thus, the programmable I/O port 505 presents the signals "CBL _ DET _ SENSE/SS _ CLK", "SS _ DATA _ OUT", "CBL _ DET _ PULSE/SS _ DATA _ IN", and "SS _ LD" on the a side of terminal 3, the a side of terminal 2, the a side of terminal 54, and the a side of terminal 55, respectively.

Fig. 6A-6C conceptually illustrate a system for managing communication between a host device and one or more respective end devices via one or more cables that serve as inter-processor links, according to one or more examples.

Referring first to FIG. 6A, a system 600A includes a programmable I/O port 615A associated with a host device (e.g., a Central Processing Unit (CPU) 605A). The system 600A also includes a terminal device interface, which in this example is another programmable I/O port 615B. The terminal device interface is associated with a terminal device (e.g., CPU 605B). The system 600A also includes a cable 630 for connecting a terminal device interface (e.g., programmable I/O port 615B) to the programmable I/O port 615A. The cable 630 is connected at one end to the programmable I/O port 615A via the I/O port connector 610A. The cable 630 is connected at another end to a terminal device interface (e.g., programmable I/O port 615B) via another I/O port connector 610B.

System 600A also includes a port manager 650 connected to programmable I/O port 615B and programmable I/O port 615A by I2C cables. Similar to the above-described port managers 340, 440, and 540 shown in fig. 3, 4A-4B, and 5, respectively, and described above, port manager 650 determines the type of end device. That is, the port manager 650 detects that the terminal device is the CPU 605B, for example, by detecting a signal from the terminal device interface (in this example, the terminal device interface is the programmable I/O port 615B).

Based on determining that the terminal device is CPU 605B, port manager 650 directs programmable I/O port 615A to present signals corresponding to the CPU native protocol. The programmable I/O port 615A may use some terminal (not otherwise shown) to present signals in the CPU local protocol. The signals present on these terminals will be the same for communication with corresponding terminal devices of any type. Instead of using those terminals for presenting signals to other types of terminal equipment, these terminals may be programmed depending on the type of terminal equipment. Thus, in this example, there is no programming of the terminals of the programmable I/O port 615A by the programmable logic control device.

In the example system 600A shown in fig. 6A, host devices and terminal devices (e.g., CPUs 605A and 605B), programmable I/O ports 615A, and terminal device interfaces (e.g., programmable I/O ports 615B) are supported on the same printed circuit board 620. According to another example system 600B shown in fig. 6B, a host device (e.g., CPU 605A) and programmable I/O port 615A are supported by one printed circuit board 620A. The terminal device (e.g., CPU 605B) and terminal device interface (e.g., programmable I/O port 615B) are supported by another printed circuit board 620B.

Referring to FIG. 6B, system 600B also includes a cable 630 for connecting a terminal device interface (e.g., programmable I/O port 615B) to programmable I/O port 615A. The cable 630 is connected at one end to the programmable I/O port 615A via the I/O port connector 610A. The cable 630 is connected at another end to a terminal device interface (e.g., programmable I/O port 615B) via another I/O port connector 610B.

System 600B also includes a port manager 650 connected to programmable I/O port 615B and programmable I/O port 615A by I2C cables. The port manager 650 is used to detect that the terminal device is CPU 605B, for example, by detecting a signal from the programmable I/O port 615B. Based on determining that the terminal device is a CPU, the port manager 650 directs the programmable I/O port 615A to present a signal corresponding to a protocol native to the CPU. As in the example described above with reference to fig. 6A, there is no programming of terminals of the programmable I/O port 615A by the programmable logic control device in this example.

Fig. 6C shows a system 600C similar to systems 600A and 600B. As shown in fig. 6C, system 600C includes a programmable I/O port 615A associated with a host device (e.g., CPU 605A). The system 600C also includes corresponding terminal device interfaces (in this example, programmable I/O ports 615B, 615C, and 615D). Terminal device interfaces (e.g., programmable I/O ports 615B, 615C, and 615D) are associated with respective terminal devices (e.g., CPUs 605B, 605C, and 605D), respectively.

In the example system 600C, the host device and a corresponding terminal device (e.g., CPUs 605A and 605B), the programmable I/O port 615A, and a corresponding terminal device interface (e.g., programmable I/O port 615B) are supported on the same printed circuit board 620A. Other respective terminal devices (e.g., CPUs 605C and 605D) and other respective terminal device interfaces (e.g., programmable I/O ports 615C and 615D) are supported on another printed circuit board 620B.

The system 600C also includes a cable 630A for connecting a terminal device interface (e.g., programmable I/O port 615B) to the programmable I/O port 615A. The cable 630 is connected at one end to the programmable I/O port 615A via the I/O port connector 610A. Cable 630A connects at another end to a terminal equipment interface (e.g., programmable I/O port 615B) via another I/O port connector 610B.

The system 600C also includes another cable 630B for connecting end device interfaces (e.g., programmable I/O ports 615C and 615D). Cable 630B connects at one end to a terminal equipment interface (e.g., programmable I/O port 615C) via I/O port connector 610C. Cable 630B connects at another end to a terminal device interface (e.g., programmable I/O port 615D) via another I/O port connector 610D. As shown in fig. 6C, cables 630A and 630B are also connected to each other to provide communication between a host device (e.g., CPU 605A) and an end device (e.g., CPUs 605B, 605C, and 605D) via programmable I/O port 615A.

The system 600C also includes a port manager 650 connected to the end device interfaces (e.g., programmable I/O ports 615B, 615C, and 615D) and the programmable I/O port 615A via I2C cables. Port manager 650 is used to detect signals from end device interfaces (e.g., programmable I/O ports 615B, 615C, and 615D) and determine that the end devices are CPUs 605B, 605C, and 605D. Based on determining that the terminal device is a CPU, the port manager 650 directs the programmable I/O port 615A to present a signal corresponding to a protocol native to the CPU. As in the example described above with reference to fig. 6A and 6B, in this example, there is no programming of the terminals of the programmable I/O port 615A by the programmable logic control device.

Fig. 7 is a flow diagram depicting a method 700 for managing communications between host devices according to one or more examples of the disclosure. Method 700 may be performed by, for example, port managers 340, 440, 540, and 650 shown in fig. 3, 4A, 4B, 5, and 6A-6C.

Method 700 includes, at 710, detecting a signal from a terminal device interface associated with a terminal device. The end device is connected to the host device via a cable and programmable I/O associated with the host device. The host device is connectable to a plurality of different types of terminal devices, and the plurality of different types of terminal devices are respectively associated with different types of protocols.

Based on the detected signal, the type of terminal device is determined at 720. At 730, based on the determined type of the end device, the programmable I/O port is directed to present a signal corresponding to a protocol associated with the end device. This may include instructing the programmable logic device to program the programmable I/O port to present a signal.

Fig. 8 is a block diagram of a computing device 800 with which port managers 340, 440, 540, and 650 shown in fig. 3, 4A-4B, 5, and 6A-6C, respectively, may be implemented according to an illustrative example.

Referring to fig. 8, computing device 800 includes a processor 810, processor 810 communicatively coupled to an input/output (I/O) interface 820 via an address/data bus 825. The processor 810 receives input and transmits output via the I/O interface 820. Processor 810 may be any commercially available or custom microprocessor or microcontroller. The processor 810 may be, for example, a controller, microprocessor, digital signal processor, graphics processor, or even a processor chipset. This list is neither exclusive nor exhaustive. I/O interface 820 may include any suitable connection interface, such as an I2C cable interface.

The processor 810 communicates with the memory 830 via, for example, an address/data bus 815. The memory 830 represents a memory device containing the software and data used to implement the functionality of the computing device 800. The memory 830 may include, but is not limited to, a non-transitory computer-readable storage medium 835, such as an electrically erasable programmable read-only memory (EEPROM) implemented as firmware. Other alternatives may also be used. The memory may be volatile or non-volatile, random access or read-only or even a cache. As shown in fig. 8, memory 830 may include a number of categories of software and data (including computer-executable instructions 840) for use in computing device 800.

Computer-executable instructions 840 may be stored in memory 830 and executed by processor 810. Computer-executable instructions 840 include various programs that implement various features of computing device 800. For example, computer-executable instructions 840 may include instructions for implementing the functionality of a port manager (including detecting signals from an end device interface associated with an end device connected to a host device via a cable and a programmable I/O port associated with the host device, determining a type of the end device based on the detected signals, directing the programmable I/O port to present signals corresponding to a protocol associated with the determined type of the end device based on the determined type of the end device, allowing the host device to communicate with the end device, etc.).

The memory 830 may also store static and dynamic data used by the instructions 840. In addition, other software programs may reside in memory 830. The data that may be stored in the memory may include, for example, a motherboard specification for determining what type of connected terminal device is based on signals detected from the terminal device interface, instructions sent to the programmable logic device for different types of devices, and so forth.

It should be understood that fig. 8 and the above description are intended to provide a brief, general description of a suitable environment in which various aspects of some examples of the disclosure may be implemented. While the general context of including executable instructions stored in firmware is described, the disclosure may be implemented in combination with other program modules and/or as a combination of hardware and software, in addition to or in place of processor-executable instructions.

The foregoing description, for purposes of explanation, used specific nomenclature to provide a thorough understanding of the disclosure. However, it will be apparent to one skilled in the art that the specific details are not required in order to practice the systems and methods described herein. The foregoing descriptions of specific examples have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the disclosure to the precise forms described. Many modifications and variations are possible in light of the above teaching. The examples are shown and described in order to best explain the principles of the disclosure and the practical application, to thereby enable others skilled in the art to best utilize the disclosure and various examples with various modifications as are suited to the particular use contemplated. It is intended that the scope of the disclosure be defined by the following claims and their equivalents.