1. A power composite bus circuit comprising a controller, a transmitter, and a receiver; the controller is connected with a transmitter, and the transmitter is connected with a receiver.

2. The power composite bus circuit according to claim 1, wherein the controller includes a data transmission controller and a communication cache controller; the data transmission controller is connected with a communication cache controller, and the communication cache controller is connected with a transmitter.

3. The power composite bus circuit according to claim 1, wherein the communication transmitter is connected to the communication receiver through an S bus and a GND ground.

4. A method for caching a power composite bus, the method applying the power composite bus circuit according to any one of claims 1 to 3, the method comprising the steps of:

step S1: a communication cache controller is added on the original circuit;

step S2: the communication baud rate of the data transmission controller is improved;

step S3: the data transmission controller transmits the data packet to the communication cache controller;

step S4: the communication cache controller sends data to the communication transmitter, and the communication transmitter sends the data to the power composite bus;

step S5: the communication receiver receives the data and sends the data to a communication cache controller at a receiving end;

step S6: and after receiving a complete data packet, the communication cache controller sends the data to the data receiving controller to complete communication.

5. The method for buffering the power composite bus according to claim 4, wherein the data transmission controller in step S3 transmits the data packets to the communication buffer controller at a baud rate of 8 Mbit.

6. The method for buffering the power composite bus as claimed in claim 4, wherein the communication buffer controller in step S4 sends data to the communication transmitter at the original 9600Bit baud rate.

7. The method for buffering the power composite bus according to claim 4, wherein the communication receiver in step S5 receives data at the original 9600Bit baud rate.

8. The method for buffering the power composite bus according to claim 4, wherein the data is transmitted to the data receiving controller at a baud rate of 8MBit in step S6.

9. The method of caching for a power composite bus of claim 4, wherein said method further comprises a double-baud-rate method, said double-baud-rate method comprising: a high baud rate is used between the data transmission controller and the communication cache controller; the original baud rate is used for communication between the cache controller and the communication transmission generator.

10. The method of claim 4, wherein the double baud rate method further comprises using a high baud rate between the data receiving controller and the communicating cache controller; the original baud rate is used for communication between the cache controller and the communication receiving controller.

Background

The existing power composite bus usually adopts a common mode of a power supply cable and a communication cable. The power and communication share one cable, so that the problems of low communication baud rate (only 9600bps), more error codes and the like can occur, and the reliability of the machine time and the communication of the main controller is seriously occupied.

In patent document CN203423005U, a composite power cable with a single bus transmission function is disclosed, wherein the cable comprises a power cable and at least one single bus cable, and the power cable and the single bus cable are respectively wrapped by an insulating sheath. The composite power cable further includes a protective sheath that encases the insulating sheaths of the power cable and the single bus cable in a single cable.

In view of the above technical problems, a technical solution is needed to improve the above technical problems.

Disclosure of Invention

In view of the defects in the prior art, the present invention provides a cache circuit and a cache method for a power composite bus.

The invention provides a power composite bus circuit, which comprises a controller, a transmitter and a receiver; the controller is connected with a transmitter, and the transmitter is connected with a receiver.

Preferably, the controller comprises a data transmission controller and a communication cache controller; the data transmission controller is connected with a communication cache controller, and the communication cache controller is connected with a transmitter.

Preferably, the communication transmitter is connected to the communication receiver via an S bus and a GND ground.

The invention also provides a cache method of the electric power composite bus, which is applied to the electric power composite bus circuit, and comprises the following steps:

step S1: a communication cache controller is added on the original circuit;

step S2: the communication baud rate of the data transmission controller is improved;

step S3: the data transmission controller transmits the data packet to the communication cache controller;

step S4: the communication cache controller sends data to the communication transmitter, and the communication transmitter sends the data to the power composite bus;

step S5: the communication receiver receives the data and sends the data to a communication cache controller at a receiving end;

step S6: and after receiving a complete data packet, the communication cache controller sends the data to the data receiving controller to complete communication.

Preferably, the data transmission controller in step S3 transmits the data packets to the communication buffer controller at a baud rate of 8 Mbit.

Preferably, the communication buffer controller in step S4 sends the data to the communication transmitter at the baud rate of the original 9600 Bit.

Preferably, the communication receiver in step S5 receives data at the baud rate of the original 9600 Bit.

Preferably, in step S6, the data is transmitted to the data receiving controller at a baud rate of 8 MBit.

Preferably, the method further comprises a double baud rate method, the double baud rate method comprising: a high baud rate is used between the data transmission controller and the communication cache controller; the original baud rate is used for communication between the cache controller and the communication transmission generator.

Preferably, the double baud rate method further comprises using a high baud rate between the data reception controller and the communication buffer controller; the original baud rate is used for communication between the cache controller and the communication receiving controller.

Compared with the prior art, the invention has the following beneficial effects:

1. because the invention uses higher communication baud rate when connecting with the data sending controller and the data receiving controller, the invention can reduce the communication time when reducing the communication machines of the data sending controller and the data receiving controller, and is beneficial to improving the running speed of the sending controller and the data receiving controller;

2. when the invention is connected with the data sending controller and the data receiving controller, the data sending controller and the data receiving controller occupy less machine time, can be connected with more contacts and can execute more complex control logic;

3. the invention has the function of buffering the line voltage because the original line is added with a series connection link. Under the condition of equipment failure, the data transmission controller and the data receiving controller can be prevented from being burnt down due to abnormal high voltage on the S bus;

4. the newly added communication cache controller has simple circuit diagram, can be combined with a data sending controller and a data receiving controller when drawing a printed circuit board, occupies little circuit board area and has low cost.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:

FIG. 1 is a diagram of a point-to-point network topology of a prior art system;

FIG. 2 is a diagram of a point-to-point network topology of the present invention;

FIG. 3 is a baud rate profile of a communication system;

FIG. 4 is a circuit diagram of a communication cache controller;

FIG. 5 is a schematic block diagram of the increased communication buffer;

FIG. 6 is a circuit diagram after adding a communication buffer;

FIG. 7 is a flow chart of a data transmission process by the data transmission controller;

fig. 8 is a flow chart of a data reception controller transmission process.

Detailed Description

The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.

The invention provides a power composite bus circuit, which comprises a controller, a transmitter and a receiver, wherein the transmitter is connected with the receiver; the controller is connected with the transmitter, and the transmitter is connected with the receiver. The controller comprises a data transmission controller and a communication cache controller; the data transmission controller is connected with the communication cache controller, and the communication cache controller is connected with the transmitter. The communication transmitter is connected with the communication receiver through the S bus and the GND grounding wire.

The invention aims to provide a caching method of a power composite bus, wherein data needing to be transmitted is transmitted to a cache of a communication cache controller by a data transmitting controller in a rapid mode, then the communication cache controller carries out communication and verification according to the baud rate of the bus and transmits the data to an opposite communication cache controller, and after a group of data is completely received, the opposite communication cache controller rapidly communicates with a data receiving controller. Thus, the data transmission controller and the data reception controller have a small size in communication with the occupied machine during the communication.

The invention provides a cache method of a power composite bus, which comprises a double-baud rate method, wherein the double-baud rate method comprises the following steps: a high baud rate is used between the data transmission controller and the communication cache controller; the original baud rate is used for communication between the cache controller and the communication sending generator; a high baud rate is used between the data receiving controller and the communication cache controller; the original baud rate is used for communication between the cache controller and the communication receiving controller.

Referring to fig. 1 and 2, the method of the present invention includes the steps of:

step S1: a communication cache controller is added on the original circuit; step S2: increasing the communication baud rate of the data transmission controller, for example, from the original 9600Bit to 8 Mbit; step S3: the data transmission controller transmits the data packet to the communication cache controller at a baud rate of 8 Mbit; step S4: the communication cache controller sends data to a communication transmitter at the original 9600Bit baud rate, and the communication transmitter sends the data to the power composite bus; step S5: the communication receiver receives data at the baud rate of the original 9600Bit and sends the data to a communication cache controller at a receiving end; step S6: after receiving a complete data packet, the communication buffer controller sends the data to the data receiving controller at the baud rate of 8MBit to complete the communication.

Referring to fig. 3 and 4, according to the design, the circuit can be realized in many ways, and the 8051 single chip microcomputer of the STC company is used, so that the circuit is simple, economic, cheap and low in cost.

The explanation is given by taking the sending end as an example: the data transmission controller is connected with the communication buffer controller through the current limiting resistors R1 and R2, and communicates with a high baud rate (for example, 8MBit) to transmit data to be transmitted in a whole packet to the single chip microcomputer U2. The single chip microcomputer is connected with the communication sending controller through the current limiting resistors R3 and R4, the baud rate (9600Bit) which can be accepted by the S bus is used for communication, data to be sent are sent to the original communication sender one byte by one byte, and data sending is achieved. The procedure at the receiving end is the same as that at the transmitting end, and the sequence is reversed, and will not be described in detail.

Referring to fig. 5, in a certain project, an original system does not adopt a buffering mechanism, when one integrated gateway can be connected with loads of 10S buses, the data occupancy rate on the buses is already high and reaches 80%, and when the data occupancy rate is increased to 11S bus loads, the bus fullness and communication abnormal states often occur.

After the cache communication cache controller is added, through testing, one integrated gateway can be connected with loads of 120S buses, and smooth communication can be achieved.

Referring to fig. 6, the system composition and working principle: the system consists of an integrated gateway (data transmission controller), a communication cache controller and a communication transmitter, and comprises an STM32F427 singlechip, an STC8F2K16S2 singlechip and an S bus transmission module.

After the mechanical structure is installed and debugged, debugging the circuit and the software, and performing the following steps:

step 1: the perfusion software is used for perfusing data to the STM32F427 single chip microcomputer and sending controller software; step 2: software filling, namely filling communication cache controller software to an STC8F2K16S2 single chip microcomputer; and step 3: 120 loads are hung on the S bus, and the smoothness and accuracy of data sending and receiving are tested.

When the original circuit board is additionally installed, a communication cache controller needs to be specially accessed, so that the mechanical structure of the interface is complex.

The communication buffer controller is integrated on an integrated gateway or a sending controller circuit board. According to the complexity of the circuit diagram, the circuit board is easy to integrate into the sending controller. And (4) redrawing the printed circuit board for the circuit of the sending controller, keeping the original mechanical and electrical interfaces, and directly replacing the original circuit board of the sending controller.

Because the invention uses higher communication baud rate when connecting with the data sending controller and the data receiving controller, the invention can reduce the communication time when reducing the communication machines of the data sending controller and the data receiving controller, and is beneficial to improving the running speed of the sending controller and the data receiving controller; when the controller is connected with the data sending controller and the data receiving controller, the data sending controller and the data receiving controller occupy less machine time, can be connected with more contacts and can execute more complex control logic; because the original circuit is added with a series connection link, the circuit voltage buffer function is realized. Under the condition of equipment failure, the data transmission controller and the data receiving controller can be prevented from being burnt down due to abnormal high voltage on the S bus; the newly added communication cache controller has a simple circuit diagram, can be combined with a data sending controller and a data receiving controller when drawing a printed circuit board, occupies little circuit board area and has low cost.

Those skilled in the art will appreciate that, in addition to implementing the system and its various devices, modules, units provided by the present invention as pure computer readable program code, the system and its various devices, modules, units provided by the present invention can be fully implemented by logically programming method steps in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Therefore, the system and various devices, modules and units thereof provided by the invention can be regarded as a hardware component, and the devices, modules and units included in the system for realizing various functions can also be regarded as structures in the hardware component; means, modules, units for performing the various functions may also be regarded as structures within both software modules and hardware components for performing the method.

The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.