EUV photomask and method of manufacturing the same
1. A reflective mask, comprising:
a substrate;
a reflective multilayer disposed on the substrate;
a capping layer disposed on the reflective multilayer; and
an absorber layer disposed on the cap layer,
wherein the absorber layer comprises a CrN layer, a CrON layer having a nitrogen concentration of 10 atomic% to 30 atomic%, or a CrCON layer having a nitrogen concentration of 10 atomic% to 30 atomic%.
2. The reflective mask of claim 1, wherein the absorber layer has a thickness in a range from 20nm to 50 nm.
3. The reflective mask of claim 1, wherein the absorber layer comprises a CrN layer having a nitrogen concentration of 16 atomic% to 40 atomic%.
4. The reflective mask of claim 3, wherein the CrN layer comprises a Cr phase and Cr2And (4) N phase.
5. The reflective mask of claim 3, wherein the CrN layer is made of Cr2And (4) N-phase composition.
6. The reflective mask of claim 3, wherein the CrN layer comprises Cr2N phase and CrN phase.
7. The reflective mask of claim 1, further comprising: an intermediate layer disposed on the cap layer.
8. The reflective mask of claim 7, wherein the intermediate layer comprises at least one of: TaB, TaO, TaBO or TaBN, silicon-based compounds, ruthenium or ruthenium-based compounds.
9. A method of fabricating a reflective mask, the method comprising:
forming a photoresist layer over a mask blank, the mask blank comprising a substrate, a reflective multilayer on the substrate, a cap layer on the reflective multilayer, an intermediate layer on the cap layer, an absorber layer on the intermediate layer, a first hard mask layer on the absorber layer, and a second hard mask layer on the first hard mask layer;
patterning the photoresist layer;
patterning the second hard mask layer by using the patterned photoresist layer;
patterning the first hard mask layer by using the patterned second hard mask layer;
patterning the absorber layer by using a patterned first hard mask layer and a patterned second hard mask layer; and
removing the first hard mask layer and the second hard mask layer,
wherein the second hard mask layer and the absorber layer comprise a Cr-based compound, and the first hard mask layer and the intermediate layer comprise a Ta-based compound.
10. A method of fabricating a reflective mask, the method comprising:
forming a photoresist layer over a mask blank, the mask blank comprising a substrate, a reflective multilayer on the substrate, a cap layer on the reflective multilayer, an intermediate layer on the cap layer, an absorber layer on the intermediate layer, an oxide layer on the absorber layer, a first hard mask layer on the oxide layer, and a second hard mask layer on the first hard mask layer;
patterning the photoresist layer;
patterning the second hard mask layer by using the patterned photoresist layer;
patterning the first hard mask layer by using the patterned second hard mask layer;
patterning the oxide layer and the absorber layer by using a patterned first hard mask layer and a patterned second hard mask layer; and
patterning the intermediate layer.
Background
The photolithography operation is one of the key operations in the semiconductor manufacturing process. Photolithography techniques include ultraviolet lithography, deep ultraviolet lithography, and extreme ultraviolet lithography (EUVL). Photomasks are important components in lithographic operations. It is important to manufacture an EUV photomask having a high contrast ratio including a high-reflectance portion and a high-absorbance portion.
Disclosure of Invention
According to an aspect of the present disclosure, there is provided a reflective mask including: a substrate; a reflective multilayer disposed on the substrate; a capping layer disposed on the reflective multilayer; and an absorber layer disposed on the cap layer, wherein the absorber layer includes a CrN layer, a CrON layer having a nitrogen concentration of 10 atomic% to 30 atomic%, or a CrCON layer having a nitrogen concentration of 10 atomic% to 30 atomic%.
According to another aspect of the present disclosure, there is provided a method of manufacturing a reflective mask, the method including: forming a photoresist layer over a mask blank, the mask blank comprising a substrate, a reflective multilayer on the substrate, a cap layer on the reflective multilayer, an intermediate layer on the cap layer, an absorber layer on the intermediate layer, a first hard mask layer on the absorber layer, and a second hard mask layer on the first hard mask layer; patterning the photoresist layer; patterning the second hard mask layer by using the patterned photoresist layer; patterning the first hard mask layer by using the patterned second hard mask layer; patterning the absorber layer by using a patterned first hard mask layer and a patterned second hard mask layer; and removing the first hard mask layer, wherein the second hard mask layer and the absorber layer include a Cr-based compound, and the first hard mask layer and the intermediate layer include a Ta-based compound.
According to yet another aspect of the present disclosure, there is provided a method of manufacturing a reflective mask, the method including: forming a photoresist layer over a mask blank, the mask blank comprising a substrate, a reflective multilayer on the substrate, a cap layer on the reflective multilayer, an intermediate layer on the cap layer, an absorber layer on the intermediate layer, an oxide layer on the absorber layer, a first hard mask layer on the oxide layer, and a second hard mask layer on the first hard mask layer; patterning the photoresist layer; patterning the second hard mask layer by using the patterned photoresist layer; patterning the first hard mask layer by using the patterned second hard mask layer; patterning the oxide layer and the absorber layer by using a patterned first hard mask layer and a patterned second hard mask layer; and patterning the intermediate layer.
Drawings
The disclosure can be best understood from the following detailed description when read in connection with the accompanying drawings. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
FIGS. 1A, 1B, 1C, 1D and 1E illustrate an EUV photomask blank (blank) according to an embodiment of the present disclosure.
Fig. 2A, 2B, 2C, 2D, 2E and 2F schematically illustrate a method of manufacturing an EUV photomask according to an embodiment of the present disclosure.
Fig. 3A, 3B, 3C, 3D, and 3E schematically illustrate a method of manufacturing an EUV photomask according to an embodiment of the present disclosure.
Figure 4 illustrates a cross-sectional view of an EUV photomask according to an embodiment of the present disclosure.
Fig. 5A, 5B, and 5C illustrate cross-sectional views of a multilayer structure of an absorber layer according to another embodiment of the present disclosure.
Figure 6 illustrates a cross-sectional view of an EUV photomask according to an embodiment of the present disclosure.
FIG. 7 shows a flow chart for manufacturing a mask blank for an EUV photomask according to an embodiment of the present disclosure.
Fig. 8A shows a flowchart of a method of manufacturing a semiconductor device, and fig. 8B, 8C, 8D, and 8E show sequential manufacturing operations of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.
Detailed Description
It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the dimensions of the elements are not limited to the disclosed ranges or values, but may depend on the process conditions and/or desired characteristics of the device. Furthermore, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn in different scales for simplicity and clarity.
Furthermore, spatially relative terms, such as "below," "beneath," "below," "above," "upper," and the like, may be used herein to readily describe one element or structure's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Furthermore, the term "consisting of may mean" including "or" consisting of. In this disclosure, the phrase "one of A, B and C" refers to "A, B and/or C" (A, B, C, A and B, A and C, B and C, or A, B and C), and does not refer to one element from a, one element from B, and one element from C unless otherwise specified.
Embodiments of the present disclosure provide a method of fabricating an EUV photomask. More specifically, the present disclosure provides techniques to prevent or inhibit damage to a backside conductive layer of an EUV photomask.
EUV lithography (EUVL) uses a scanner that uses light in the Extreme Ultraviolet (EUV) region with wavelengths of about 1nm to about 100nm (e.g., 13.5 nm). Masks are key components of EUVL systems. Since the optical material is opaque to EUV radiation, an EUV photomask is a reflective mask. The circuit pattern is formed in an absorber layer disposed over the reflective structure. The absorber has a low EUV reflectivity, for example less than 3-5%.
The present disclosure provides EUV reflective photomasks having low reflective (high absorbing) absorber structures.
Fig. 1A and 1B illustrate an EUV reflective photomask blank according to an embodiment of the present disclosure. Fig. 1A is a plan view (viewed from the top), and fig. 1B is a cross-sectional view along the X direction.
In some embodiments, an EUV photomask having a circuit pattern is formed from the EUV photomask blank 5. The EUV photomask blank 5 comprises a substrate 10, a multilayer Mo/Si stack 15 of a plurality of alternating layers of silicon and molybdenum, a capping layer 20, a protective layer 22, an absorber layer 25, a first hard mask layer 30 and a second hard mask layer 32. As shown in fig. 1B, a rear surface conductive layer 45 is formed on the rear surface of the substrate 10. In some embodiments, as shown in figure 1B, an oxide layer 27 is formed on the top surface of the absorber layer 25. In other embodiments, as shown in FIG. 1D, no oxide layer is formed on the top surface of the absorber layer 25.
In some embodiments, substrate 10 is formed of a low thermal expansion material. In some embodiments, the substrate is a low thermal expansion glass or quartz, such as fused silica glass or fused quartz. In some embodiments, the low thermal expansion glass substrate transmits light at visible wavelengths, a portion of infrared wavelengths (near infrared) near the visible spectrum, and a portion of ultraviolet wavelengths. In some embodiments, the low thermal expansion glass substrate absorbs extreme ultraviolet wavelengths and deep ultraviolet wavelengths near the extreme ultraviolet wavelengths. In some embodiments, the substrate 10 is 152mm by 152mm in size and approximately 20mm thick. In other embodiments, the substrate 10 has dimensions less than 152mm by 152mm, and equal to or greater than 148mm by 148 mm. The substrate 10 is square or rectangular in shape.
In some embodiments, the width of the functional layers (multilayer Mo/Si stack 15, capping layer 20, protective layer 22, absorber layer 25, first hard mask layer 30, and second hard mask layer 32) above the substrate is less than the width of substrate 10. In some embodiments, the functional layer ranges in size from about 138mm by 138mm to 142mm by 142 mm. In some embodiments, the functional layer is square or rectangular in shape in plan view.
In other embodiments, the protective layer 22, absorber layer 25, first hard mask layer 30, and second hard mask layer 32 have smaller dimensions than the substrate 10, multilayer Mo/Si stack 15, and cap layer 20, in a range from about 138mm to 142mm, as shown in FIG. 1C. In forming each functional layer by, for example, sputtering, the smaller size of one or more functional layers may be formed by using a box-shaped cover having an opening in the range from about 138mm × 138mm to 142mm × 142 mm. In other embodiments, all layers above the substrate 10 have the same dimensions as the substrate 10.
In some embodiments, the Mo/Si multilayer stack 15 includes from about 30 alternating layers of silicon and molybdenum to about 60 alternating layers of silicon and molybdenum. In certain embodiments, about 40 to about 50 alternating layers of silicon and molybdenum are formed. In some embodiments, the reflectance is greater than about 70% for the wavelength of interest, e.g., 13.5 nm. In some embodiments, the silicon layer and the molybdenum layer are formed by Chemical Vapor Deposition (CVD), plasma enhanced CVD (pecvd), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD) (sputtering), or any other suitable method of forming a film. Each layer of silicon and molybdenum is about 2nm to about 10nm thick. In some embodiments, the silicon layer and the molybdenum layer have about the same thickness. In other embodiments, the silicon layer and the molybdenum layer have different thicknesses. In some embodiments, the thickness of each silicon layer is about 4nm and the thickness of each molybdenum layer is about 3 nm.
In other embodiments, the multilayer stack 15 includes alternating layers of molybdenum and beryllium. In some embodiments, the number of layers in the multilayer stack 15 is in the range from about 20 to about 100, but any number of layers may be allowed as long as sufficient reflectivity is maintained for imaging the target substrate. In some embodiments, the reflectance is greater than about 70% for the wavelength of interest, e.g., 13.5 nm. In some embodiments, the multilayer stack 15 includes about 30 to about 60 alternating layers of Mo and Be. In other embodiments of the present disclosure, the multilayer stack 15 includes from about 40 to about 50 alternating layers of Mo and Be.
In some embodiments, a capping layer 20 is disposed over the Mo/Si multilayer stack 15 to prevent oxidation of the multilayer stack 15. In some embodiments, the cap layer 20 is made of ruthenium, ruthenium alloys (e.g., RuNb, RuZr, RuZrN, RuRh, RuNbN, RuRhN, RuV, or RuVN), or ruthenium-based oxides (e.g., RuO)2RuNbO, RiVO, or RuON) with a thickness in a range of about 2nm to about 10 nm. In some embodiments, the thickness of capping layer 20 is in the range from about 2nm to about 5 nm. In some embodiments, capping layer 20 is 3.5nm 10% thick. In some embodiments, cap layer 20 is formed by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition (e.g., sputtering), or any other suitable method of forming a film. In other embodiments, a Si layer is used as the cap layer 20.
In some embodiments, a protective (intermediate) layer 22 is formed between capping layer 20 and absorber layer 25. In some embodiments, a protective layer 22 is used to protect cap layer 20. In some embodiments, the protective layer 22 includes: ta-based materials, such as TaB, TaO, TaBO or TaBN; silicon; silicon-based compounds (e.g., silicon oxide, SiN, SiON, or MoSi); ruthenium; or ruthenium-based compounds (Ru or RuB). In some embodiments, the protective layer 22 has a thickness of about 2nm to about 20 nm. In some embodiments, the protective layer 22 is formed by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable film forming method. In some embodiments, the protective layer 22 serves as an etch stop layer during the patterning operation of the absorber layer.
In other embodiments, the intermediate layer 22 is a photocatalytic layer which can catalyze the formation of hydrocarbon residues on a photomask to CO using EUV radiation2And/or H2And O. Thus, in-situ self-cleaning of the mask surface is performed. In some embodiments, in an EUV scanner system, oxygen and hydrogen are injected into an EUV chamber to maintain a chamber pressure (e.g., at about 2 Pa). The chamber background gas may be a source of oxygen. In addition to photocatalytic function, photocatalytic layers are designed to have sufficient durability and resistance to various chemicals and various chemical processes (e.g., cleaning and etching). Ozone water used for manufacturing the EUV reflective mask in a subsequent process may damage the capping layer 20 made of Ru and cause a significant drop in EUV reflectance. In addition, after oxidation of Ru, the Ru oxide is readily oxidized by, for example, C12Or CF4An etchant such as a gas etches away. In some embodiments, the photocatalytic layer comprises one or more of the following: titanium oxide (TiO)2) Tin oxide (SnO), zinc oxide (ZnO) or cadmium sulfide (CdS). In some embodiments, photocatalytic layer 22 has a thickness in a range from about 2nm to about 10nm, and in other embodiments, in a range from about 3nm to about 7 nm. When the thickness is too thin, the photocatalytic layer may not sufficiently function as an etching stopper layer. When the thickness is too large, the photocatalytic layer may absorb EUV radiation.
An absorber layer 25 is disposed over the intermediate (protective) layer 22. In an embodiment of the present disclosure, the absorber layer 25 comprises a Cr-based material, e.g., Cr, CrN, CrON, and/or CrCON. In some embodiments, in the case of CrON or CrCON, the nitrogen content ranges from about 10 atomic% to about 30 atomic%. In some embodiments, the absorber layer 25 has a multilayer structure of Cr, CrN, CrON, and/or CrCON.
In certain embodiments, a CrN layer is used as the absorber layer 25. In some embodiments, when a CrN layer is used, the nitrogen content is in the range of about 16 atomic% to about 40 atomic%. The CrN absorber layer includes a Cr phase and Cr when the nitrogen content is in the range of about 16 atomic% to about 30 atomic%2And (4) N phase. When the nitrogen content is in the range of about 30 atomic% to about 33 atomic%, the CrN absorber layer consists essentially of Cr2N phase composition (e.g., greater than 95 vol%). The CrN absorber layer includes Cr when the nitrogen content is in the range of about 33 atomic% to about 40 atomic%2N phase and CrN phase. The phases may be observed by Electron Energy Loss Spectroscopy (EELS), Transmission Electron Microscopy (TEM), and/or X-ray diffraction (XRD) analysis. In some embodiments, the two phases form a solid solution (solid solution).
In some embodiments, the nitrogen concentration in the absorber layer 25 is not uniform. In some embodiments, the nitrogen concentration is higher in the middle or center of the absorber layer 25 than at the surface region of the absorber layer 25. In some embodiments, the CrN absorber layer includes one or more impurities other than Cr and N in an amount less than about 5 atomic%. In some embodiments, the getter layer 25 further comprises one or more elements of Co, Te, Hf and/or Ni.
In some embodiments, the thickness of the absorber layer 25 is in the range from about 20nm to about 50nm, and in other embodiments, in the range from about 35nm to about 46 nm.
In some embodiments, an anti-reflective layer (not shown) is optionally disposed over the absorber layer 25. In some embodiments, the antireflective layer is formed of silicon oxide and has a thickness of about 2nm to about 10 nm. In other embodiments, a TaBO layer having a thickness in the range from about 12nm to about 18nm is used as the antireflective layer. In some embodiments, the antireflective layer is about 3nm to 6nm thick. In some embodiments, the antireflective layer is formed by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable method of forming a film.
In some embodiments, oxide layer 27 comprises Cr2O3Or CrO2One or more of (a). In some embodiments, oxide layer 27 is formed during the fabrication operation of the mask blank. In some embodiments, the thickness of oxide layer 27 is in a range from about 1nm to about 3 nm. In some embodiments, as shown in fig. 1D, no oxide layer is formed.
In some embodiments, a first hard mask layer 30 is disposed over oxide layer 27. In some embodiments, the first hard mask layer 30 is formed over an antireflective layer. In some embodiments, first hard mask layer 30 is made of a Ta-based material, for example, TaB, TaO, TaBO, or TaBN. In other embodiments, the first hard mask layer 30 is made of silicon, a silicon-based compound (e.g., silicon oxide, SiN, SiON, or MoSi), ruthenium, or a ruthenium-based compound (Ru or RuB). In some embodiments, the first hard mask layer 30 is made of the same or similar material as the protective layer 22. In some embodiments, the thickness of the first hard mask layer 30 is about 2nm to about 20 nm. In some embodiments, the first hard mask layer 30 is formed by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable film forming method.
In some embodiments, a second hard mask layer 32 is disposed over the first hard mask layer 30. In some embodiments, the second hard mask layer 32 is made of one or more of GaN, CrON, CrCON, silicon oxide, SiCO, and/or yttrium oxide. In some embodiments, the thickness of the second hard mask layer 32 is about 2nm to about 20 nm. In some embodiments, the second hard mask layer 32 is less than or greater than the thickness of the first hard mask layer 30. In some embodiments, the second hard mask layer 32 is formed by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable film forming method.
In some embodiments, the second hard mask layer 32 is made of a material having a higher etch rate for a plasma including chlorine and oxygen than the material of the first hard mask layer 30. In some embodiments, the first hard mask layer 30 is made of a material having a higher etch rate for a plasma including fluorine than the material of the second hard mask layer 32.
In some embodiments, one or more of the functional layers above the substrate (multilayer Mo/Si stack 15, capping layer 20, protective layer 22, absorber layer 25, oxide layer 27, first hard mask layer 30, and second hard mask layer 32) have a polycrystalline structure (e.g., a nanocrystalline (nano-crystalline) structure) or an amorphous structure.
In some embodiments, the backside conductive layer45 are provided on a second main surface of the substrate 10, which is opposite to the first main surface of the substrate 10 on which the Mo/Si multilayer stack 15 is formed. In some embodiments, the backside conductive layer 45 is formed of TaB (tantalum boride) or other Ta-based conductive material. In some embodiments, the tantalum boride is crystalline. The crystalline tantalum boride includes TaB and Ta5B6、Ta3B4And TaB2. In other embodiments, the tantalum boride is polycrystalline or amorphous. In other embodiments, the backside conductive layer 45 is formed of a Cr-based conductive material (CrN or CrON). In some embodiments, the sheet resistance of the back conductive layer 45 is equal to or less than 20 Ω/□. In some embodiments, the sheet resistance of the back conductive layer 45 is equal to or greater than 0.1 Ω/□. In some embodiments, the surface roughness Ra of the backside conductive layer 45 is equal to or less than 0.25 nm. In some embodiments, the surface roughness Ra of the backside conductive layer 45 is equal to or greater than 0.05 nm. Furthermore, in some embodiments, the flatness of the backside conductive layer 45 (within the EUV photomask) is equal to or less than 50 nm. In some embodiments, the flatness of the backside conductive layer 45 is greater than 1 nm. In some embodiments, the thickness of the backside conductive layer 45 is in the range from about 50nm to about 400 nm. In other embodiments, the backside conductive layer 45 has a thickness of about 50nm to about 100 nm. In certain embodiments, the thickness is in a range from about 65nm to about 75 nm. In some embodiments, the backside conductive layer 45 is formed by atmospheric Chemical Vapor Deposition (CVD), low pressure CVD, plasma-enhanced CVD, laser-enhanced CVD, Atomic Layer Deposition (ALD), Molecular Beam Epitaxy (MBE), physical vapor deposition (including thermal deposition, pulsed laser deposition, e-beam evaporation, ion-beam assisted evaporation, and sputtering), or any other suitable method of forming a film. In some embodiments, in the case of CVD, the source gas comprises TaCl5And BCl3。
In some embodiments, as shown in fig. 1E, a substrate protection layer 12 is formed between the substrate 10 and the multi-layer stack 15. In some embodiments, the substrate protective layer 12 is formed of Ru or a Ru compound, for example, RuO, RuNb, RuNbO, RuZr, and RuZrO. In some embodiments, substrate protective layer 12 is formed of the same or different material as cap layer 20. In some embodiments, the thickness of the substrate protective layer 12 is in a range from about 2nm to about 10 nm.
Fig. 2A to 2F and 3A to 3E schematically illustrate a method of manufacturing an EUV photomask for extreme ultraviolet lithography (EUVL). It should be understood that additional operations may be provided before, during, and after the processes shown in fig. 2A-3E, and that some of the operations described below may be replaced or eliminated with respect to further embodiments of the method. The order of these operations/processes may be interchangeable.
In the fabrication of an EUV photomask, a first photoresist layer 35 is formed over the second hard mask layer 32 of an EUV photomask blank, as shown in fig. 2A, and then the first photoresist layer 35 is selectively exposed to actinic radiation EB, as shown in fig. 2B. In some embodiments, the EUV photomask blank is inspected prior to forming first photoresist layer 35. The selectively exposed first photoresist layer 35 is developed to form a pattern 40 in the first photoresist layer 35, as shown in fig. 2C. In some embodiments, actinic radiation EB is an electron beam or an ion beam. In some embodiments, pattern 40 corresponds to a pattern of semiconductor device features that an EUV photomask will be used to form in subsequent operations. In some embodiments, the thickness of the first photoresist layer 35 on the second hard mask layer 32 is in the range from about 500nm to about 1000 nm.
Next, the pattern 40 in the first photoresist layer 35 is extended into the second hard mask layer 32, thereby forming a pattern 41 in the second hard mask layer 32 exposing portions of the first hard mask layer 30, as shown in fig. 2D. In some embodiments, pattern 41 extending into second hard mask layer 32 is formed by etching using a suitable wet or dry etchant that is selective to first hard mask layer 30. In some embodiments, a chlorine-containing gas (e.g., Cl) is used2HCl, BCl and CCl4) And oxygen-containing gas (e.g., O)2) Is used to pattern the second hard mask layer 32. In some embodiments, the material of the first hard mask layer 30 is selected to have higher etch relative to a plasma dry etch operation using chlorine and oxygenEtch resistance (lower etch rate) and the etch substantially stops at the first hard mask layer 30. After forming the pattern 41 in the second hard mask layer 32, the first photoresist layer 35 is removed using a photoresist stripper to expose the upper surface of the second hard mask layer 32, as shown in fig. 2E.
Next, the pattern 41 in the second hard mask layer 32 is extended into the first hard mask layer 30, exposing portions of the oxide layer 27, as shown in fig. 2F. In some embodiments, pattern 41 is formed extending into first hard mask layer 30 by etching using a suitable wet or dry etchant that is selective to oxide layer 27. In some embodiments, a fluorine-containing gas (e.g., fluorocarbon (CF)) is used4、CHF3Etc.) and SF6) Is used to pattern the first hard mask layer 30. In some embodiments, the material of oxide layer 27 is selected to have a higher etch resistance (lower etch rate) relative to a plasma dry etch operation using fluorine, and the etch substantially stops at oxide layer 27.
Then, the patterns 41 in the first and second hard mask layers 30 and 32 are extended into the absorber layer 25, thereby forming patterns 42 in the absorber layer 25, exposing portions of the intermediate layer 22, as shown in fig. 3A. The oxide layer 27 and the absorber layer 25 are etched by using a suitable wet or dry etchant selective to the first hard mask layer 30 and/or the intermediate layer 22. In some embodiments, a chlorine-containing gas (e.g., Cl) is used2HCl, BCl and CCl4) And oxygen-containing gas (e.g., O)2) Is used to pattern the oxide layer 27 and the absorber layer 25. In some embodiments, the material of intermediate layer 22 is selected to have a higher etch resistance (lower etch rate) relative to a plasma dry etch operation using chlorine and oxygen, and the etch substantially stops at intermediate layer 22. In some embodiments, as shown in figure 3A, the second hard mask layer 32 is removed during the etching of the oxide layer 27 and the absorber layer 25. Specifically, when the second hard mask layer 32 is made of a Cr-based material (e.g., CrON or CrCON), the second hard mask layer is made of a Cr-based materialThe mask layer 32 is removed during the etching of the oxide layer 27 and the absorber layer 25. If second hard mask layer 32 remains after etching oxide layer 27 and absorber layer 25, additional removal operations of second hard mask layer 32 are performed in some embodiments by using a suitable wet or dry etch.
Then, the first hard mask layer 30 and the portion of the intermediate layer 22 at the bottom of the pattern opening are removed together, as shown in fig. 3B. In some embodiments, the etching is wet etching and/or dry etching. In some embodiments, a fluorine-containing gas (e.g., fluorocarbon (CF)) is used4、CHF3Etc.) and SF6) Is used to remove the first hard mask layer 30 and the intermediate layer 22. Specifically, when the first hard mask layer 30 is made of the same or similar material as the intermediate layer 22, the first hard mask layer 32 is removed together with the intermediate layer 22. In some embodiments, the material of cap layer 20 is selected to have a higher etch resistance (lower etch rate) relative to a plasma dry etch operation using fluorine, and the etch substantially stops at cap layer 20.
As shown in fig. 3C, a second photoresist layer 50 is formed over the oxide layer 27, filling the pattern 42 in the oxide layer 27. The second photoresist layer 50 is selectively exposed to actinic radiation, such as electron beam, ion beam or UV radiation. The selectively exposed second photoresist layer 50 is developed to form a pattern 55 in the second photoresist layer 50, as shown in fig. 3C. The pattern 55 corresponds to a black border around the circuit pattern. The black border is a frame-shaped area created by removing all the multilayers on the EUV photomask in the area around the circuit pattern area. The frame-shaped region is created to prevent exposure to adjacent fields (fields) when printing an EUV photomask onto a wafer. In some embodiments, the width of the black border ranges from about 1mm to about 5 mm.
Next, the pattern 55 in the second photoresist layer 50 is extended into the oxide layer 27, absorber layer 25, optional intermediate layer 22, cap layer 20, and Mo/Si multilayer 15, thereby forming a pattern 57 (see fig. 3E) in the oxide layer 27, absorber layer 25, intermediate layer 22, cap layer 20, and Mo/Si multilayer 15, exposing portions of the substrate 10, as shown in fig. 3D. In some embodiments, pattern 57 is formed by etching using one or more suitable wet or dry etchants selective to each layer being etched. In some embodiments, a plasma dry etch is used.
The second photoresist layer 50 is then removed by a suitable photoresist stripper to expose the upper surface of the oxide layer 27, as shown in fig. 3E. In some embodiments of the present disclosure, the black edge pattern 57 in the oxide layer 27, absorber layer 25, intermediate layer 22, cap layer 20, and Mo/Si multilayer 15 define the black edges of the photomask. In addition, the photomask is subjected to a cleaning operation, inspected, and repaired as necessary to provide a finished photomask.
Figure 4 illustrates a cross-sectional view of a finished EUV photomask according to embodiments of the present disclosure. In some embodiments, an EUV photomask having a circuit pattern 42 as shown in fig. 4 includes a substrate 10, a multilayer Mo/Si stack 15 composed of a plurality of alternating layers of silicon and molybdenum, a capping layer 20, an intermediate layer 22, a patterned absorber layer 25, and a patterned oxide layer 27. Further, a black border pattern 57 is formed in the oxide layer 27, the absorber layer 25, the intermediate layer 22, the cap layer 20, and the Mo/Si multilayer 15, and a rear conductive layer 45 is formed on the rear surface of the substrate 10. In some embodiments, the patterned absorber layer 25 comprises a CrN layer or a nitrogen-rich CrON or CrCON layer, wherein the nitrogen content in some embodiments ranges from about 10 atomic% to about 30 atomic%.
Fig. 5A, 5B, and 5C illustrate cross-sectional views of a multilayer structure of an absorber layer according to another embodiment of the present disclosure. It should be understood that additional operations may be provided before, during, and after the processes shown in fig. 2A-3E, and that some of the operations described below may be replaced or eliminated with respect to further embodiments of the method. The order of these operations/processes may be interchangeable. Materials, configurations, processes, and/or dimensions explained for the foregoing embodiments may be adopted in the following embodiments, and detailed descriptions thereof may be omitted. The embodiments of fig. 5A, 5B and 5C are for the mask blank shown in fig. 1D, where no oxide layer is formed on the absorber layer 25. Fig. 5A shows the structure after the first hard mask layer 30 is patterned, similar to fig. 2F. The etching of the first hard mask layer 30 substantially stops at the absorber layer 25.
Then, the absorber layer 25 is patterned (etched) by using the patterned first hard mask layer and the patterned second hard mask layer, as shown in fig. 5B. In some embodiments, as shown in figure 5B, the second hard mask layer 32 is removed during the etching of the absorber layer 25. In some embodiments, the etching substantially stops at the intermediate layer 22 when the intermediate layer 22 is made of the same or similar material as the first hard mask layer 30. Then, as shown in fig. 5C, the first hard mask layer 30 is removed together with the portion of the intermediate layer 22 located at the bottom of the opening pattern of the absorber layer 25.
Figure 6 illustrates a cross-sectional view of a finished EUV photomask according to embodiments of the present disclosure. In some embodiments, an EUV photomask having a circuit pattern 42 as shown in fig. 6 includes a substrate 10, a multilayer Mo/Si stack 15 composed of multiple alternating layers of silicon and molybdenum, a capping layer 20, an intermediate layer 22, and a patterned absorber layer 25. Further, a black border pattern 57 is formed in the absorber layer 25, the intermediate layer 22, the cap layer 20, and the Mo/Si multilayer 15, and a rear conductive layer 45 is formed on the rear surface of the substrate 10. In some embodiments, the patterned absorber layer 25 comprises a CrN layer or a nitrogen-rich CrON or CrCON layer, wherein the nitrogen content in some embodiments ranges from about 10 atomic% to about 30 atomic%.
Typically, Cr-based materials (CrN, CrON or CrCON) have a high EUV absorption (extinction) coefficient k. For example, CrN has a k value of 0.0387, which is higher than the k value of TaBN (0.031) and the k value of TaBO (0.027). Thus, the thickness of the absorber layer may be reduced (e.g., from 70nm for TaBN to 46nm for CrN), which may inhibit the three-dimensional effect of the patterned absorber layer. However, since the etching rate of the CrN layer or the nitrogen-rich CrON or CrCON layer is low, it is difficult to etch. Therefore, directly patterning the CrN layer may result in poor pattern profile, thereby affecting the resolution of EUV lithography. In the present embodiment, two hard mask layers are used to pattern the absorber layer, and since the thickness of each hard mask layer is relatively thin (2-20nm), the pattern profile of the etching pattern can be controlled. Therefore, a good pattern profile with a higher etch rate and a higher EUV absorption coefficient can be obtained.
FIG. 7 shows a flow chart for manufacturing a mask blank for an EUV photomask according to an embodiment of the present disclosure.
In some embodiments, at S701, a multi-layer stack 15 is formed over the substrate 10. Then, at S702, a cap layer 20 is formed on the multilayer stack 15, and at S703, a protective layer 22 is formed on the cap layer 20. Next, at S704, the absorber layer 25 is formed on the protective layer 22. Subsequently, a first hard mask layer 30 and a second hard mask layer 32 are formed on the absorber layer 25 at S705 and S706, respectively. In some embodiments, after formation of the absorber layer 25 and before formation of the hard mask layer, an oxide layer 27 is formed by oxidation. In some embodiments, when the hard mask layer is formed without breaking vacuum after the formation of the absorber layer 25, no oxide layer is formed on the top surface of the absorber layer 25.
Fig. 8A shows a flow of a method of manufacturing a semiconductor device, and fig. 8B, 8C, 8D, and 8E show sequential manufacturing operations of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. A semiconductor substrate or other suitable substrate is provided that is to be patterned to form integrated circuits thereon. In some embodiments, the semiconductor substrate comprises silicon. Alternatively or additionally, the semiconductor substrate comprises germanium, silicon germanium, or other suitable semiconductor materials, such as group III-V semiconductor materials. In S801 of fig. 8A, a target layer to be patterned is formed over a semiconductor substrate. In some embodiments, the target layer is a semiconductor substrate. In some embodiments, the target layer comprises a conductive layer such as a metallization layer or a polysilicon layer, a dielectric layer such as silicon oxide, silicon nitride, SiON, SiOC, SiOCN, SiCN, hafnium oxide, or aluminum oxide, or a semiconductor layer such as an epitaxially formed semiconductor layer. In some embodiments, the target layer is formed over underlying structures such as isolation structures, transistors, or wires. At S802 of fig. 8A, a photoresist layer is formed over the target layer, as shown in fig. 8B. In a subsequent lithographic exposure process, the photoresist layer is sensitive to radiation from an exposure source. In this embodiment, the photoresist layer is sensitive to EUV light used in the photolithography exposure process. A photoresist layer may be formed over the target layer by spin coating or other suitable techniques. The coated photoresist layer may be further baked to drive off the solvent in the photoresist layer. In S803 of fig. 8A, the photoresist layer is patterned using the EUV reflective mask as described above, as shown in fig. 8B. Patterning the photoresist layer includes performing a photolithography exposure process using an EUV exposure system using an EUV mask. In an exposure process, an Integrated Circuit (IC) design pattern defined on an EUV mask is imaged onto a photoresist layer to form a latent image (latent pattern) thereon. Patterning the photoresist layer further includes developing the exposed photoresist layer to form a patterned photoresist layer having one or more openings. In one embodiment where the photoresist layer is a positive photoresist layer, the exposed portions of the photoresist layer are removed in a developing process. Patterning the photoresist layer may also include other process steps, such as various baking steps at different stages. For example, a Post Exposure Bake (PEB) process may be performed after the photolithography exposure process and before the development process.
In S804 of fig. 8A, the target layer is patterned using the patterned photoresist layer as an etch mask, as shown in fig. 8D. In some embodiments, patterning the target layer includes applying an etch process to the target layer using the patterned photoresist layer as an etch mask. The portions of the target layer exposed within the openings of the patterned photoresist layer are etched while the remaining portions are not etched. In addition, the patterned photoresist layer may be removed by wet stripping or plasma ashing, as shown in fig. 8E.
In the present embodiment, the absorber layer is patterned using two hard mask layers, and since the thickness of each hard mask layer is relatively thin (2-20nm), the pattern profile of the etching pattern can be controlled. Therefore, a good pattern profile with a higher etch rate and a higher EUV absorption coefficient can be obtained. Furthermore, since the CrN or nitrogen-rich CrON or CrCON layer has a higher EUV absorption coefficient, the thickness of the absorber layer can be reduced, which in turn suppresses the three-dimensional effect in EUV lithography.
It is to be understood that not necessarily all advantages may have been discussed herein, that no particular advantage is required in all embodiments or examples, and that other embodiments or examples may have different advantages. According to one aspect of the present application, a reflective mask includes: the absorber layer includes a substrate, a reflective multilayer disposed on the substrate, a cap layer disposed on the reflective multilayer, and an absorber layer disposed on the cap layer. The absorber layer includes a CrN layer, a CrON layer having a nitrogen concentration of 10 atomic% to 30 atomic%, or a CrCON layer having a nitrogen concentration of 10 atomic% to 30 atomic%. In one or more of the foregoing and following embodiments, the absorber layer has a thickness in a range from 20nm to 50 nm. In one or more of the foregoing and following embodiments, the absorber layer includes a CrN layer having a nitrogen concentration of 16 atomic% to 40 atomic%. In one or more of the foregoing and following embodiments, the CrN layer includes a Cr phase and Cr2And (4) N phase. In one or more of the foregoing and following embodiments, the CrN layer is formed of Cr2And (4) N-phase composition. In one or more of the foregoing and following embodiments, the CrN layer comprises Cr2N phase and CrN phase. In one or more of the foregoing and following embodiments, the reflective mask further comprises an intermediate layer disposed on the cap layer. In one or more of the foregoing and the following embodiments, the intermediate layer comprises at least one of: TaB, TaO, TaBO or TaBN, silicon-based compounds, ruthenium or ruthenium-based compounds. In one or more of the foregoing and the following embodiments, the intermediate layer comprises at least one of: titanium oxide (TiO)2) Tin oxide (SnO), zinc oxide (ZnO) or cadmium sulfide (CdS). In one or more of the foregoing and following embodiments, a size of an outer periphery of the absorber layer is smaller than a size of an outer periphery of the substrate in a plan view. In one or more of the foregoing and following embodiments, the absorber layer is in plan viewIs in the range from 138mm x 138mm to 142mm x 142mm, and the outer periphery of the substrate is in the range from 148mm x 148mm to 152mm x 152mm in a plan view.
According to another aspect of the present disclosure, a reflective mask includes: the multilayer structure includes a substrate, a reflective multilayer disposed on the substrate, a cap layer disposed on the reflective multilayer, an absorber layer disposed on the cap layer, and a Cr oxide layer disposed on the absorber layer. The absorber layer includes a CrN layer, a CrON layer having a nitrogen concentration of 10 atomic% to 30 atomic%, or a CrCON layer having a nitrogen concentration of 10 atomic% to 30 atomic%. In one or more of the foregoing and following embodiments, the Cr oxide layer includes Cr2O3Or CrO2. In one or more of the foregoing and following embodiments, the thickness of the Cr oxide layer is in a range from 1nm to 3 nm. In one or more of the foregoing and following embodiments, the reflective mask further comprises: an intermediate layer disposed on the cap layer. In one or more of the foregoing and the following embodiments, the intermediate layer comprises at least one of: TaB, TaO, TaBO, or TaBN.
According to another aspect of the present disclosure, a reflective mask blank for an EUV mask, comprises: the absorber layer includes a substrate, a reflective multilayer disposed on the substrate, a cap layer disposed on the reflective multilayer, an intermediate layer disposed on the cap layer, an absorber layer disposed on the intermediate layer, a first hard mask layer disposed on the absorber layer, and a second hard mask layer disposed on the first hard mask layer. In one or more of the foregoing and following embodiments, the second hard mask layer is made of a material having a higher etch rate for plasma including chlorine and oxygen than a material of the first hard mask layer. In one or more of the foregoing and following embodiments, the first hard mask layer is made of a material having a higher etch rate for a plasma including fluorine than a material of the second hard mask layer. In one or more of the foregoing and following embodiments, the absorber layer includes a CrN layer, a CrON layer having a nitrogen concentration of 10 atomic% to 30 atomic%, or a CrCON layer having a nitrogen concentration of 10 atomic% to 30 atomic%.
According to another aspect of the present disclosure, in a method of manufacturing a reflective mask, a photoresist layer is formed over a mask blank. The mask blank includes: the absorber layer includes a substrate, a reflective multilayer on the substrate, a cap layer on the reflective multilayer, an intermediate layer on the cap layer, an absorber layer on the intermediate layer, a first hardmask layer on the absorber layer, and a second hardmask layer on the first hardmask layer. Patterning the photoresist layer, patterning the second hard mask layer by using the patterned photoresist layer, patterning the first hard mask layer by using the patterned second hard mask layer, and patterning the absorber layer by using the patterned first hard mask layer and the patterned second hard mask layer. In one or more of the foregoing and following embodiments, a first plasma dry etch using a chlorine-containing gas and an oxygen-containing gas is employed in patterning the second hard mask layer. In one or more of the foregoing and following embodiments, the second hard mask layer is made of a material having a higher etching rate in plasma dry etching than a material of the first hard mask layer. In one or more of the foregoing and following embodiments, a second plasma dry etch using a chlorine-containing gas and an oxygen-containing gas is employed in patterning the absorber layer. In one or more of the foregoing and following embodiments, the patterned second hard mask layer is removed during a second plasma dry etch. In one or more of the foregoing and following embodiments, a first plasma dry etch using a fluorine-containing gas is employed in patterning the first hard mask layer. In one or more of the foregoing and following embodiments, the first hard mask layer is made of a material having a higher etching rate in plasma dry etching than a material of the second hard mask layer. In one or more of the foregoing embodiments and the following embodiments, after patterning the absorber layer, the intermediate layer is patterned by using a second plasma dry etching using a fluorine-containing gas. In one or more of the foregoing and following embodiments, the intermediate layer is made of a material having a higher etching rate in the second plasma dry etching than a material of the second hard mask layer. In one or more of the foregoing and following embodiments, the patterned first hard mask layer is removed during the second plasma dry etch.
According to another aspect of the present disclosure, in a method of manufacturing a reflective mask, a photoresist layer is formed over a mask blank. The mask blank includes: the absorber layer includes a substrate, a reflective multilayer on the substrate, a cap layer on the reflective multilayer, an intermediate layer on the cap layer, an absorber layer on the intermediate layer, a first hardmask layer on the absorber layer, and a second hardmask layer on the first hardmask layer. Patterning the photoresist layer, patterning the second hard mask layer by using the patterned photoresist layer, patterning the first hard mask layer by using the patterned second hard mask layer, patterning the absorber layer by using the patterned first hard mask layer and the patterned second hard mask layer, and removing the first hard mask layer. The second hard mask layer and the absorber layer include a Cr-based compound, and the first hard mask layer and the intermediate layer include a Ta-based compound. In one or more of the foregoing and following embodiments, the second hard mask layer is made of CrON or CrCON, and the absorber layer is made of CrN, CrON having a nitrogen concentration of 10 atomic% to 30 atomic%, or CrCON having a nitrogen concentration of 10 atomic% to 30 atomic%. In one or more of the foregoing and following embodiments, the first hard mask layer is made of TaBO, Ta2O5、TaO2TaO or Ta2O and an intermediate layer made of TaBO, Ta2O5、TaO2TaO or Ta2And O. In one or more of the foregoing and following embodiments, the second hard mask layer is removed during patterning of the absorber layer. In one or more of the foregoing and following embodiments, a portion of the intermediate layer is patterned during the removing of the first hard mask layer.
According to another aspect of the present disclosure, in a method of manufacturing a reflective mask, a photoresist layer is formed over a mask blank. The mask blank includes a substrate, a reflective multilayer on the substrate, a cap layer on the reflective multilayer, an intermediate layer on the cap layer, an absorber layer on the intermediate layer, an oxide layer on the absorber layer, a first hard mask layer on the oxide layer, and a second hard mask layer on the first hard mask layerAnd a second hard mask layer on the substrate. Patterning the photoresist layer, patterning the second hard mask layer by using the patterned photoresist layer, patterning the first hard mask layer by using the patterned second hard mask layer, patterning the oxide layer and the absorber layer by using the patterned first hard mask layer and the patterned second hard mask layer, and patterning the intermediate layer. In one or more of the foregoing and following embodiments, the second hard mask layer and the absorber layer include materials having a higher etching rate in plasma dry etching using a chlorine-containing gas and an oxygen-containing gas than the materials of the first hard mask layer and the intermediate layer. In one or more of the foregoing and following embodiments, a thickness of each of the first and second hard mask layers is in a range from 2nm to 20 nm. In one or more of the foregoing and following embodiments, the second hard mask layer comprises GaN, SiCO, or yttria. In one or more of the foregoing and following embodiments, the oxide layer comprises Cr2O3Or CrO2。
The foregoing outlines features of several embodiments or examples so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Example 1. a reflective mask, comprising: a substrate; a reflective multilayer disposed on the substrate; a capping layer disposed on the reflective multilayer; and an absorber layer disposed on the cap layer, wherein the absorber layer includes a CrN layer, a CrON layer having a nitrogen concentration of 10 atomic% to 30 atomic%, or a CrCON layer having a nitrogen concentration of 10 atomic% to 30 atomic%.
Example 2. the reflective mask of example 1, wherein the absorber layer has a thickness in a range from 20nm to 50 nm.
Example 3. the reflective mask of example 1, wherein the absorber layer comprises a CrN layer having a nitrogen concentration of 16 atomic% to 40 atomic%.
Example 4. the reflective mask of example 3, wherein the CrN layer includes a Cr phase and Cr2And (4) N phase.
Example 5. the reflective mask of example 3, wherein the CrN layer is made of Cr2And (4) N-phase composition.
Example 6 the reflective mask of example 3, wherein the CrN layer comprises Cr2N phase and CrN phase.
Example 7. the reflective mask of example 1, further comprising: an intermediate layer disposed on the cap layer.
Example 8. the reflective mask of example 7, wherein the intermediate layer comprises at least one of: TaB, TaO, TaBO or TaBN, silicon-based compounds, ruthenium or ruthenium-based compounds.
Example 9. the reflective mask of example 7, wherein the intermediate layer comprises at least one of: titanium oxide (TiO)2) Tin oxide (SnO), zinc oxide (ZnO) or cadmium sulfide (CdS).
Example 10. the reflective mask of example 1, wherein, in a plan view, a size of an outer periphery of the absorber layer is smaller than a size of an outer periphery of the substrate.
Example 11 a method of fabricating a reflective mask, the method comprising: forming a photoresist layer over a mask blank, the mask blank comprising a substrate, a reflective multilayer on the substrate, a cap layer on the reflective multilayer, an intermediate layer on the cap layer, an absorber layer on the intermediate layer, a first hard mask layer on the absorber layer, and a second hard mask layer on the first hard mask layer; patterning the photoresist layer; patterning the second hard mask layer by using the patterned photoresist layer; patterning the first hard mask layer by using the patterned second hard mask layer; patterning the absorber layer by using a patterned first hard mask layer and a patterned second hard mask layer; and removing the first hard mask layer, wherein the second hard mask layer and the absorber layer include a Cr-based compound, and the first hard mask layer and the intermediate layer include a Ta-based compound.
Example 12 the method of example 11, wherein the second hard mask layer is made of CrON or CrCON, and the absorber layer is made of CrN, CrON with a nitrogen concentration of 10 atomic% to 30 atomic%, or CrCON with a nitrogen concentration of 10 atomic% to 30 atomic%.
Example 13. the method of example 11, wherein the first hard mask layer is made of TaBO, Ta2O5、TaO2TaO or Ta2O and the intermediate layer is made of TaBO, Ta2O5、TaO2TaO or Ta2And O.
Example 14. the method of example 11, wherein the second hard mask layer is removed during patterning the absorber layer.
Example 15 the method of example 11, wherein a portion of the intermediate layer is patterned during the removing of the first hard mask layer.
Example 16. a method of fabricating a reflective mask, the method comprising: forming a photoresist layer over a mask blank, the mask blank comprising a substrate, a reflective multilayer on the substrate, a cap layer on the reflective multilayer, an intermediate layer on the cap layer, an absorber layer on the intermediate layer, an oxide layer on the absorber layer, a first hard mask layer on the oxide layer, and a second hard mask layer on the first hard mask layer; patterning the photoresist layer; patterning the second hard mask layer by using the patterned photoresist layer; patterning the first hard mask layer by using the patterned second hard mask layer; patterning the oxide layer and the absorber layer by using a patterned first hard mask layer and a patterned second hard mask layer; and patterning the intermediate layer.
Example 17. the method of example 16, wherein the second hard mask layer and the absorber layer comprise materials having a higher etch rate in plasma dry etching using a chlorine-containing gas and an oxygen-containing gas than a material of the first hard mask layer and a material of the intermediate layer.
Example 18 the method of example 17, wherein a thickness of each of the first and second hard mask layers is in a range from 2nm to 20 nm.
Example 19. the method of example 17, wherein the second hard mask layer comprises GaN, SiCO, or yttria.
Example 20. the method of example 17, wherein the oxide layer includes Cr2O3Or CrO2。
