1. An array substrate, comprising:

a substrate base plate;

the first metal layer is arranged on the substrate base plate;

the first insulating layer is arranged on the first metal layer;

a second metal layer disposed on the first insulating layer;

the second insulating layer is arranged on the second metal layer;

a pixel electrode layer disposed on the second insulating layer, the pixel electrode layer including a pixel electrode;

the array substrate further comprises a plurality of common wires and a plurality of voltage dividing wires, the common wires are formed by patterning the first metal layer or the second metal layer, the voltage dividing wires are formed by patterning the first metal layer or the second metal layer, and the orthographic projection of the common wires on the substrate is not overlapped with the orthographic projection of the voltage dividing wires on the substrate.

2. The array substrate of claim 1, wherein the common traces and the voltage divider traces are disposed in the same layer.

3. The array substrate of claim 1, wherein the common trace is disposed parallel to the voltage divider trace.

4. The array substrate of claim 1, wherein the shape of the area defined by the projection of each common trace on the substrate comprises a square, and the shape of the area defined by the projection of each voltage divider trace on the substrate comprises a square.

5. The array substrate of claim 1, wherein each common trace comprises: a first portion and a second portion extending in a first direction and arranged in a second direction, and a plurality of third portions extending in the second direction and electrically connecting the first portion and the second portion;

each said voltage divider trace includes: the second portion is arranged along the second direction, and the plurality of sixth portions extend along the second direction and electrically connect the fourth portion and the fifth portion.

6. The array substrate of claim 1, wherein the first metal layer comprises a plurality of scan lines extending along a first direction, and the second metal layer comprises a plurality of data lines extending along a second direction;

the common wire and the voltage dividing wire extend along the first direction, and the common wire and the voltage dividing wire are both arranged on the first metal layer.

7. The array substrate of claim 6, wherein an orthographic projection of the common trace on the substrate is not overlapped with an orthographic projection of the scan line on the substrate;

the orthographic projection of the partial pressure routing on the substrate base plate is not overlapped with the orthographic projection of the scanning line on the substrate base plate.

8. The array substrate according to claim 6, wherein one common trace and one voltage dividing trace are disposed between two adjacent scan lines.

9. The array substrate according to claim 8, wherein a plurality of pixel electrodes are further disposed between two adjacent scan lines, each pixel electrode includes a main pixel electrode and an auxiliary pixel electrode, and the voltage dividing trace is electrically connected to the main pixel electrode.

10. The array substrate of claim 9, wherein an orthographic projection of the main pixel electrode on the substrate at least partially coincides with an orthographic projection of the voltage dividing trace on the substrate, and an orthographic projection of the auxiliary pixel electrode on the substrate at least partially coincides with an orthographic projection of the common trace on the substrate.

11. The array substrate of claim 9, wherein the main pixel electrode and the auxiliary pixel electrode disposed on opposite sides of the same scan line along the second direction are electrically connected to the same data line through a switching element.

12. A display panel, comprising: the array substrate of any one of claims 1 to 11, a counter substrate disposed opposite the array substrate, and a liquid crystal disposed between the array substrate and the counter substrate.

Background

Liquid crystal display is one of the most widely used display modes in the display technology field today. The liquid crystal display panel comprises an array substrate, an opposite substrate and liquid crystal positioned between the array substrate and the opposite substrate, wherein an electric field provided by a pixel electrode positioned on the array substrate is a power source for promoting liquid crystal molecules to deflect. In order to make the liquid crystal display panel have a larger visual angle, a pixel electrode in each pixel is divided into a main electrode and an auxiliary electrode, and the main electrode is connected with a voltage division line to reduce the electric field intensity generated by the main electrode; under the action of different electric field intensities of the main electrode and the auxiliary electrode, liquid crystal molecules in the same pixel deflect at different angles, so that the visualization angle of the display panel is improved. However, the quality of the display panel is seriously affected by the short circuit between the voltage dividing trace and the common trace on the array substrate caused by particle impurities or electrostatic discharge.

Therefore, the conventional liquid crystal display panel has the technical problem that the voltage dividing wiring and the common wiring are short-circuited.

Disclosure of Invention

The application provides an array substrate and a display panel, which are used for relieving the technical problem that the voltage division wiring and the public wiring of the existing liquid crystal display panel are short-circuited.

The application provides an array substrate, it includes:

a substrate base plate;

the first metal layer is arranged on the substrate base plate;

the first insulating layer is arranged on the first metal layer;

a second metal layer disposed on the first insulating layer;

the second insulating layer is arranged on the second metal layer;

a pixel electrode layer disposed on the second insulating layer, the pixel electrode layer including a pixel electrode;

the array substrate further comprises a plurality of common wires and a plurality of voltage dividing wires, the common wires are formed by patterning the first metal layer or the second metal layer, the voltage dividing wires are formed by patterning the first metal layer or the second metal layer, and the orthographic projection of the common wires on the substrate is not overlapped with the orthographic projection of the voltage dividing wires on the substrate.

In the array substrate of the present application, the common trace and the voltage dividing trace are disposed on the same layer.

In the array substrate of the present application, the common trace is parallel to the voltage dividing trace.

In the array substrate of the present application, a shape of an area surrounded by projections of each common trace on the substrate includes a square, and a shape of an area surrounded by projections of each partial voltage trace on the substrate includes a square.

In the array substrate of the present application, each of the common lines includes: a first portion and a second portion extending in a first direction and arranged in a second direction, and a plurality of third portions extending in the second direction and electrically connecting the first portion and the second portion;

each said voltage divider trace includes: the second portion is arranged along the second direction, and the plurality of sixth portions extend along the second direction and electrically connect the fourth portion and the fifth portion.

In the array substrate of the present application, the first metal layer includes a plurality of scan lines extending along a first direction, and the second metal layer includes a plurality of data lines extending along a second direction;

the common wire and the voltage dividing wire extend along the first direction, and the common wire and the voltage dividing wire are both arranged on the first metal layer.

In the array substrate of the present application, an orthogonal projection of the common trace on the substrate does not coincide with an orthogonal projection of the scan line on the substrate;

the orthographic projection of the partial pressure routing on the substrate base plate is not overlapped with the orthographic projection of the scanning line on the substrate base plate.

In the array substrate, two adjacent scanning lines are provided with one common line and one voltage dividing line.

In the array substrate of this application, adjacent two still be provided with a plurality ofly between the scanning line pixel electrode, every pixel electrode all includes main pixel electrode and assistance pixel electrode, the partial pressure walk the line with main pixel electrode electric connection.

In the array substrate, the orthographic projection of the main pixel electrode on the substrate is at least partially overlapped with the orthographic projection of the partial pressure wiring on the substrate, and the orthographic projection of the auxiliary pixel electrode on the substrate is at least partially overlapped with the orthographic projection of the common wiring on the substrate.

In the array substrate of this application, follow the second direction sets up in same the relative both sides of scanning line main pixel electrode with it is same that supplementary pixel electrode passes through switching element electric connection the data line.

The present application also provides a display panel, which includes: the liquid crystal display device includes the array substrate, the counter substrate disposed opposite to the array substrate, and the liquid crystal disposed between the array substrate and the counter substrate.

The beneficial effect of this application is: the application provides an array substrate and display panel, the array substrate includes the substrate base plate, sets up first metal level on the substrate base plate, sets up first insulating layer on first metal level, sets up second metal level on first insulating layer, sets up the second insulating layer on the second metal level and sets up the pixel electrode layer on the second insulating layer, the array substrate still includes many public wirings and many partial pressure and walks the line, public wiring by first metal level or second metal level patterning forms, partial pressure is walked by first metal level or second metal level patterning forms, public wiring is in orthographic projection on the substrate base plate with partial pressure is walked and is in orthographic projection on the substrate base plate does not have the coincidence. This application is walked the orthographic projection of line on the substrate base plate and is walked the orthographic projection of line on the substrate base plate to set up to no coincidence with the partial pressure through being public for public walking is walked the line and is walked the line along array substrate thickness direction and stagger each other with the partial pressure, has reduced public walking and has walked the risk of taking place the short circuit between the line with the partial pressure, has improved display panel's quality.

Drawings

The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.

Fig. 1 is a first partial perspective view of an array substrate provided in an embodiment of the present application.

Fig. 2 is a second partial perspective view of an array substrate provided in an embodiment of the present application.

Fig. 3 is a schematic cross-sectional view of the array substrate shown in fig. 2 in a switching element region.

Fig. 4 is a schematic cross-sectional view of the array substrate shown in fig. 2 in a voltage dividing routing area.

Fig. 5 is a schematic cross-sectional view of the array substrate shown in fig. 2 in a voltage dividing routing area.

Fig. 6 is a schematic cross-sectional view of the array substrate shown in fig. 2 in a voltage dividing routing area.

Fig. 7 is a schematic cross-sectional view of the array substrate shown in fig. 2 in a second cross-sectional structure of the switching element region.

Fig. 8 is a schematic cross-sectional view of the array substrate shown in fig. 2 in a voltage dividing routing area.

Fig. 9 is a schematic structural diagram of a display panel according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The embodiment of the application provides an array substrate and a display panel, the array substrate comprises a substrate base plate, a first metal layer arranged on the substrate base plate, a first insulating layer arranged on the first metal layer, a second metal layer arranged on the first insulating layer, a second insulating layer arranged on the second metal layer and a pixel electrode layer arranged on the second insulating layer, the array substrate further comprises a plurality of public wiring lines and a plurality of partial pressure wiring lines, the public wiring lines are formed by patterning of the first metal layer or the second metal layer, the partial pressure wiring lines are formed by patterning of the first metal layer or the second metal layer, the public wiring lines are in orthographic projection on the substrate base plate and the partial pressure wiring lines are in orthographic projection non-coincidence on the substrate base plate. The orthographic projection of the public wiring on the substrate base plate and the orthographic projection of the partial pressure wiring on the substrate base plate are set to be free of coincidence, so that the public wiring and the partial pressure wiring are staggered with each other along the thickness direction of the array base plate, and the risk of short circuit between the public wiring and the partial pressure wiring is reduced.

The structural features of the array substrate provided by the present application are described below with reference to specific embodiments.

In an embodiment, please refer to fig. 1 to 4, wherein fig. 1 is a first partial perspective view of an array substrate provided in the present application, fig. 2 is a second partial perspective view of the array substrate provided in the present application, fig. 3 is a first cross-sectional structure diagram of the array substrate shown in fig. 2 in a switch element area, and fig. 4 is a first cross-sectional structure diagram of the array substrate shown in fig. 2 in a voltage dividing routing area.

The array substrate includes: a substrate base plate 101, a first metal layer disposed on the substrate base plate 101, a first insulating layer 102 disposed on the first metal layer, a second metal layer disposed on the first insulating layer 102, a second insulating layer 103 disposed on the second metal layer, and a pixel electrode layer disposed on the second insulating layer 103; the first metal layer comprises a scanning line Sc, a partial pressure line S _ Com and a common line A _ Com; the second metal layer includes a data line Da; the pixel electrode layer includes a pixel electrode P including a main pixel electrode P1 and an auxiliary pixel electrode P2.

Alternatively, the base substrate 101 may be a hard substrate such as a glass substrate, or may be a flexible substrate such as a polyimide substrate. A buffer layer may be further disposed between the substrate base plate 101 and the first metal layer to alleviate the problem of stress mismatch between the substrate base plate 101 and the first metal layer, and the buffer layer may include a combination film of multiple organic material layers and inorganic material layers.

The first insulating layer 102 and the second insulating layer 103 are made of insulating materials. Alternatively, the first insulating layer 102 and the second insulating layer 103 may be a silicon nitride layer, a silicon oxide layer, or the like formed by a chemical vapor deposition process.

Specifically, the common trace a _ Com and the partial pressure trace S _ Com are both formed by patterning the first metal layer, and an orthographic projection of the common trace a _ Com on the substrate base plate 101 does not coincide with an orthographic projection of the partial pressure trace S _ Com on the substrate base plate 101, that is, in the first metal layer, a wiring area of the common trace a _ Com and a wiring area of the partial pressure trace S _ Com are staggered, so that a short circuit problem occurring when the common trace and the partial pressure trace are overlapped is avoided, and reliability of the array substrate device is improved.

Further, the common trace a _ Com and the partial pressure trace S _ Com are parallel, the common trace a _ Com and the partial pressure trace S _ Com both extend along a first direction X, and the plurality of common traces a _ Com and the plurality of partial pressure traces S _ Com are arranged along a second direction Y. Optionally, the first direction X and the second direction Y are two directions perpendicular to each other.

Further, the shape of an area defined by the orthographic projection of each common trace a _ Com on the substrate base plate 101 includes a square, and the shape of an area defined by the orthographic projection of each partial voltage trace S _ Com on the substrate base plate 101 also includes a square.

It should be noted that the common trace a _ Com serves to form a storage capacitor with the pixel electrode P to maintain the electric field intensity generated by the pixel electrode P, and the common trace a _ Com having a square structure has more overlapping space with the pixel electrode P, which is more beneficial to forming a stable and uniform storage capacitor. The voltage dividing trace S _ Com serves to reduce the voltage of the main pixel electrode P1, and the overlapping area between the voltage dividing trace S _ Com having a square structure and the main pixel electrode P1 is more, which is beneficial to forming more electrical connections with the main pixel electrode P1 and promoting the main pixel electrode P1 to generate stable and uniform electric field intensity.

Further, each of the common traces a _ Com includes: a first portion a1 and a second portion a2 extending in the first direction X and aligned in the second direction Y, and a plurality of third portions A3 extending in the second direction Y and electrically connecting the first portion a1 and the second portion a 2. The common trace a _ Com with the above structure has more overlapping areas with the pixel electrode P, which is beneficial to forming a stable and uniform storage capacitor with the pixel electrode P.

Each partial pressure wire S _ Com comprises: a fourth portion S1 and a fifth portion S2 extending in the first direction X and arranged in the second direction Y, and a plurality of sixth portions S3 extending in the second direction Y and electrically connecting the fourth portion S1 and the fifth portion S2. The overlapping area between the voltage dividing trace S _ Com and the main pixel electrode P1 with the above structure is more, which is beneficial to forming more electrical connections with the main pixel electrode P1 and promoting the main pixel electrode P1 to generate stable and uniform electric field intensity.

The scanning lines Sc extend along the first direction X, and a plurality of the scanning lines Sc are arranged along the second direction Y; the data lines Da extend along the second direction Y, and a plurality of the data lines Da are arranged along the first direction X. Each grid region defined by the intersection of the scan lines Sc and the data lines Da corresponds to a pixel region, and each pixel region is provided with one main pixel electrode P1 and one auxiliary pixel electrode P2. The main pixel electrode P1 and the auxiliary pixel electrode P2 may be pixel electrodes having branches in a shape of a Chinese character mi.

Alternatively, the main pixel electrode P1 and the auxiliary pixel electrode P2 are both indium tin oxide electrodes.

Further, the partial voltage trace S _ Com, the common trace a _ Com, and the scan line Sc are all located in the first metal layer, and an orthographic projection of the common trace a _ Com on the substrate base plate 101 does not coincide with an orthographic projection of the scan line Sc on the substrate base plate 101; the orthographic projection of the partial voltage trace S _ Com on the substrate 101 does not coincide with the orthographic projection of the scan line Sc on the substrate 101.

A common line A _ Com and a partial voltage line S _ Com are arranged between two adjacent scanning lines Sc; wherein, the orthographic projection of the main pixel electrode P1 on the substrate base plate 101 at least partially coincides with the orthographic projection of the partial voltage trace S _ Com on the substrate base plate 101, and the orthographic projection of the auxiliary pixel electrode P2 on the substrate base plate 101 at least partially coincides with the orthographic projection of the trace common a _ Com on the substrate base plate 101.

Further, the voltage dividing trace S _ Com is electrically connected to the main pixel electrode P1, and the voltage dividing trace S _ Com is used for reducing the voltage of the main pixel electrode P1, so that the electric field intensity generated by the main pixel electrode P1 is different from the electric field intensity generated by the auxiliary pixel electrode P2. When the array substrate is applied to a liquid crystal display panel, the liquid crystal molecules in the same pixel region can generate different deflection angles due to the design of the embodiment, so that the visualization angle of the liquid crystal display panel is improved.

Further, the main pixel electrode P1 and the auxiliary pixel electrode P2 disposed at two opposite sides of the same scan line Sc along the second direction Y are electrically connected to the same data line Da via a switch element K. The main pixel electrode P1 and the auxiliary pixel electrode P2 generate a specific electric field strength when receiving the data signal transmitted by the data line Da, and the main pixel electrode P1 forms an electric field strength different from that of the auxiliary pixel electrode P2 under the action of the voltage dividing trace S _ Com.

Alternatively, the switching element K may be a thin film transistor device. Specifically, the switching element K includes a gate G, a channel C, a source S, and a drain D; the gate G is disposed on the first metal layer, the source S and the drain D are disposed on the second metal layer, the channel C is disposed on the first insulating layer 102, and the source S and the drain D are respectively and correspondingly connected to two opposite ends of the channel C. The gate G is electrically connected to the scan line Sc, the source S is electrically connected to the data line Da, and the drain D is electrically connected to the pixel electrode P, specifically, the drain D is electrically connected to the main pixel electrode P1 and the auxiliary pixel electrode P2 at the same time.

In an embodiment, please refer to fig. 1, fig. 2 and fig. 5, wherein fig. 5 is a schematic cross-sectional view of the array substrate shown in fig. 2 in a voltage dividing routing area. The array substrate shown in fig. 5 has the same or similar structural features as the array substrates shown in fig. 3 and 4, and the structural features of the array substrate shown in fig. 5 will be described below, wherein the description of the above embodiments is referred to for details.

In this embodiment, the array substrate includes: a substrate 101, a first metal layer disposed on the substrate 101, a first insulating layer 102 disposed on the first metal layer, a second metal layer disposed on the first insulating layer 102, a second insulating layer 103 disposed on the second metal layer, a third metal layer disposed on the second insulating layer 103, a third insulating layer 104 disposed on the third metal layer, and a pixel electrode layer disposed on the third insulating layer 104.

The first metal layer comprises a scanning line Sc and a voltage division line S _ Com; the second metal layer comprises a common trace A _ Com, and the third metal layer comprises a data line Da; the pixel electrode layer includes a pixel electrode P including a main pixel electrode P1 and an auxiliary pixel electrode P2.

Furthermore, the orthographic projection of the common trace a _ Com on the substrate base plate 101 does not coincide with the orthographic projection of the partial pressure trace S _ Com on the substrate base plate 101, that is, the wiring area of the common trace a _ Com is staggered with the wiring area of the partial pressure trace S _ Com, so that the problem of short circuit when the common trace and the partial pressure trace are overlapped is avoided, and the reliability of the array substrate device is improved.

Further, the common trace a _ Com and the partial pressure trace S _ Com are parallel, the common trace a _ Com and the partial pressure trace S _ Com both extend along a first direction X, and the plurality of common traces a _ Com and the plurality of partial pressure traces S _ Com are arranged along a second direction Y. Optionally, the first direction X and the second direction Y are two directions perpendicular to each other.

Further, the shape of an area defined by the orthographic projection of each common trace a _ Com on the substrate base plate 101 includes a square, and the shape of an area defined by the orthographic projection of each partial voltage trace S _ Com on the substrate base plate 101 also includes a square.

Each of the common traces a _ Com includes: a first portion a1 and a second portion a2 extending in the first direction X and aligned in the second direction Y, and a plurality of third portions A3 extending in the second direction Y and electrically connecting the first portion a1 and the second portion a 2.

Each partial pressure wire S _ Com comprises: a fourth portion S1 and a fifth portion S2 extending in the first direction X and arranged in the second direction Y, and a plurality of sixth portions S3 extending in the second direction Y and electrically connecting the fourth portion S1 and the fifth portion S2.

The scanning lines Sc extend along the first direction X, and a plurality of the scanning lines Sc are arranged along the second direction Y; the data lines Da extend along the second direction Y, and a plurality of the data lines Da are arranged along the first direction X.

The orthographic projection of the common trace A _ Com on the substrate base plate 101 is not overlapped with the orthographic projection of the scanning line Sc on the substrate base plate 101; the orthographic projection of the partial voltage trace S _ Com on the substrate 101 does not coincide with the orthographic projection of the scan line Sc on the substrate 101.

The voltage dividing trace S _ Com is electrically connected to the main pixel electrode P1, and the voltage dividing trace S _ Com is used for reducing the voltage of the main pixel electrode P1, so that the electric field intensity generated by the main pixel electrode P1 is different from the electric field intensity generated by the auxiliary pixel electrode P2.

Further, the main pixel electrode P1 and the auxiliary pixel electrode P2 disposed at two opposite sides of the same scan line Sc along the second direction Y are electrically connected to the same data line Da via a switch element K.

In an embodiment, please refer to fig. 1, fig. 2 and fig. 6, wherein fig. 6 is a schematic cross-sectional view of the array substrate shown in fig. 2 in a voltage dividing routing area. The array substrate shown in fig. 6 has the same or similar structural features as the array substrates shown in fig. 3 and 4, and the structural features of the array substrate shown in fig. 6 will be described below, wherein the description of the above embodiments is referred to for details.

In this embodiment, the array substrate includes: a substrate 101, a first metal layer disposed on the substrate 101, a first insulating layer 102 disposed on the first metal layer, a second metal layer disposed on the first insulating layer 102, a second insulating layer 103 disposed on the second metal layer, a third metal layer disposed on the second insulating layer 103, a third insulating layer 104 disposed on the third metal layer, and a pixel electrode layer disposed on the third insulating layer 104.

The first metal layer comprises a scanning line Sc and a common line A _ Com; the second metal layer comprises a voltage division line S _ Com, and the third metal layer comprises a data line Da; the pixel electrode layer includes a pixel electrode P including a main pixel electrode P1 and an auxiliary pixel electrode P2.

Furthermore, the orthographic projection of the common line a _ Com on the substrate base plate 101 does not coincide with the orthographic projection of the partial pressure line S _ Com on the substrate base plate 101, so that the problem of short circuit when the common line and the partial pressure line are overlapped is avoided, and the reliability of the array substrate device is improved.

Further, the common trace a _ Com and the partial pressure trace S _ Com are parallel, the common trace a _ Com and the partial pressure trace S _ Com both extend along a first direction X, and the plurality of common traces a _ Com and the plurality of partial pressure traces S _ Com are arranged along a second direction Y.

Further, the shape of an area defined by the orthographic projection of each common trace a _ Com on the substrate base plate 101 includes a square, and the shape of an area defined by the orthographic projection of each partial voltage trace S _ Com on the substrate base plate 101 also includes a square.

Each of the common traces a _ Com includes: a first portion a1 and a second portion a2 extending in the first direction X and aligned in the second direction Y, and a plurality of third portions A3 extending in the second direction Y and electrically connecting the first portion a1 and the second portion a 2.

Each partial pressure wire S _ Com comprises: a fourth portion S1 and a fifth portion S2 extending in the first direction X and arranged in the second direction Y, and a plurality of sixth portions S3 extending in the second direction Y and electrically connecting the fourth portion S1 and the fifth portion S2.

The scanning lines Sc extend along the first direction X, and a plurality of the scanning lines Sc are arranged along the second direction Y; the data lines Da extend along the second direction Y, and a plurality of the data lines Da are arranged along the first direction X.

The orthographic projection of the common trace A _ Com on the substrate base plate 101 is not overlapped with the orthographic projection of the scanning line Sc on the substrate base plate 101; the orthographic projection of the partial voltage trace S _ Com on the substrate 101 does not coincide with the orthographic projection of the scan line Sc on the substrate 101.

The voltage dividing trace S _ Com is electrically connected to the main pixel electrode P1, and the voltage dividing trace S _ Com is used for reducing the voltage of the main pixel electrode P1, so that the electric field intensity generated by the main pixel electrode P1 is different from the electric field intensity generated by the auxiliary pixel electrode P2.

Further, the main pixel electrode P1 and the auxiliary pixel electrode P2 disposed at two opposite sides of the same scan line Sc along the second direction Y are electrically connected to the same data line Da via a switch element K.

In an embodiment, please refer to fig. 1, fig. 2, fig. 7 and fig. 8, wherein fig. 7 is a schematic diagram of a second cross-sectional structure of the array substrate shown in fig. 2 in a switch element area, and fig. 8 is a schematic diagram of a fourth cross-sectional structure of the array substrate shown in fig. 2 in a voltage dividing routing area.

The array substrate includes: a substrate 101, a first metal layer disposed on the substrate 101, a first insulating layer 102 disposed on the first metal layer, a second metal layer disposed on the first insulating layer 102, a second insulating layer 103 disposed on the second metal layer, and a pixel electrode layer disposed on the second insulating layer 103.

The first metal layer includes a data line Da; the second metal layer comprises a scanning line Sc, a partial pressure line S _ Com and a common line A _ Com; the pixel electrode layer includes a pixel electrode P including a main pixel electrode P1 and an auxiliary pixel electrode P2.

The common line a _ Com and the partial pressure line S _ Com are located on the second metal layer together, and an orthographic projection of the common line a _ Com on the substrate base plate 101 does not coincide with an orthographic projection of the partial pressure line S _ Com on the substrate base plate 101, so that a short circuit problem occurring when the common line and the partial pressure line are arranged in an overlapping manner is avoided, and the reliability of the array substrate device is improved.

Further, the common trace a _ Com and the partial pressure trace S _ Com are parallel, the common trace a _ Com and the partial pressure trace S _ Com both extend along a first direction X, and the plurality of common traces a _ Com and the plurality of partial pressure traces S _ Com are arranged along a second direction Y.

Further, the shape of an area defined by the orthographic projection of each common trace a _ Com on the substrate base plate 101 includes a square, and the shape of an area defined by the orthographic projection of each partial voltage trace S _ Com on the substrate base plate 101 also includes a square. It should be noted that the common trace a _ Com with a square structure and the pixel electrode P have more overlapping spaces, which is more favorable for forming a stable and uniform storage capacitor. The overlapping area between the voltage dividing trace S _ Com with the square structure and the main pixel electrode P1 is more, which is beneficial to forming more electrical connections with the main pixel electrode P1 and promoting the main pixel electrode P1 to generate stable and uniform electric field intensity.

Further, each of the common traces a _ Com includes: a first portion a1 and a second portion a2 extending in the first direction X and aligned in the second direction Y, and a plurality of third portions A3 extending in the second direction Y and electrically connecting the first portion a1 and the second portion a 2.

Each partial pressure wire S _ Com comprises: a fourth portion S1 and a fifth portion S2 extending in the first direction X and arranged in the second direction Y, and a plurality of sixth portions S3 extending in the second direction Y and electrically connecting the fourth portion S1 and the fifth portion S2.

The scanning lines Sc extend along the first direction X, and a plurality of the scanning lines Sc are arranged along the second direction Y; the data lines Da extend along the second direction Y, and a plurality of the data lines Da are arranged along the first direction X. Each grid region defined by the intersection of the scan lines Sc and the data lines Da corresponds to a pixel region, and each pixel region is provided with one main pixel electrode P1 and one auxiliary pixel electrode P2.

Further, the partial pressure trace S _ Com, the common trace a _ Com, and the scan line Sc are all located on the second metal layer, and an orthographic projection of the common trace a _ Com on the substrate base plate 101 does not coincide with an orthographic projection of the scan line Sc on the substrate base plate 101; the orthographic projection of the partial voltage trace S _ Com on the substrate 101 does not coincide with the orthographic projection of the scan line Sc on the substrate 101.

A common line A _ Com and a partial voltage line S _ Com are arranged between two adjacent scanning lines Sc; wherein, the orthographic projection of the main pixel electrode P1 on the substrate base plate 101 at least partially coincides with the orthographic projection of the partial voltage trace S _ Com on the substrate base plate 101, and the orthographic projection of the auxiliary pixel electrode P2 on the substrate base plate 101 at least partially coincides with the orthographic projection of the trace common a _ Com on the substrate base plate 101.

Further, the voltage dividing trace S _ Com is electrically connected to the main pixel electrode P1, and the voltage dividing trace S _ Com is used for reducing the voltage of the main pixel electrode P1, so that the electric field intensity generated by the main pixel electrode P1 is different from the electric field intensity generated by the auxiliary pixel electrode P2.

Further, the main pixel electrode P1 and the auxiliary pixel electrode P2 disposed at two opposite sides of the same scan line Sc along the second direction Y are electrically connected to the same data line Da via a switch element K.

The switching element K may be a thin film transistor device. Specifically, the switching element K includes a channel C, a source S, a drain D, and a gate G; the source S and the drain D are disposed on the first metal layer, the gate G is disposed on the second metal layer, the channel C is disposed on the substrate 101, and the source S and the drain D are respectively and correspondingly connected to two opposite ends of the channel C. The gate G is electrically connected to the scan line Sc, the source S is electrically connected to the data line Da, and the drain D is electrically connected to the pixel electrode P.

To sum up, the array substrate that this application embodiment provided includes the substrate base plate, sets up first metal layer on the substrate base plate, sets up first insulating layer on first metal layer, sets up second metal layer on first insulating layer, sets up the second insulating layer on the second metal layer and sets up the pixel electrode layer on the second insulating layer, the array substrate still includes many public wirings and many partial pressure and walks the line, public wiring sets up first metal layer or the second metal layer, the partial pressure is walked the line and is set up first metal layer or the second metal layer, public wiring is in orthographic projection on the substrate base plate with the partial pressure is walked the line and is in orthographic projection on the substrate base plate does not have the coincidence. The orthographic projection of the public wiring on the substrate base plate and the orthographic projection of the partial pressure wiring on the substrate base plate are set to be free of coincidence, so that the public wiring and the partial pressure wiring are staggered with each other along the thickness direction of the array base plate, and the risk of short circuit between the public wiring and the partial pressure wiring is reduced.

Referring to fig. 9, the display panel includes an array substrate 10, an opposite substrate 30 disposed opposite to the array substrate 10, and a liquid crystal 20 disposed between the array substrate 10 and the opposite substrate 30, where the array substrate 10 is any one of the array substrates provided in the embodiments of the present application.

The embodiment of the application also provides a display device comprising the display panel, and the display device can be a computer display, a television, a notebook computer, a mobile phone, a navigator and other devices with a display function.

It should be noted that, although the present application has been described with reference to specific examples, the above-mentioned examples are not intended to limit the present application, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, so that the scope of the present application shall be limited by the appended claims.