1. An apparatus, comprising:

an array of bit cells accessible via a word line and a bit line including an unselected bit line and a selected bit line, wherein each bit cell in the array of bit cells is selectable via a selected word line of the word line and the selected bit line of the bit line; and

a precharge circuit configured to selectively precharge the unselected bit lines and the selected bit line prior to arrival of a word line signal on the selected word line.

2. The apparatus of claim 1, wherein the array of bit cells is arranged in columns and rows, and wherein the columns comprise selected columns having the selected bit lines, and wherein the columns comprise unselected columns having the unselected bit lines.

3. The apparatus of claim 1, wherein the precharge circuit is configured to selectively precharge the unselected bit lines and the selected bit line at different times during the same clock cycle before arrival of the word line signal on the selected word line.

4. The apparatus of claim 1, wherein the selected bit line corresponds to a write bit line that is discharged when the unselected bit lines are precharged by the precharge circuit.

5. The apparatus of claim 4, wherein discharging the selected bit line when the unselected bit lines are precharged improves write time by increasing a speed of write operations to selected bit cells in the array of bit cells.

6. The apparatus of claim 4, wherein discharging the selected bit lines and precharging the unselected bit lines are accomplished in parallel during the same clock cycle.

7. The apparatus of claim 1, wherein the pre-charge circuit is configured to pre-charge the selected bit line with a first pre-charge signal, and wherein the pre-charge circuit is configured to pre-charge the unselected bit lines with a second pre-charge signal.

8. A memory circuit, comprising:

an array of memory cells arranged in columns and rows, wherein the columns include selected columns and unselected columns, wherein the selected columns include selected memory cells that can be selected via a selected word line and a selected bit line, and wherein the unselected columns include unselected memory cells coupled to unselected bit lines; and

a precharge circuit that selectively precharges the selected bit line and the unselected bit lines prior to arrival of a word line signal on the selected word line, wherein:

the precharge circuit is configured to precharge the selected bit line in the selected column with a first precharge signal, and

the precharge circuit is configured to precharge the unselected bit lines in the unselected columns with a second precharge signal.

9. The circuit of claim 8, wherein the precharge circuit is configured to selectively precharge the selected bit line and the unselected bit lines at different times during the same clock cycle before the arrival of the word line signal on the selected word line.

10. The circuit of claim 8, wherein the selected bit line corresponds to a write bit line that is discharged when the unselected bit lines are precharged by the precharge circuit.

11. The circuit of claim 10, wherein discharging the selected bit line when the unselected bit lines are precharged improves write time by increasing the speed of write operations to selected memory cells in the array of memory cells.

12. The circuit of claim 10, wherein discharging the selected bit lines and precharging the unselected bit lines are accomplished in parallel during the same clock cycle.

13. The circuit of claim 8, wherein the first pre-charge signal applied to the selected column is different than the second pre-charge signal applied to the unselected columns.

14. A method, comprising:

providing an array of bit cells accessible via word lines and bit lines, wherein each bit cell in the array of bit cells is selectable via a selected one of the word lines and a selected one of the bit lines, and wherein the bit lines include unselected bit lines; and

selectively precharging the selected bit line and the unselected bit lines before a word line signal on the selected word line arrives.

15. The method of claim 14, wherein the array of bit cells is arranged in columns, and wherein the columns comprise selected columns having the selected bit lines, and wherein the columns comprise unselected columns having the unselected bit lines.

16. The method of claim 14, wherein the selected bit line and the unselected bit lines are precharged at different times during the same clock cycle before the arrival of the word line signal on the selected word line.

17. The method of claim 14, wherein the selected bit line corresponds to a write bit line that is discharged when the unselected bit lines are precharged.

18. The method of claim 17, wherein discharging the selected bit line when the unselected bit lines are precharged improves write time by increasing the speed of write operations to selected bit cells in the array of bit cells.

19. The method of claim 17, wherein discharging the selected bit lines and precharging the unselected bit lines are accomplished in parallel during the same clock cycle.

20. The method of claim 14, wherein the selected bit line is precharged with a first precharge signal, and wherein the unselected bit lines are precharged with a second precharge signal different from the first bit line signal.

Background

This section is intended to provide information relevant to understanding the various techniques described herein. As the title of this section implies, this is a discussion of related art and should in no way imply that it is prior art. In general, the related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be taken in this sense and not as any admission of prior art.

In conventional computing architectures, some dual port memory designs utilize 1 reads and 1 writes (1R1W) that can be implemented with 8-transistor (8T) bit cells (e.g., in the RF2 design) or with 6-transistor (6T) bit cells (e.g., in the pseudo 2P design). RF2(8T) designs typically provide faster performance at significantly poorer densities, while pseudo 2P designs typically provide high densities at the expense of lower frequencies. Additionally, in some cases, the RF2 design may allow read and write operations to occur simultaneously, while the dummy 2P design (RA2P) may operate with sequential cycles (e.g., an internal read cycle followed by a write cycle). For the RA2P design, the separation time may be kept between two GTP clock pulses (i.e., 2 global timing pulses) to meet internal settings and some critical margins. Thus, the final cycle time is the "read + split + write" time that affects performance, and unfortunately, for positive timing requirements in a networking architecture, the negative impact on performance is a limiting factor. Therefore, there is a need to improve internal setup timing in memory designs.

Drawings

Specific implementations of various techniques are described herein with reference to the accompanying drawings. It should be understood, however, that the drawings illustrate only various implementations described herein and are not intended to limit embodiments of the various technologies described herein.

FIG. 1 illustrates a diagram of a memory circuit in accordance with various implementations described herein.

Fig. 2 illustrates a diagram of switching waveforms in accordance with various implementations described herein.

Fig. 3 illustrates a diagram of another switching waveform in accordance with various implementations described herein.

Fig. 4 illustrates a truth table diagram for the input-output (IO) signals of a 2-input multiplexer (Mux _2) according to various implementations described herein.

FIG. 5 illustrates a diagram of a method for bit line precharging in accordance with various implementations described herein.

6A-6B illustrate diagrams of bit line precharge circuits according to various implementations described herein.

Fig. 7A-7C illustrate various other diagrams of bit line precharge circuits according to various implementations described herein.

Detailed Description

Various implementations described herein refer to bit line precharge schemes and techniques. For example, the various schemes and techniques described herein may provide an ultra-fast high-density multi-port memory design with 1 read and 1 write (1R1W), such as a 2-port (1R1W) memory design.

To overcome the drawbacks of conventional memory designs, the various schemes and techniques described herein are configured to improve timing by effectively utilizing the separation time and using write control signals that do not need to be re-mixed with the clock. The various schemes and techniques described herein operate to ensure that write data is set on the bit lines before the write word line arrives, thereby making writes much faster than single port designs, which may be limited by the bit line pull down slope. The various schemes and techniques described herein utilize a novel modification that allows the same cell to be used for both single port and pseudo-dual (1R/1W) memory designs.

In some implementations, various aspects and techniques described herein provide a bit line precharge circuit that improves write time by allowing a write bit line to pull down while other bit lines are precharged. The bit line precharge circuits described herein do not need to wait for the second GTP clock signal to arrive, and the bit line precharge circuits described herein also use the port B column address/GWEN directly to generate the write select signals (the YW and WCLK signals) just after the first GTP clock reset. Additionally, as described herein, the word line is not changed and the word line will appear after the second GTP clock. Some modifications mean that the GTP clock is used for YW/WCLK generation in a single port design, while the global write enable signal (GWEN) will be used for a pseudo 2 port (RA2P) design. In some cases, even when there may be some contention margin between the Column Address (CA) signals when the YW signal is generated, it does not affect the function because the word line remains off. Furthermore, during the "split time" between GTP clock pulses, where the pre-charging of unselected bit lines and the discharging of selected bit lines occur in parallel, the bit lines may be pulled low before the write word line signal arrives, which provides significant performance gain.

Various implementations of bit line precharge schemes and techniques will be described in detail herein with reference to fig. 1-7C.

FIG. 1 illustrates a schematic diagram of a memory circuit 100 in accordance with various implementations described herein.

In various implementations, the memory circuit 100 may be implemented as a system or device having various Integrated Circuit (IC) components arranged and coupled together as an assembly or combination of parts that provide a physical circuit design and related structure. In some cases, methods of designing, providing, and constructing the memory circuit 100 as an integrated system or apparatus may involve the use of various IC circuit components described herein in order to thereby implement various bit line precharge schemes and techniques associated therewith. The memory circuit 100 may be integrated with computing circuitry and related components on a single chip, and the memory circuit 100 may be implemented in an embedded system for electronic, mobile, and internet of things (IoT) applications, including sensor nodes.

As shown in FIG. 1, the memory circuit 100 may include one or more bit cell arrays 104A, 104B of Bit Cells (BC) accessible via one or more Word Lines (WL) and bit lines (BL/NBL), including unselected bit lines and selected bit lines. In some cases, each Bit Cell (BC) in the bit cell arrays 104A, 104B can be selected via a selected word line of the Word Lines (WL) and a selected bit line of the bit lines (BL/NBL). Additionally, each Bit Cell (BC) in the bit cell arrays 104A, 104B may be arranged in columns and rows, and a column may comprise a selected column having a selected bit line and a column may comprise an unselected column having an unselected bit line.

The memory circuit 100 may include a number (N) of input-output (IO) circuit (IO _0, IO _1,. -, IO _ N) columns coupled to a Bit Cell (BC) column in the bit cell arrays 104A, 104B. In some cases, each IO circuit block (IO _0, IO _1,. eta., IO _ N) may include a precharge circuit configured to selectively precharge unselected and selected bit lines prior to arrival of a word line signal on a selected Word Line (WL). The precharge circuit may be configured to selectively precharge the unselected and selected bit lines at different times during the same clock cycle before arrival of a word line signal on a selected Word Line (WL). In some cases, each IO circuit block (IO _0, IO _1,... and IO _ N) may be configured to provide a corresponding output data signal (Q0, Q1,... and QN) as an output from each column of bitcell arrays 104A, 104B.

In some implementations, the selected bit line may correspond to a Write Bit Line (WBL) that is discharged when the unselected bit lines are precharged by the precharge circuit. In some cases, discharging selected bit lines while precharging unselected bit lines may improve write time by increasing the speed of write operations to selected bit cells in the bit cell arrays 104A, 104B. Additionally, in some cases, discharging selected bit lines and precharging unselected bit lines may be accomplished in parallel during the same clock cycle. In addition, the pre-charge circuit may be configured to pre-charge the selected bit lines with a first pre-charge signal, and the pre-charge circuit may be configured to pre-charge the unselected bit lines with a second pre-charge signal different from the first pre-charge signal. The precharge circuit, along with various aspects and features associated therewith, will be described in greater detail herein.

In some implementations, the memory circuit 102 can include a multiple-input multiplexer (Mux)124 having a first input port (port a) for receiving a first input data signal (inA) and a second input port (port B) for receiving a second input data signal (inB). Mux 124 may be configured as a multiplexer with port B input latches. Mux 124 may be configured to provide an output signal (Mux _ Out) based on a multiplexer select signal (portAB _ Mux _ sel), where the output signal (Mux _ Out) is either a port a signal or a port B signal based on the portAB _ Mux _ sel signal. In some cases, the output signal (Mux _ Out) is provided to a clock signal generation circuit 120 (which may be part of the control logic block (Ctrl)), the clock signal generation circuit 120 providing data signals to Word Line Drivers (WLD) in the row decoder block (rowdec). A Word Line Driver (WLD) receives a data signal from the clock signal generation circuit 120 and provides a word line signal to one or more rows of Bit Cells (BC) in the bit cell arrays 104A, 104B. In addition, in some cases, Mux 124 may provide an output signal (Mux _ Out) to one or more IO circuit blocks (IO _0, IO _1,.. and IO _ N), where the output signal (Mux _ Out) may be used as one or more of a precharge signal (prech <0:1>), a read column select signal (col _ sel <0:1> read), a write column select signal (col _ sel <0:1> write), an IO write column select signal (IO _ col _ sel <0:1> write), and an IO clock signal (IO _ clk).

In some implementations, as described herein, the bit line precharge circuit may be configured to selectively precharge unselected and selected bit lines for improved performance and functionality, such that the unselected bit lines and the selected bit line (which should not discharge) are precharged prior to arrival of the Word Line (WL). Various aspects and features associated with bit line precharge circuits and techniques related thereto are described in greater detail herein.

FIG. 2 illustrates a timing diagram 200 of a switching waveform 200 associated with a precharge circuit according to various implementations described herein.

As shown in fig. 2, the switching waveform 202 may include a READ pulse (READ) associated with a READ period 214 during a READ operation and a WRITE pulse (WRITE) associated with a WRITE period 214 during a WRITE operation. The switching waveform 2020 also illustrates the precharge and discharge operations (PRECH & DISCH) that occur during the precharge and discharge period 218. In some cases, the precharging and discharging may occur during the same time between the read cycle 212 and the write cycle 214. As described below, the precharge circuit may be configured to precharge a selected bit line in a selected column with a first precharge signal, and the precharge circuit may be further configured to precharge an unselected bit line in an unselected column with a second precharge signal different from the first precharge signal.

FIG. 3 illustrates a timing diagram 302 of a switching waveform 300 associated with a precharge circuit, according to various implementations described herein.

As shown in fig. 3, switching waveform 302 may include an internal clock signal (CLK int) that provides clock pulses to the precharge circuitry. The rising edge of the clock pulse (CLK _ int) triggers the first word line pulse signal (WL) on the selected word line, and in some cases, the first word line pulse signal (WL) may be configured to trigger the precharging and/or discharging of the unselected bit lines (PRECH <0>) and the selected bit line (PRECH <1 >). For example, as shown in FIG. 3, the PRECH <0> signal can be turned off during the first and second pulses, and between these two pulses, the precharge of the unselected bitlines can be achieved with the deactivation PRECH <0> signal. Additionally, in some cases, as shown in FIG. 3, the PRECH <1> signal may be turned off during the active pulse period, and precharging of the selected bit lines may also be accomplished with the active PRECH <1> signal. In some cases, the first column select signal (COL _ SEL <0>) for the unselected bit lines may be turned off, and the other second column select signal (COL _ SEL <1>) for the selected bit line may also be turned on (activated) with an active pulse during the precharge of the unselected bit lines. In addition, in this case, the input-output clock signal (IO _ CLK) may be simultaneously turned on (activated) with the second column selection signal (COL _ SEL <1>) during the precharge of the unselected bit lines.

In some implementations, the Global Write Enable (GWEN) signal toggles when the first clock (CLK _ int) is reset. Since the GWEN switch is a clock signal, the CLK _ int signal can be used to generate the write select signal (YW/WCLK) instead of the GTP signal, which can be used to control the bit line precharge signal. For unselected columns, the precharge is turned on, and for selected columns, the precharge is disabled. Based on the data to be written, the Bit Line (BL) or its complementary bit line (NBL) is pulled low. In this case, the column select signal and/or data information may be used to precharge the NBL if BL is pulled low or vice versa. Additional aspects, features, and behavior associated with bit line precharge schemes and techniques, and circuits related thereto, are described in greater detail herein.

Fig. 4 illustrates a diagram 400 of a truth table 402 for the IO signal of the reference 2-input multiplexer (Mux _2) according to a specific implementation described herein.

As shown in FIG. 4, truth table 402 may refer to the selected column along with the associated precharge signal state. For example, during a first timing cycle, selecting the first column (COL _ SEL <0>) may refer to the precharge signal state of the first precharge signal (PRECH <0>) being off, and during the same first timing cycle, selecting the second column (COL _ SEL <1>) may refer to the precharge signal state of the second precharge signal (PRECH <1>) being on. Otherwise, in another case, during a second timing period, the selected first column (COL _ SEL <0>) may refer to the precharge signal state of the first precharge signal (PRECH <0>) being turned on, and during the same second timing period, the selected second column (COL _ SEL <1>) may be turned off with the precharge signal state of the second precharge signal (PRECH <1 >).

FIG. 5 illustrates a diagram 500 of a method for providing a bit line precharge technique according to various implementations described herein.

It should be understood that even though the method 500 indicates a particular order of execution of the operations, in some cases, various particular portions of the operations may be executed in a different order and on a different system. In other cases, additional operations and/or steps may be added to and/or omitted from method 500. Additionally, the method 500 may be implemented in hardware and/or software. If implemented in hardware, the method 500 may be implemented with various components and/or circuitry, as described herein with reference to fig. 1-4 and 6A-7C. Additionally, if implemented in software, the method 500 may be implemented as a program and/or software instruction process configured to provide a bit line precharge technique, as described herein. Additionally, if implemented in software, the instructions associated with implementing the method 500 may be stored in a memory and/or database. For example, a computer or various other types of computing devices having a processor and memory may be configured to perform the method 500.

In various implementations, method 500 may refer to a method of designing, providing, constructing and/or fabricating a bit line precharge circuit as an integrated circuit, device and/or circuit, which may involve the use of various IC circuit components described herein to thereby implement the bit line precharge schemes and techniques associated therewith. The bit line precharge circuit may be integrated with the computational circuitry and various related components on a single chip, and may also be implemented in various embedded systems for various electronic, mobile, and internet of things (IoT) applications, including sensor nodes.

At block 510, the method 500 may provide an array of bit cells accessible via word lines and bit lines. In some cases, each bit cell in the array of bit cells is selectable via a selected one of the word lines and a selected one of the bit lines, and the bit lines may include unselected bit lines. In some cases, the array of bit cells may be arranged in columns, wherein a column may include a selected column having a selected bit line, and wherein a column may include an unselected column having an unselected bit line.

At block 520, the method 500 may selectively precharge the selected bit line with a first precharge signal before the arrival of the word line signal on the selected word line. Additionally, at block 530, the method 500 may selectively precharge the unselected bit lines with a second precharge signal (which may be different from the first precharge signal) before the wordline signal on the selected wordline arrives. In some cases, the selected bit lines and unselected bit lines may be precharged at different times during the same clock cycle before the arrival of the word line signal on the selected word line. In addition, in other cases, the selected bit line may correspond to a write bit line that is discharged when the unselected bit lines are precharged by the precharge circuit.

In some implementations, discharging the selected bit lines while precharging the unselected bit lines can improve write time by increasing the speed of write operations to selected bit cells in the bit cell array. Additionally, in some cases, discharging the selected bit lines and precharging the unselected bit lines are accomplished in parallel during the same clock cycle. In addition, the selected bit lines may be precharged with a first precharge signal, and in addition, the unselected bit lines may be precharged with a second precharge signal different from the first bit line signal.

In various implementations, the schematic diagrams of the bit line precharge circuits shown in fig. 6A-6B and 7A-7C provide some example implementations of logic that may be used to implement the various aspects and techniques described herein. However, there are other ways to implement similar logic, and thus, the implementations shown in fig. 6A-6B and 7A-7C may be implemented in various other ways, and should not be limited to the schematic shown in these designs of fig. 6A-6B and 7A-7C.

6A-6B illustrate various schematic diagrams of bit line precharge circuits 602A, 602B according to various implementations described herein. Specifically, FIG. 6A shows a diagram 600A of a bit line precharge circuit 602A, and FIG. 6B shows a diagram 600B of a bit line precharge circuit 602B. In some implementations, the bit line precharge circuits 602A, 602B may be formed as part of a memory circuit, such as the memory circuit 100 of fig. 1 having one or more arrays of bit cells. Additionally, in some cases, the bit line precharge circuits 602A, 602B of fig. 6A-6B may refer to a multi-column bit line precharge circuit for use with one or more bit cell arrays.

In various implementations, the bit line precharge circuits 602A, 602B may be implemented as a system or device having various Integrated Circuit (IC) components arranged and coupled together as an assembly or combination of parts that provide a physical circuit layout design and related structures. In some cases, methods of designing, providing, and constructing the bit line precharge circuits 602A, 602B as an integrated system or apparatus may involve the use of various IC circuit components described herein in order to thereby implement the various bit line precharge schemes and techniques associated therewith. The bit line precharge circuits 602A, 602B may be integrated with computing circuitry and related components on a single chip, and the bit line precharge circuits 602A, 602B may be implemented in various embedded systems for electronic, mobile, and internet of things (IoT) applications, including sensor nodes.

As shown in FIG. 6A, the bit line precharge circuit 602A may be coupled to bit lines (BL0, NBL0), and may also be coupled to an array of memory cells (or bit cells) arranged in columns and rows via bit lines (BL0, NBL 0). For example, the array of memory cells (or bit cells) and bit lines (BL0, NBL0) may correspond to bit cell arrays 104A, 104B and bit lines (BL, NBL) in FIG. 1. Referring to fig. 6A, a bit line precharge circuit 602A may refer to an unselected column (PCH _0) in the bit cell array, where the unselected column may include unselected memory cells (or bit cells) coupled to the unselected bit lines.

In some implementations, as shown in fig. 6A, the bit line precharge circuit 602A may include a plurality of transistors (e.g., T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10) arranged and configured to precharge one or more bit lines (BL0, NBL 0). For example, the transistor (T0) may be coupled between a voltage source (VDD) and the transistor (T2), and the transistor (T0) may be activated with the first header signal (HDR _ N0). Additionally, the transistor (T1) may be coupled between the voltage source (VDD) and the transistor (T3), and the transistor (T1) may be activated with the second header signal (HDR _ N1). The transistor (T2) may be coupled between the transistor (T0) and the transistor (T5), and the transistor (T2) may be activated with a first precharge signal (PRECH _ N0), which may refer to a first column select signal of the unselected column (PCH _ 0). In addition, the transistor (T3) may be coupled between the transistor (T1) and the transistor (T6), and the transistor (T1) may also be activated by a first precharge signal (PRECH _ N0), which may refer to a first column select signal of the unselected column (PCH _ 0). In addition, in some cases, a transistor (T4) may be coupled between the output terminals of the transistors (T2, T3), and in this case, the transistor (T4) may also be activated with the first precharge signal (PRECH _ N0).

Furthermore, in some implementations, as shown in fig. 6A, the transistor (T5) may be coupled between the transistor (T2) and the Read Data Line (RDL), and the transistor (T5) may be activated with the read select signal (YRSN 0). In addition, the transistor (T6) may be coupled between the transistor (T3) and another Read Data Line (RDLN) that is a complement of the RDL, and the transistor (T6) may be activated with a read select signal (YRSN 0). The transistor (T7) may be coupled in parallel with the transistor (T9) between the first bit line (BL0) at node (n0) and the Write Data Line (WDL), where the first bit line (BL0) at node (n0) is also coupled to the transistors (T2, T4, T5). In this case, the transistor (T7) may be activated with the write select signal (nYWS0), and the transistor (T9) may also be activated with another write select signal (YWS0) that is the complement of nYWS 0. Additionally, a transistor (T8) may be coupled in parallel with transistor (T10) between second bit line (NBL0) at node (n1) and another Write Data Line (WDLN), where second bit line (NBL0) at node (n1) is also coupled to transistors (T3, T4, T6) and write data line WDLN is the complement of WDL. In addition, the transistor (T8) may be activated with the write select signal (nYWS0), and the transistor (T10) may also be activated with the write select signal (YWS 0).

In some implementations, referring to the first column select signal of the unselected column (PCH _0), when activated, the transistor (T8) may provide the first write signal (nYW0) to the second bit line (NBL0) via node (n 1). Otherwise, in some other implementations, when activated, the transistor (T10) may provide the second write signal (YW0) to the second bit line (NBL0) via node (n 1). In this case, the second write signal (YW0) is complementary to the first write signal (nYW 0).

As shown in FIG. 6B, the bit line precharge circuit 602B may be coupled to bit lines (BL0, NBL0), and may also be coupled to an array of memory cells (or bit cells) arranged in columns and rows via bit lines (BL0, NBL 0). For example, the array of memory cells (or bit cells) and bit lines (BL0, NBL0) may correspond to bit cell arrays 104A, 104B and bit lines (BL, NBL) in FIG. 1. Referring to fig. 6B, a bit line precharge circuit 602B may refer to a selected column (PCH _1) in the bit cell array, where the selected column may include a selected memory cell (or bit cell) coupled to a selected bit line. In this case, the selected column (PCH _1) may include a selected memory cell (or bit cell) that can be selected via a selected Word Line (WL) and a selected bit line (BL0 or NBL 0).

In some implementations, as shown in fig. 6B, the bit line precharge circuit 602B may include a plurality of transistors (e.g., T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10) arranged and configured to precharge one or more bit lines (BL0, NBL0) in the manner shown by the bit line precharge circuit 602A of fig. 6A. However, in some cases, as shown with reference to fig. 6B, a second column select signal for the selected column (PCH _1) may be used. In this case, the transistors (T2, T3, T4) may be activated with a second precharge signal (PRECH _ N1), which may refer to a second column selection signal of the selected column (PCH _ 1). In addition, referring to the second column selection signal of the selected column (PCH _1), when activated, the transistor (T8) may provide a third write signal (nYW1) to the second bit line (NBL0) via node (n 1). Otherwise, in some other cases, when activated, the transistor (T10) may provide the fourth write signal (YW1) to the second bit line (NBL0) via node (n 1). In this case, the fourth write signal (YW1) is complementary to the third write signal (nYW 1).

In some implementations, referring to fig. 6A-6B, the precharge circuits 602A, 602B may be configured to selectively precharge selected bit lines and unselected bit lines prior to arrival of a word line signal on a selected Word Line (WL). Referring to fig. 6A, precharge circuit 602A may be configured to precharge unselected bitlines in unselected columns (PCH _0) with a precharge signal (PRECH _ N0). Referring to fig. 6B, precharge circuitry 602B may be configured to precharge a selected bit line (PCH _1) in a selected column with a precharge signal (PRECH _ N1). Additionally, the precharge circuits 602A, 602B may be configured to selectively precharge selected and unselected bit lines at different times during the same clock cycle before arrival of a word line signal on a selected Word Line (WL). The selected bit lines may correspond to Write Bit Lines (WBLs) that are discharged when unselected bit lines are precharged by precharge circuits 602A, 602B. In some cases, discharging the selected bit lines while precharging the unselected bit lines may improve write time, for example, by increasing the speed of write operations to selected bit cells in the bit cell array. In addition, discharging the selected bitlines and precharging the unselected bitlines can be accomplished in parallel during the same clock cycle, and the first precharge signal (PRECH _0) applied to the unselected columns (PCH _0) can be different from the second precharge signal (PRECH _1) applied to the selected columns (PCH _ 1).

7A-7C illustrate various schematic diagrams of bit line precharge circuits 702A, 702B, 702C according to various implementations described herein. Specifically, FIG. 7A shows a diagram 700A of a bit line precharge circuit 702A, FIG. 7B shows a diagram 700B of a bit line precharge circuit 702B, and FIG. 7C shows a diagram 700C of a bit line precharge circuit 702C.

In some implementations, the bit line precharge circuits 702A, 702B, 702C may be implemented as a system or device having various Integrated Circuit (IC) components arranged and coupled together as an assembly or combination of parts that provide a physical circuit layout design and related structures. In some cases, methods of designing, providing, and constructing the bit line precharge circuits 702A, 702B, 702C as an integrated system or apparatus may involve the use of various IC circuit components described herein in order to thereby implement the various bit line precharge schemes and techniques associated therewith. The bit line precharge circuits 702A, 702B, 702C may be integrated with computing circuitry and related components on a single chip, and the bit line precharge circuits 702A, 702B, 702C may be implemented in embedded systems for electronic, mobile, and internet of things (IoT) applications.

As shown in FIG. 7A, the bit line precharge circuit 702A may be coupled to bit lines (BL0, NBL0), and may also be coupled to an array of memory cells (or bit cells) arranged in columns and rows via bit lines (BL0, NBL 0). For example, the array of memory cells (or bit cells) and bit lines (BL0, NBL0) may correspond to bit cell arrays 104A, 104B and bit lines (BL, NBL) in FIG. 1. Referring to fig. 7A, a bit line precharge circuit 702A may refer to an unselected column (PCH _0) or a selected column (PCH _1) in an array of bit cells, where the selected column may include a selected memory cell (or bit cell) coupled to a selected bit line. In some cases, the unselected column (PCH _0) may include unselected memory cells (or bit cells). In other cases, the selected column (PCH _1) may include a selected memory cell (or bit cell) that can be selected via a selected Word Line (WL) and a selected bit line (BL0 or NBL 0).

In some implementations, as shown in fig. 7A, the bit line precharge circuit 702A may include transistors (e.g., T0, T1, T2, T3, T4, T5, T6, T9, T10) arranged and configured to precharge one or more bit lines (BL0, NBL0) in a manner as shown in the bit line precharge circuit 702A of fig. 7A. In various cases, two column select signals (PCH _0, PCH _1) may be used. In this case, Transistor (TP) may be activated with a precharge signal (PRECH _ N1), which refers to the column select signal for the selected column (PCH _ 1). In addition, the transistors (T2, T3, T4) may be activated by a precharge signal (PRECH _ N0), which is a column select signal for the unselected column (PCH _ 0). With reference to the column selection signals (PCH _0, PCH _1), when activated, the transistor (T10) may provide a write signal (YW0) to the second bit line (NBL0) via node (n 1).

As shown in FIG. 7B, the bit line precharge circuit 702B may be coupled to bit lines (BL0, NBL0), and may also be coupled to an array of memory cells (or bit cells) arranged in columns and rows via bit lines (BL0, NBL 0). For example, the array of memory cells (or bit cells) and bit lines (BL0, NBL0) may correspond to bit cell arrays 104A, 104B and bit lines (BL, NBL) in FIG. 1. Referring to fig. 7B, a bit line precharge circuit 702B may refer to a column signal (PCH) in an array of bit cells, where an unselected/selected column may refer to an unselected memory cell or a selected memory cell (or bit cell) coupled to a selected bit line. In addition, in some cases, the bit line precharge circuit 702B may utilize the DATA signals (DATA, nDATA) as internal activation signals.

In some implementations, as shown in fig. 7B, the bit line precharge circuit 702B may include a plurality of transistors (e.g., T0, T1, T2, T3, T4A, T4B, T5, T6, T9, T10) arranged and configured to precharge one or more bit lines (BL0, NBL0), as shown by the bit line precharge circuit 702B. In some cases, a column signal (PCH) may be used, and in this case, the transistors (T0, T1) may be activated using the column signal (PCH). In addition, the transistors (T2, T3) may be activated with a write select signal (YW0), and the transistors (T4A, T4B) may be activated with DATA signals (nDATA, DATA). In some cases, when activated, the transistor (T10) may provide a write signal (YW0) to the second bit line (NBL0) via node (n 1).

As shown in FIG. 7C, the bit line precharge circuit 702C may be coupled to bit lines (BL0, NBL0), and may also be coupled to an array of memory cells (or bit cells) arranged in columns and rows via bit lines (BL0, NBL 0). For example, the array of memory cells (or bit cells) and bit lines (BL0, NBL0) may correspond to bit cell arrays 104A, 104B and bit lines (BL, NBL) in FIG. 1. Referring to fig. 7C, a bit line precharge circuit 702C may refer to a column signal (PCH) in an array of bit cells, where an unselected/selected column may refer to an unselected memory cell or a selected memory cell (or bit cell) coupled to a selected bit line. In addition, in some cases, the bit line precharge circuit 702C may utilize the DATA signals (DATA, nDATA) as internal activation signals.

In some implementations, as shown in fig. 7C, the bit line precharge circuit 702C may include a plurality of transistors (e.g., T0, T1, T2, T3, T4A, T4B, T5, T6, T9, T10) arranged and configured to precharge one or more bit lines (BL0, NBL0), as shown by the bit line precharge circuit 702C. In some cases, a column signal (PCH) may be used, and in this case, the transistors (T0, T1) may be activated using the column signal (PCH). In addition, the transistors (T2, T3) may be activated with a write select signal (YW0), and the transistors (T4A, T4B) may be activated with DATA signals (nDATA, DATA) after inversion by corresponding inverters (I0, I1). In addition, when activated, the transistor (T10) may provide a write signal (YW0) to the second bit line (NBL0) via node (n 1).

It is intended that the claimed subject matter not be limited to the implementations and illustrations provided herein, but include modified forms of those implementations including portions of the implementations and combinations of elements of different implementations in accordance with the claims. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions should be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

Reference has been made in detail to various implementations, examples of which are illustrated in the accompanying drawings and drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the disclosure provided herein. However, the disclosure provided herein may be practiced without these specific details. In some other instances, well-known methods, procedures, components, circuits, and networks have not been described in detail so as not to unnecessarily obscure the details of the embodiments.

Various implementations of the apparatus are described herein. The apparatus may include an array of bit cells accessible via a word line and a bit line including an unselected bit line and a selected bit line. Each bit cell in the array of bit cells is selectable via a selected word line of the word lines and the selected bit line of the bit lines. The apparatus may include a precharge circuit configured to selectively precharge the unselected bit lines and the selected bit line prior to arrival of a word line signal on the selected word line.

Various implementations of memory circuitry are described herein. The memory circuit may include an array of memory cells arranged in columns and rows. The columns may include selected columns and unselected columns. The selected column may include a selected memory cell that is capable of being selected via a selected word line and a selected bit line. The unselected columns may include unselected memory cells coupled to unselected bit lines. The memory circuit may include a precharge circuit that selectively precharges selected bit lines and unselected bit lines prior to arrival of a word line signal on a selected word line. The precharge circuit may be configured to precharge a selected bit line in a selected column with a first precharge signal. The precharge circuit may be configured to precharge the unselected bit lines in the unselected columns with a second precharge signal.

Various implementations of the methods are described herein. The method may include providing an array of bit cells accessible via word lines and bit lines. Each bit cell in the array of bit cells is selectable via a selected one of the word lines and a selected one of the bit lines, and the bit lines may include unselected bit lines. The method may include selectively precharging selected bit lines and unselected bit lines before a word line signal on a selected word line arrives.

It will also be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element. The first and second elements are each an element, but they are not considered to be the same element.

The terminology used in the description of the disclosure provided herein is for the purpose of describing particular implementations and is not intended to be limiting of the disclosure provided herein. As used in the disclosure provided herein and the description of the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein, the term "and/or" refers to and encompasses any and all possible combinations of one or more of the associated listed items. The terms "comprises," "comprising," "includes" and/or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

As used herein, the term "if" may be interpreted to mean "when or" at. Similarly, the phrase "if it is determined." or "if [ the condition or event ] is detected" may be interpreted to mean "upon determining.. or" in response to determining. "or" upon detecting [ the condition or event ] or "in response to detecting [ the condition or event ]" depending on the context. The terms "upper" and "lower"; "upper" and "lower"; "upward" and "downward"; "below" and "above"; and other similar terms indicating relative positions above or below a given point or element may be used in conjunction with some implementations of the various techniques described herein.

While the foregoing is directed to implementations of the various techniques described herein, other and further implementations are contemplated in light of the disclosure herein, which may be determined by the appended claims.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.