1. A display device, comprising:

a plurality of first pixels connected to a first data line and a plurality of first scan lines;

a plurality of second pixels connected to the first data lines and a plurality of second scan lines;

a plurality of third pixels connected to a second data line and the first scan line or the second scan line; and

a scan driver including a plurality of stages supplying a plurality of scan signals to one of the first scan line and the second scan line.

2. The display device of claim 1, wherein the plurality of stages comprises:

a plurality of first stages sequentially supplying the scan signal to each of the plurality of first scan lines based on a first start signal; and

a plurality of second stages sequentially supplying the scan signal to each of the plurality of second scan lines based on a second start signal.

3. The display device of claim 2, wherein the first stage comprises:

a first-first stage outputting a first-first scan signal based on the first start signal; and

a second-first stage outputting a second-first scan signal based on the first-first scan signal.

4. The display device of claim 2, wherein the second stage comprises:

a first-second stage outputting first-second scan signals based on the second start signal; and

a second-second stage outputting a second-second scan signal based on the first-second scan signal.

5. The display device according to claim 2, further comprising:

a first test transistor supplying a first lighting voltage to the first data line based on a test gate signal; and

a second test transistor supplying a second lighting voltage to the second data line based on the test gate signal.

6. The display device according to claim 5, wherein the first and second light sources are arranged in a matrix,

wherein the second lighting voltage has a second voltage level that turns off the first pixel or the second pixel when the first lighting voltage has a first voltage level that turns on the first pixel or the second pixel.

7. The display device of claim 1, wherein the plurality of stages comprises:

a plurality of first stages sequentially supplying the scan signal to each of the plurality of first scan lines when a start signal is supplied during a first period; and

a plurality of second stages sequentially supplying the scan signal to each of the plurality of second scan lines when the start signal is supplied during a second period different from the first period.

8. The display device of claim 7, wherein the first stage comprises:

a first-first stage outputting a first-first scan signal when the start signal is supplied during the first period; and

a second-first stage outputting a second-first scan signal based on the first-first scan signal.

9. The display device of claim 7, wherein the second stage comprises:

a first-second stage outputting first-second scan signals when the start signal is supplied during the second period; and

a second-second stage outputting a second-second scan signal based on the first-second scan signal.

10. The display device according to claim 2 or 7,

the first pixel is connected to the second scan line and a third data line,

the second pixel is connected to the first scan line and the third data line, and

the third pixel is connected to a fourth data line and the first scan line or the second scan line.

11. The display device according to claim 10, further comprising:

a first test transistor supplying a first lighting voltage to the first data line based on a first test gate signal; and

a second test transistor supplying the first lighting voltage to the third data line based on a second test gate signal.

12. The display device according to claim 11, further comprising:

a third test transistor that supplies a third lighting voltage to the third data line based on the first test gate signal; and

a fourth test transistor that supplies the third lighting voltage to the first data line based on the second test gate signal.

13. The display device according to claim 12, wherein the first and second light sources are arranged in a matrix,

wherein the third lighting voltage has a second voltage level that turns off the first pixel or the second pixel when the first lighting voltage has a first voltage level that turns on the first pixel or the second pixel.

14. The display device according to claim 12, wherein the first and second light sources are arranged in a matrix,

wherein the first lighting voltage has a second voltage level that turns off the first pixel or the second pixel when the third lighting voltage has a first voltage level that turns on the first pixel or the second pixel.

15. The display device according to claim 12, further comprising:

a fifth test transistor supplying a second lighting voltage to the second data line based on a third test gate signal, an

A sixth test transistor that supplies the second lighting voltage to the fourth data line based on the third test gate signal.

Background

With the development of the information society, display devices for displaying images have been used in various fields. For example, such a display device is applied to various electronic devices such as a smart phone, a digital camera, a notebook computer, a navigator, and a smart television. The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, or a light emitting display device. Since a light emitting display device among flat panel display devices includes a light emitting element in which each of pixels in a display panel emits light by itself, the light emitting display device can display an image without using a backlight unit for supplying light to the display panel.

The display device generally includes: a display panel including data lines, scan lines, and pixels connected to the data lines and the scan lines; a data driver for supplying a data signal to the data lines; and a scan driver including a shift register for supplying a scan signal to the scan line.

Disclosure of Invention

In the display device, pixels emitting light of colors different from each other may be connected to the same data line. In such a display device, a lighting voltage may be applied to each of the pixels connected to the same data line to perform a lighting check on the pixels, and as the resolution of the display device increases, the charging rate of the data line may decrease.

An embodiment of the present invention will provide a display device in which a lighting voltage can be applied to each of a plurality of pixels that are connected to one data line and emit light of colors different from each other, and a decrease in the charging rate of the data line can be prevented to effectively check the lighting of each of the pixels.

According to an embodiment of the present disclosure, a display device includes: a plurality of first pixels connected to the first data lines and the plurality of first scan lines; a plurality of second pixels connected to the first data lines and the plurality of second scan lines; a plurality of third pixels connected to the second data line and the first scan line or the second scan line; and a scan driver including a plurality of stages supplying scan signals to one of the first scan lines and the second scan lines.

In an embodiment, the plurality of stages may include: a plurality of first stages sequentially supplying a scan signal to each of the plurality of first scan lines based on a first start signal; and a plurality of second stages sequentially supplying a scan signal to each of the plurality of second scan lines based on the second start signal.

In an embodiment, the first stage may comprise: a first-first stage outputting a first-first scan signal based on a first start signal; and a second-first stage outputting a second-first scan signal based on the first-first scan signal.

In an embodiment, the second stage may comprise: a first-second stage outputting first-second scan signals based on a second start signal; and a second-second stage outputting a second-second scan signal based on the first-second scan signal.

In an embodiment, the display device may further include: a first test transistor supplying a first lighting voltage to the first data line based on the test gate signal; and a second test transistor supplying a second lighting voltage to the second data line based on the test gate signal.

In an embodiment, when the first lighting voltage has a first voltage level to turn on the first pixel or the second pixel, the second lighting voltage may have a second voltage level to turn off the first pixel or the second pixel.

In an embodiment, the plurality of stages may include: a plurality of first stages sequentially supplying a scan signal to each of a plurality of first scan lines when a start signal is supplied during a first period; and a plurality of second stages sequentially supplying the scan signal to each of the plurality of second scan lines when the start signal is supplied during a second period different from the first period.

In an embodiment, the first stage may comprise: a first-first stage outputting a first-first scan signal when the start signal is supplied during a first period; and a second-first stage outputting a second-first scan signal based on the first-first scan signal.

In an embodiment, the second stage may comprise: a first-second stage outputting first-second scan signals when the start signal is supplied during a second period; and a second-second stage outputting a second-second scan signal based on the first-second scan signal.

In an embodiment, the first pixel may be connected to the second scan line and the third data line, the second pixel may be connected to the first scan line and the third data line, and the third pixel may be connected to the fourth data line and the first scan line or the second scan line.

In an embodiment, the display device may further include: a first test transistor supplying a first lighting voltage to the first data line based on the first test gate signal; and a second test transistor supplying the first lighting voltage to the third data line based on the second test gate signal.

In an embodiment, the display device may further include: a third test transistor supplying a third lighting voltage to the third data line based on the first test gate signal; and a fourth test transistor supplying a third lighting voltage to the first data line based on the second test gate signal.

In an embodiment, when the first lighting voltage has a first voltage level to turn on the first pixel or the second pixel, the third lighting voltage may have a second voltage level to turn off the first pixel or the second pixel.

In an embodiment, when the third lighting voltage has a first voltage level to turn on the first pixel or the second pixel, the first lighting voltage may have a second voltage level to turn off the first pixel or the second pixel.

In an embodiment, the display device may further include: a fifth test transistor supplying the second lighting voltage to the second data line based on the third test gate signal, and a sixth test transistor supplying the second lighting voltage to the fourth data line based on the third test gate signal.

In an embodiment, the plurality of first pixels may be connected to the second scan line and the third data line, the plurality of second pixels may be connected to the first scan line and the third data line, and the plurality of third pixels may be connected to the fourth data line and the first scan line or the second scan line.

In an embodiment, the display device may further include: a first test transistor supplying a first lighting voltage to the first data line based on the first test gate signal; and a second test transistor supplying the first lighting voltage to the third data line based on the second test gate signal.

In an embodiment, the display device may further include: a third test transistor supplying a third lighting voltage to the third data line based on the first test gate signal; and a fourth test transistor supplying a third lighting voltage to the first data line based on the second test gate signal.

In an embodiment, when the first lighting voltage has a first voltage level to turn on the first pixel or the second pixel, the third lighting voltage may have a second voltage level to turn off the first pixel or the second pixel.

In an embodiment, the display device may further include: a fifth test transistor supplying the second lighting voltage to the second data line based on the third test gate signal, and a sixth test transistor supplying the second lighting voltage to the fourth data line based on the third test gate signal.

Drawings

The above and other features of the present invention will become more apparent by describing in detail embodiments of the present invention with reference to the attached drawings in which:

fig. 1 is a perspective view of a display device according to an embodiment;

fig. 2 is a plan view of a display device according to an embodiment;

fig. 3 is a block diagram of a display device according to an embodiment;

fig. 4 is a circuit diagram illustrating a pixel of a display device according to an embodiment;

fig. 5 is a block diagram illustrating a scan driver of a display device according to an embodiment;

fig. 6 is a waveform diagram illustrating input/output signals of a scan driver in a display device according to an embodiment;

fig. 7 is a waveform diagram illustrating input/output signals of odd stages in the display apparatus of fig. 5;

fig. 8 is a diagram illustrating a process of supplying a lighting voltage in a display device according to an embodiment;

fig. 9 is a waveform diagram illustrating a lighting voltage and a test gate signal in the display device according to the embodiment;

fig. 10 is a diagram illustrating a result of a lighting inspection of a first pixel in the display device of fig. 9;

fig. 11 is a waveform diagram illustrating a lighting voltage and a test gate signal in a display device according to an alternative embodiment;

fig. 12 is a diagram illustrating a result of a lighting inspection of the second pixel in the display device of fig. 11;

fig. 13 is a waveform diagram illustrating input/output signals of even-numbered stages in the display device of fig. 5;

fig. 14 is a diagram illustrating a result of a lighting inspection of the second pixel in the display device of fig. 13;

fig. 15 is a diagram illustrating a result of a lighting inspection of a first pixel in the display device of fig. 13;

FIG. 16 is a block diagram illustrating a scan driver of a display device according to an alternative embodiment;

fig. 17 is a waveform diagram illustrating input/output signals of odd stages in the display device of fig. 16;

fig. 18 is a waveform diagram illustrating input/output signals of even-numbered stages in the display device of fig. 16;

FIG. 19 is a plan view of a display device according to an alternative embodiment;

fig. 20 is a diagram illustrating a process of supplying a lighting voltage in a display device according to an alternative embodiment;

fig. 21 is a waveform diagram illustrating a lighting voltage and a test gate signal in the display device according to the embodiment; and

fig. 22 is a waveform diagram illustrating a lighting voltage and a test gate signal in a display device according to an alternative embodiment.

Detailed Description

The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

Parts irrelevant to the description will be omitted to clearly describe the present disclosure, and like reference numerals denote like elements throughout the specification.

The use of cross-hatching and/or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, neither the presence nor absence of cross-hatching or shading is intended to convey or indicate any preference or requirement for particular materials, material properties, dimensions, proportions, commonality between illustrated elements, and/or any other feature, attribute, characteristic, etc. of an element. Further, in the drawings, the size and relative sizes of elements may be exaggerated for clarity and/or descriptive purposes. When embodiments may be implemented differently, certain processes may be performed in a different order than described. For example, two processes described in succession may be executed substantially concurrently or in the reverse order to that described.

When an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. To this end, the term "connected" may refer to physical, electrical, and/or fluid connections with or without intervening elements. Further, the X-axis, Y-axis, and Z-axis are not limited to three axes (such as X-axis, Y-axis, and Z-axis) of a rectangular coordinate system, and may be explained in a broader sense. For example, the X, Y, and Z axes may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For purposes of this disclosure, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" can be interpreted as X only, Y only, Z only, or any combination of two or more of X, Y and Z, e.g., XYZ, XYY, YZ, and ZZ. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Although the terms first, second, etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

Spatially relative terms, such as "below," "lower," "above," "upper," "above," "higher," "side" (e.g., as in "side walls"), and the like, may be used herein for descriptive purposes and thus to describe one element's relationship to another element(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and/or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. Further, the devices may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the terms "comprises" and/or "comprising" and/or "includes" and/or "including" when used in this specification specify the presence of stated features, integers, steps, operations, elements, components, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or combinations thereof. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as approximate terms and not as degree terms, and thus, are utilized to explain the inherent deviations in measured, calculated, and/or provided values that would be recognized by one of ordinary skill in the art.

Various embodiments are described herein with reference to cross-sectional illustrations and/or exploded illustrations that are schematic illustrations of idealized embodiments and/or intermediate structures. Thus, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments disclosed herein are not necessarily to be construed as limited to the particular illustrated shapes of regions but are to include deviations in shapes that result, for example, from manufacturing. In this manner, the regions illustrated in the figures may be schematic in nature and the shapes of these regions may not reflect the actual shape of a region of a device and, thus, are not necessarily intended to be limiting.

As is conventional in the art, some embodiments are described and illustrated in the figures as functional blocks, units, and/or modules. Those skilled in the art will appreciate that the blocks, units and/or modules are physically implemented by electronic (or optical) circuitry (such as logic circuitry, discrete components, microprocessors, hardwired circuitry, memory elements, wired connections, etc.), which may be formed using semiconductor-based or other manufacturing techniques. Where the blocks, units, and/or modules are implemented by a microprocessor or other similar hardware, they may be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and/or software. It is also contemplated that each block, unit, and/or module may be implemented by dedicated hardware, or as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions. Furthermore, each block, unit and/or module of some example embodiments may be physically separated into two or more interacting and discrete blocks, units and/or modules without departing from the scope of the inventive concept. Further, the blocks, units and/or modules of some embodiments may be physically combined into more complex blocks, units and/or modules without departing from the scope of the inventive concept.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Fig. 1 is a perspective view of a display device according to an embodiment, fig. 2 is a plan view of the display device according to the embodiment, and fig. 3 is a block diagram of the display device according to the embodiment.

In this specification, "upper", "above", "top", "upper side" or "upper surface" refers to an upward direction with respect to the display device 10, that is, a Z-axis direction, and "lower", "bottom", "lower side" or "lower surface" refers to a downward direction with respect to the display device 10, that is, a direction opposite to the Z-axis direction. Further, "left", "right", "upper" and "lower" refer to directions when the display device 10 is viewed from a plane. For example, "left" refers to a direction opposite to the X-axis direction, "right" refers to the X-axis direction, "upper" refers to the Z-axis direction, and "lower" refers to a direction opposite to the Z-axis direction.

Referring to fig. 1 to 3, embodiments of a display device 10 as a device for displaying moving or still images may be a device including a display screen, such as a television, a laptop or notebook computer, a display, a billboard, an internet of things ("IOT"), and a portable electronic device, such as a mobile phone, a smart phone, a tablet personal computer ("PC"), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player ("PMP"), a navigator, and an ultra mobile PC ("UMPC").

The display device 10 may be a light emitting display device such as an organic light emitting display device including an organic light emitting diode, a quantum dot light emitting display device including a quantum dot light emitting layer, an inorganic light emitting display device including an inorganic semiconductor, or a micro light emitting display device using a micro light emitting diode. Hereinafter, for convenience of description, an embodiment in which the display device 10 is an organic light emitting display device will be described, but the present invention is not limited thereto.

An embodiment of the display device 10 may include a display panel 100, a display driver 200, and a circuit board 300.

The display panel 100 may have a rectangular planar shape having a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction) intersecting the first direction (X-axis direction). The corner where the short side in the first direction (X-axis direction) meets the long side in the second direction (Y-axis direction) may have a right-angled shape or a circular shape with a predetermined curvature. The planar shape of the display panel 100 is not limited to a rectangular shape, and may be variously modified into another polygonal shape, a circular shape, or an elliptical shape. The display panel 100 may be flat, but the shape of the display panel 100 is not limited thereto. The display panel 100 may include curved portions at left and right ends of the display panel 100 and having a constant curvature or a variable curvature. The display panel 100 may be flexibly formed to be warped, bent, folded, or curled.

The display panel 100 may include a display area DA in which the pixels SP are arranged to display an image and a non-display area NDA that is a peripheral area of the display area DA. The display region DA may include pixels SP, scan lines SL connected to the pixels SP, emission control lines EL, data lines DL, and voltage supply lines VL. The scan lines SL and the emission control lines EL may be disposed in parallel in the first direction. The data lines DL and the voltage supply lines VL may be disposed in parallel in a second direction crossing the first direction.

Each of the pixels SP may be connected to a corresponding scan line SL, a corresponding data line DL, a corresponding emission control line EL, and a corresponding voltage supply line VL. Fig. 2 is an embodiment in which each of the pixels SP is connected to two scan lines SL, one data line DL, one emission control line EL, and one voltage supply line VL, but the present invention is not limited thereto. In an alternative embodiment, for example, each of the pixels SP may be connected to three scan lines SL.

The pixels SP may include first to third pixels RP, BP and GP. The first pixel RP may be connected to the first data line DL1 and the first scan line SL 1. The second pixel BP may be connected to the first data line DL1 and the second scan line SL 2. The first and second pixels RP and BP may be connected to the same data line DL and may be connected to scan lines SL different from each other. The first pixels RP may be disposed in the odd-numbered rows to be connected to the scan lines SL1, SL3,. multidot.sl (n-1) (n is a multiple of 2) of the odd-numbered rows, and the second pixels BP may be disposed in the even-numbered rows to be connected to the scan lines SL2, SL4,. multidot.sln of the even-numbered rows. The first and second pixels RP and BP are not limited to the pixels shown in fig. 2 and may be alternately disposed along the same data line DL. In one embodiment, for example, the scan driver 400 may perform the lighting inspection of the first pixels RP by supplying scan signals to some of the plurality of scan lines SL. In an alternative embodiment, for example, the scan driver 400 may perform the lighting check of the second pixels BP by supplying the scan signal to the other scan lines of the plurality of scan lines SL.

The third pixels GP may be connected between corresponding scan lines of the plurality of scan lines SL and the second data lines DL 2. The third pixels GP may be disposed along the same data line DL. In one embodiment, for example, the first and second pixels RP and BP may be connected to odd data lines DL1, DL3,. and DL (m-1) (m is a multiple of 2), and the third pixel GP may be connected to even data lines DL2, DL4,. and DLm.

Each of the pixels SP may include a driving transistor, a switching transistor, a light emitting element, and a capacitor. When a scan signal is applied from the scan line SL, the switching transistor may be turned on, and thus, a data voltage of the data line DL may be applied to the gate electrode of the driving transistor. The driving transistor may supply a driving current to the light emitting element based on the data voltage applied to the gate electrode, and the light emitting element may emit light having a predetermined luminance corresponding to the intensity of the driving current. In one embodiment, for example, the driving transistor and the switching transistor may be thin film transistors. The light emitting element may be an organic light emitting diode including a first electrode, an organic light emitting layer, and a second electrode. The capacitor may maintain a data voltage applied to the gate electrode of the driving transistor constant.

The non-display area NDA may be defined as an area from the display area DA to an edge of the display panel 100. The non-display area NDA may further include a scan driver 400 for applying scan signals to the scan lines SL, a fanout line between the data lines DL and the display driver 200, a pad DP connected to the display driver 200 to supply data voltages, a test pad TP for supplying a lighting voltage, and a test gate pad TGP for supplying a test gate signal.

In one embodiment, for example, the display driver 200 may be disposed at one side of the display panel 100, and the pad DP, the test pad TP, and the test gate pad TGP may be disposed at an edge portion of the display panel 100. The pad DP, the test pad TP, and the test gate pad TGP may be disposed closer to an edge of the display panel 100 than the display driver 200.

The test pads TP may include first to third test pads TP1, TP2, and TP 3. The first to third test pads TP1, TP2, and TP3 may receive the first to third lighting voltages, respectively. Each of the first to third lighting voltages may be a gray voltage of the on pixel SP or a black voltage of the off pixel SP. Each of the first to third lighting voltages may be a DC voltage, but is not limited thereto. In one embodiment, for example, the first to third test pads TP1, TP2, and TP3 may be connected to a lighting device or a power supply device, and may receive the first to third lighting voltages.

The non-display area NDA may further include a test transistor connected between the test pad TP and the display driver 200. The test transistors may include first to fourth test transistors TT1 to TT 4. The first test transistor TT1 may be connected between the first test pad TP1 and the first data line DL1, and the second test transistor TT2 may be connected between the second test pad TP2 and the second data line DL 2. The third test transistor TT3 may be connected between the third test pad TP3 and the third data line DL3, and the fourth test transistor TT4 may be connected between the second test pad TP2 and the fourth data line DL 4. Each of the first to fourth test transistors TT1 to TT4 may be connected between a corresponding one of the test pads TP and a corresponding one of the plurality of data lines DL, thereby selectively supplying the first to third lighting voltages to the plurality of data lines DL. In one embodiment, for example, each of the first to fourth test transistors TT1 to TT4 may receive the same test gate signal to be turned on or off at the same time.

The test gate pad TGP may receive a test gate signal and may be connected to a gate electrode of each of the first to fourth test transistors TT1 to TT 4. In one embodiment, for example, the test gate pad TGP may be connected to the lighting device, and may receive a test gate signal to turn on the first to fourth test transistors TT1 to TT4 from the lighting device.

The scan driver 400 may be connected to the display driver 200 through a plurality of scan control lines SCL. The scan driver 400 may receive the scan control signal SCS and the emission control signal ECS from the display driver 200 through the plurality of scan control lines SCL.

In an embodiment, as shown in fig. 3, the scan driver 400 may include a scan driving circuit 410 and an emission control driving circuit 420.

The scan driving circuit 410 may generate a scan signal based on the scan control signal SCS, and may sequentially output the scan signal to the scan lines SL. The emission control driving circuit 420 may generate emission signals corresponding to the emission control signals ECS from the display driver 200, and may sequentially output the emission signals to the emission control lines EL.

The scan driver 400 may include a plurality of thin film transistors. The scan driver 400 may be formed in the same layer as the thin film transistor of the pixel SP. In the embodiment, as shown in fig. 2, the scan driver 400 is formed in the non-display area NDA located at one side (e.g., the left side) of the display area DA, but the present invention is not limited thereto. In an alternative embodiment, for example, the scan driver 400 may be formed in the non-display area NDA located at two opposite sides (e.g., left and right sides) of the display area DA.

In an embodiment, as shown in fig. 3, the display driver 200 may include a timing controller 210, a data driver 220, and a power supply unit 230.

The timing controller 210 may receive digital video DATA and timing signals from the circuit board 300. The timing controller 210 may generate a data control signal DCS for controlling the operation timing of the data driver 220 based on the timing signals, may generate a scan control signal SCS for controlling the operation timing of the scan driving circuit 410 based on the timing signals, and may generate an emission control signal ECS for controlling the operation timing of the emission control driving circuit 420 based on the timing signals. The timing controller 210 may supply the digital video DATA and the DATA control signal DCS to the DATA driver 220. The timing controller 210 may supply the scan control signal SCS to the scan driving circuit 410 through the plurality of scan control lines SCL and may supply the emission control signal ECS to the emission control driving circuit 420.

The DATA driver 220 may convert the digital video DATA into an analog DATA voltage and supply the analog DATA voltage to the DATA lines DL through the fan-out lines. The scan signal of the scan driver 400 may select the pixels SP to which the data voltage is to be supplied, and the data driver 220 may supply the data voltage to the selected pixels SP.

The power supply unit 230 may generate a first driving voltage and supply the first driving voltage to the voltage supply line VL. The power supply unit 230 may generate a second driving voltage and supply the second driving voltage to the cathode electrode of the light emitting element of each of the pixels SP. Here, the first driving voltage may be a high potential voltage for driving the light emitting element, and the second driving voltage may be a low potential voltage for driving the light emitting element. That is, the first driving voltage may have a higher potential than the second driving voltage.

In an embodiment, the display driver 200 is formed as an integrated circuit ("IC") and may be attached to the display panel 100 by a chip on glass ("COG") method, a chip on plastic ("COP") method, or an ultrasonic bonding method. However, the present invention is not limited thereto. In an alternative embodiment, for example, the display driver 200 may be attached to the circuit board 300.

The circuit board 300 may be attached to the pad DP using an anisotropic conductive film. Accordingly, the lead of the circuit board 300 may be electrically connected to the pad DP. The circuit board 300 may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

Fig. 4 is a circuit diagram illustrating a pixel of a display device according to an embodiment.

Referring to fig. 2 to 4, in an embodiment, the pixels SP may be disposed on the display panel 100 along a plurality of rows and a plurality of columns. In one embodiment, for example, the pixels SP may be arranged in the kth row and the jth column of the display area DA. In this case, the pixel SP may be connected to a (k-1) th (herein, k is a natural number of 2 or more) scan line SL (k-1), a k-th scan line SLk, a k-th emission control line ELk, and a j (herein, j is a natural number) data line DLj. In such an embodiment, the pixels SP may be connected to a voltage supply line VL supplying the first driving voltage VDD, an initialization voltage line supplying the initialization voltage VINT, and a voltage supply line supplying the second driving voltage VSS.

The pixel SP may include a driving transistor DT, a light emitting element E, a switching element, and a first capacitor C1. In one embodiment, for example, the switching elements may include first to sixth switching transistors ST1, ST2, ST3, ST4, ST5, and ST 6.

The driving transistor DT controls a source-drain current (Isd) (hereinafter, referred to as a "driving current") based on a data voltage applied to the gate electrode. When the source-gate voltage (Vsg) of the driving transistor DT exceeds the threshold voltage (Vth), the driving current (Isd) may flow through the channel of the driving transistor DT. In one embodiment, for example, the driving current (Isd) is proportional to the square of the difference between the gate-source voltage (Vsg) and the threshold voltage (Vth) of the driving transistor DT, as shown in equation 1 below.

[ equation 1]

Isd＝k′X(Vsg-Vth)²

In equation 1, k' denotes a scaling factor determined by the structure and physical characteristics of the driving transistor DT, Vsg denotes a source-gate voltage of the driving transistor DT, and Vth denotes a threshold voltage of the driving transistor DT.

The light emitting element E may receive a driving current (Isd) to emit light. The emission amount or luminance of the light emitting element E may be proportional to the intensity of the driving current (Isd).

The light emitting element E may be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer disposed between the first electrode and the second electrode. Alternatively, the light emitting element E may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. Alternatively, the light emitting element E may be a quantum dot light emitting element including a first electrode, a second electrode, and a quantum dot light emitting layer disposed between the first electrode and the second electrode. Alternatively, the light emitting element E may be a micro light emitting diode. In one embodiment, for example, the first electrode of the light emitting element E may be an anode electrode, and the second electrode of the light emitting element E may be a cathode electrode, but the present invention is not limited thereto.

A first electrode or an anode electrode of the light emitting element E may be connected to a second electrode or a drain electrode of the fourth switching transistor ST4 and a second electrode or a drain electrode of the sixth switching transistor ST 6. A second electrode or a cathode electrode of the light emitting element E may be connected to a voltage supply line supplying a second driving voltage VSS.

The first switching transistor ST1 may selectively supply the initialization voltage VINT to the gate electrode of the driving transistor DT. In one embodiment, for example, the first switching transistor ST1 may be a double transistor including a first-first switching transistor ST1-1 and a second-first switching transistor ST 1-2. The first-first switching transistor ST1-1 and the second-first switching transistor ST1-2 may be turned on in response to a scan signal of the (k-1) th scan line SL (k-1) to supply the initialization voltage VINT to the gate electrode of the driving transistor DT. The gate electrode of the driving transistor DT may receive the initialization voltage VINT to be discharged. A gate electrode of the first-first switching transistor ST1-1 may be connected to the (k-1) th scan line SL (k-1), a first electrode of the first-first switching transistor ST1-1 may be connected to an initialization voltage line supplying an initialization voltage VINT, and a second electrode of the first-first switching transistor ST1-1 may be connected to a first electrode of the second-first switching transistor ST 1-2. A gate electrode of the second-first switching transistor ST1-2 may be connected to the (k-1) th scan line SL (k-1), a first electrode of the second-first switching transistor ST1-2 may be connected to a second electrode of the first-first switching transistor ST1-1, and a second electrode of the second-first switching transistor ST1-2 may be connected to a gate electrode of the driving transistor DT. In one embodiment, for example, the first electrode of the first switching transistor ST1 may be a source electrode, and the second electrode of the first switching transistor ST1 may be a drain electrode.

The second switching transistor ST2 may selectively supply the data voltage to the first electrode of the driving transistor DT. The second switching transistor ST2 may be turned on in response to a scan signal of the k-th scan line SLk to supply the data voltage to the first electrode of the driving transistor DT. A gate electrode of the second switching transistor ST2 may be connected to the kth scan line SLk, a first electrode of the second switching transistor ST2 may be connected to the jth data line DLj, and a second electrode of the second switching transistor ST2 may be connected to the first electrode of the driving transistor DT. In one embodiment, for example, the first electrode of the second switching transistor ST2 may be a source electrode, and the second electrode of the second switching transistor ST2 may be a drain electrode.

The third switching transistor ST3 may selectively connect the second electrode and the gate electrode of the driving transistor DT. In one embodiment, for example, the third switching transistor ST3 may be a double transistor including a first-third switching transistor ST3-1 and a second-third switching transistor ST 3-2. The first-third switching transistor ST3-1 and the second-third switching transistor ST3-2 may be turned on in response to a scan signal of the k-th scan line SLk to connect the second electrode and the gate electrode of the driving transistor DT. That is, when the first-third switching transistor ST3-1 and the second-third switching transistor ST3-2 are turned on, the second electrode and the gate electrode of the driving transistor DT are connected, and thus, the driving transistor DT may be driven as a diode. A gate electrode of the first-third switching transistor ST3-1 may be connected to the k-th scan line SLk, a first electrode of the first-third switching transistor ST3-1 may be connected to the second electrode of the driving transistor DT, and a second electrode of the first-third switching transistor ST3-1 may be connected to the first electrode of the second-third switching transistor ST 3-2. A gate electrode of the second-third switching transistor ST3-2 may be connected to the k-th scan line SLk, a first electrode of the second-third switching transistor ST3-2 may be connected to a second electrode of the first-third switching transistor ST3-1, and a second electrode of the second-third switching transistor ST3-2 may be connected to a gate electrode of the driving transistor DT. In one embodiment, for example, a first electrode of the third switching transistor ST3 may be a source electrode, and a second electrode of the third switching transistor ST3 may be a drain electrode.

The fourth switching transistor ST4 may selectively supply the initialization voltage VINT to the first electrode of the light emitting element E. The fourth switching transistor ST4 may be turned on in response to a scan signal of the k-th scan line SLk to supply the initialization voltage VINT to the first electrode of the light emitting element E. The first electrode of the light emitting element E may receive the initialization voltage VINT to be discharged. A gate electrode of the fourth switching transistor ST4 may be connected to the k-th scan line SLk, a first electrode of the fourth switching transistor ST4 may be connected to an initialization voltage line supplying an initialization voltage VINT, and a second electrode of the fourth switching transistor ST4 may be connected to a first electrode of the light emitting element E. In one embodiment, for example, a first electrode of the fourth switching transistor ST4 may be a source electrode, and a second electrode of the fourth switching transistor ST4 may be a drain electrode.

The fifth switching transistor ST5 may selectively supply the first driving voltage VDD to the first electrode of the driving transistor DT. The fifth switching transistor ST5 may be turned on in response to an emission signal of the kth emission control line ELk to supply the first driving voltage VDD to the first electrode of the driving transistor DT. A gate electrode of the fifth switching transistor ST5 may be connected to the kth emission control line ELk, a first electrode of the fifth switching transistor ST5 may be connected to the voltage supply line VL supplying the first driving voltage VDD, and a second electrode of the fifth switching transistor ST5 may be connected to the first electrode of the driving transistor DT. In one embodiment, for example, the first electrode of the fifth switching transistor ST5 may be a source electrode, and the second electrode of the fifth switching transistor ST5 may be a drain electrode.

The sixth switching transistor ST6 may selectively connect the second electrode of the driving transistor DT and the first electrode of the light emitting element E. The sixth switching transistor ST6 may be turned on in response to an emission signal of the k-th emission control line ELk to connect the second electrode of the driving transistor DT and the first electrode of the light emitting element E. A gate electrode of the sixth switching transistor ST6 may be connected to the k-th emission control line ELk, a first electrode of the sixth switching transistor ST6 may be connected to the second electrode of the driving transistor DT, and a second electrode of the sixth switching transistor ST6 may be connected to the first electrode of the light emitting element E. In one embodiment, for example, the first electrode of the sixth switching transistor ST6 may be a source electrode, and the second electrode of the sixth switching transistor ST6 may be a drain electrode. When both the fifth switching transistor ST5 and the sixth switching transistor ST6 are turned on, a driving current (Isd) may be supplied to the light emitting element E.

The first capacitor C1 may be connected between the gate electrode of the driving transistor DT and the voltage supply line VL. One electrode of the first capacitor C1 may be connected to the voltage supply line VL, and the other electrode of the first capacitor C1 may be connected to the gate electrode of the driving transistor DT, thereby maintaining a potential difference between the voltage supply line VL and the gate electrode of the driving transistor DT.

In one embodiment, for example, the semiconductor layer of each of the first to sixth switching transistors ST1, ST2, ST3, ST4, ST5, ST6 and the driving transistor DT may be formed by a low temperature polysilicon ("LTPS") process using polysilicon, but the present invention is not limited thereto.

Fig. 5 is a block diagram illustrating a scan driver of a display device according to an embodiment.

Referring to fig. 5, an embodiment of the scan driving circuit 410 may include a first scan driving circuit 411 and a second scan driving circuit 412. The first scan driving circuit 411 may be disposed at one side of the display panel 100, and may include a plurality of stages STG1 through STGn. The second scan driving circuit 412 may be disposed at the other side of the display panel 100, and may include a plurality of stages STG1 through STGn. The first scan driving circuit 411 and the second scan driving circuit 412 may be disposed opposite to each other. In one embodiment, for example, the first scan driving circuit 411 and the second scan driving circuit 412 may be respectively disposed at opposite sides of the display panel 100 to output the same scan signal, but the present invention is not limited thereto. Hereinafter, for convenience of description, the plurality of stages STG1 to STGn of the first scan driving circuit 411 will be mainly described, and any repetitive detailed description of the plurality of stages STG1 to STGn of the second scan driving circuit 412 will be omitted.

Each of the plurality of stages STG1 to STGn may include first and second clock terminals CT1 and CT2, a start terminal ST, and an output terminal OUT.

The first stage STG1 may be connected to a first clock line CL1 through a first clock terminal CT1, may be connected to a third clock line CL3 through a second clock terminal CT2, and may be connected to a first start signal line STL1 through a start terminal ST. The first clock terminal CT1 of the first stage STG1 may receive a first clock signal from the first clock line CL1, the second clock terminal CT2 of the first stage STG1 may receive a third clock signal from the third clock line CL3, and the start terminal ST of the first stage STG1 may receive a first start signal from the first start signal line STL 1. The output terminal OUT of the first stage STG1 may be connected to the start terminal ST of the first scan line SL1 and the third stage STG 3.

The second stage STG2 may be connected to the second clock line CL2 through the first clock terminal CT1, may be connected to the fourth clock line CL4 through the second clock terminal CT2, and may be connected to the second start signal line STL2 through the start terminal ST. The first clock terminal CT1 of the second stage STG2 may receive the second clock signal from the second clock line CL2, the second clock terminal CT2 of the second stage STG2 may receive the fourth clock signal from the fourth clock line CL4, and the start terminal ST of the second stage STG2 may receive the second start signal from the second start signal line STL 2. The output terminal OUT of the second stage STG2 may be connected to the start terminal ST of the second scan line SL2 and the fourth stage STG 4.

The third stage STG3 may be connected to the third clock line CL3 through the first clock terminal CT1, may be connected to the first clock line CL1 through the second clock terminal CT2, and may be connected to the output terminal OUT of the first stage STG1 through the start terminal ST. The first clock terminal CT1 of the third stage STG3 may receive the third clock signal from the third clock line CL3, the second clock terminal CT2 of the third stage STG3 may receive the first clock signal from the first clock line CL1, and the start terminal ST of the third stage STG3 may receive the output signal of the first stage STG 1. An output terminal OUT of the third stage STG3 may be connected to the start terminal ST of the third scan line SL3 and the fifth stage STG 5.

The fourth stage STG4 may be connected to the fourth clock line CL4 through the first clock terminal CT1, may be connected to the second clock line CL2 through the second clock terminal CT2, and may be connected to the output terminal OUT of the second stage STG2 through the start terminal ST. The first clock terminal CT1 of the fourth stage STG4 may receive the fourth clock signal from the fourth clock line CL4, the second clock terminal CT2 of the fourth stage STG4 may receive the second clock signal from the second clock line CL2, and the start terminal ST of the fourth stage STG4 may receive the output signal of the second stage STG 2. The output terminal OUT of the fourth stage STG4 may be connected to the start terminal ST of the fourth scan line SL4 and the sixth stage STG 6.

In such an embodiment, as shown in fig. 5, the start terminal ST of the (2p-1) th stage STG (2p-1) (hereinafter, p is a natural number of n/2 or less) may be connected to the output terminal OUT of the (2p-3) th stage STG (2p-3), and the start terminal ST of the 2 p-th stage STG (2p) may be connected to the output terminal OUT of the (2p-2) th stage STG (2 p-2). Accordingly, the (2p-1) th stage STG (2p-1) may receive the scan signal of the (2p-3) th stage STG (2p-3), and the 2p stage STG (2p) may receive the scan signal of the (2p-2) th stage STG (2 p-2). Here, the (2p-1) th stage STG (2p-1) may be an odd stage supplying the scan signal to the pixels SP disposed in the odd-numbered rows, and the 2 p-th stage STG (2p) may be an even stage supplying the scan signal to the pixels SP disposed in the even-numbered rows.

The (2p-1) th stage STG (2p-1) may receive the scan signal of the (2p-3) th stage STG (2p-3), and may alternately receive the first clock signal and the third clock signal through the first clock terminal CT1 or the second clock terminal CT2, thereby sequentially outputting the scan signal to the pixels disposed in the odd-numbered rows. The 2 p-th stage STG (2p) may receive the scan signal of the (2p-2) th stage STG (2p-2), and may alternately receive the second clock signal and the fourth clock signal through the first clock terminal CT1 or the second clock terminal CT2, thereby sequentially outputting the scan signal to the pixels disposed in the even-numbered rows.

When the scan driver 400 receives the first start signal from the first start signal line STL1 and does not receive the second start signal from the second start signal line STL2, the (2p-1) th stage STG (2p-1) may supply the scan signal to the scan lines SL1, SL3,.. cndot, SLn-1 in the odd-numbered rows, and the 2 p-th stage STG (2p) may not supply the scan signal to the scan lines SL2, SL4,.. cndot, SLn in the even-numbered rows. In one embodiment, for example, in the case where the first pixel RP and the second pixel BP are connected to the same data line DL, the first pixel RP is connected to the scan line in the odd-numbered row, and the second pixel BP is connected to the scan line in the even-numbered row, the scan driver 400 may perform the lighting check on the first pixel RP of the first pixel RP and the second pixel RP based on the first start signal. In such an embodiment, in the case where the first pixel RP and the second pixel BP are connected to the same data line DL, the first pixel RP is connected to the scan line in the odd-numbered row, and the second pixel BP is connected to the scan line in the even-numbered row, the scan driver 400 may perform the lighting check on the second pixel BP in the first pixel RP and the second pixel RP based on the second start signal. Therefore, in the embodiment of the display device 10, the lighting check may be selectively performed on the pixels in the odd-numbered rows or the pixels in the even-numbered rows among the pixels SP disposed in the plurality of rows, thereby sufficiently securing the charging time of the corresponding data lines. In the embodiment of the display apparatus 10, when the lighting inspection is performed on the plurality of pixels SP having a high resolution, the color mixture between the first pixel RP and the second pixel BP can be effectively prevented, and the reliability of the lighting inspection can be improved.

Fig. 6 is a waveform diagram illustrating input/output signals of a scan driver in a display device according to an embodiment. The input/output signal of the scan driver 400 of fig. 6 is a signal supplied in the display mode of the display device 10, and is different from a signal supplied in the lighting inspection mode of the display device 10.

Referring to fig. 6, a first start signal STS1 may be applied to a start terminal ST of the first-stage STG1, and a second start signal STS2 may be applied to a start terminal ST of the second-stage STG 2. In one embodiment, for example, the first start signal STS1 may have a gate-low voltage during a first period t1 of one frame (1 frame in fig. 6), and the second start signal STS2 may have a gate-low voltage during a second period t2 of one frame.

The first clock signal CLK1 may be applied to the first clock terminal CT1 or the second clock terminal CT2 of the (2p-1) th stage STG (2p-1) (hereinafter, p is a natural number of n/2 or less), and the second clock signal CLK2 may be applied to the first clock terminal CT1 or the second clock terminal CT2 of the 2 p-th stage STG (2 p). The first clock signal CLK1 may have a gate-low voltage during a (4q-3) th period from the first period t1 of one frame (hereinafter, q is a natural number of n/4 or less), and the second clock signal CLK2 may have a gate-low voltage during a (4q-2) th period from the second period t2 of one frame.

The third clock signal CLK3 may be applied to the first clock terminal CT1 or the second clock terminal CT2 of the (2p-1) th stage STG (2p-1), and the fourth clock signal CLK4 may be applied to the first clock terminal CT1 or the second clock terminal CT2 of the 2 p-th stage STG (2 p). The third clock signal CLK3 may have a gate-low voltage during a (4q-1) th period from the third period t3 of one frame, and the fourth clock signal CLK4 may have a gate-low voltage during a 4q th period from the fourth period t4 of one frame.

The plurality of stages STG1 to STGn may output a plurality of scan signals SC1 to SCn, phases of which are sequentially delayed based on the first and second start signals STS1 and STS2 and the first to fourth clock signals CLK1 to CLK 4. The plurality of stages STG1 to STGn may supply the scan signals SC1 to SCn to the plurality of pixels SP through the plurality of scan lines SL1 to SLn, and the plurality of pixels SP may emit light having a predetermined luminance based on the scan signals SC1 to SCn and the data voltages.

Fig. 7 is a waveform diagram illustrating input/output signals of odd stages in the display device of fig. 5. Here, the odd-numbered stage may be the (2p-1) th stage STG (2p-1) that supplies the scan signal to the scan line SL in the odd-numbered row among the plurality of stages STG1 to STGn.

Referring to fig. 7, the first start signal STS1 may be applied to a start terminal ST of the first stage STG1, and the first start signal STS1 may have a gate low voltage during a first period t1 of one frame. The first stage STG1 may output the first scan signal SC1 based on the first start signal STS1 and the first and third clock signals CLK1 and CLK 3. The first scan signal SC1 may be applied to the start terminal ST of the first scan line SL1 and the third stage STG 3.

The third stage STG3 may output the third scan signal SC3 based on the first scan signal SC1 of the first stage STG1 and the first and third clock signals CLK1 and CLK 3. The third scan signal SC3 may be applied to the start terminal ST of the third scan line SL3 and the fifth stage STG 5.

In the embodiment, as described above, the (2p-1) th stage STG (2p-1) may receive the scan signal of the (2p-3) th stage STG (2p-3), and may alternately receive the first clock signal and the third clock signal through the first clock terminal CT1 or the second clock terminal CT2, thereby sequentially outputting the scan signal to the pixels SP disposed in the odd-numbered rows.

The second start signal STS2 may be applied to the start terminal ST of the second stage STG 2. When the lighting check is performed on the pixels SP disposed in the odd-numbered rows, the second start signal STS2 may maintain the gate high voltage during one frame. The second stage STG2 may not output the second scan signal SC2, and the 2 p-th stage STG (2p) may not output the scan signal. Therefore, the pixels SP disposed in the even-numbered rows can maintain the off-state.

In one embodiment, for example, in the case where the first pixel RP and the second pixel BP are connected to the same data line DL, the first pixel RP is connected to a scan line in an odd-numbered row, and the second pixel BP is connected to a scan line in an even-numbered row, the scan driver 400 may perform a lighting check on the first pixel RP among the first pixel RP and the second pixel RP based on the first start signal STS 1. Therefore, in the embodiment of the display device 10, the lighting check can be selectively performed on the pixels in the odd-numbered rows among the pixels SP arranged in the plurality of rows, thereby sufficiently securing the charging time of the corresponding data lines. In the embodiment of the display apparatus 10, when the lighting inspection is performed on the plurality of pixels SP having the high resolution, the color mixture between the first pixel RP and the second pixel BP can be prevented and the reliability of the lighting inspection can be improved.

Fig. 8 is a diagram illustrating a process of supplying a lighting voltage in a display device according to an embodiment.

Referring to fig. 8, the test pads TP may include first to third test pads TP1, TP2, and TP 3. The first to third test pads TP1, TP2, and TP3 may receive the first to third lighting voltages DC1, DC2, and DC3, respectively. Each of the first to third lighting voltages DC1, DC2, and DC3 may be a gray voltage of the on pixel SP or a black voltage of the off pixel SP. Each of the first to third lighting voltages DC1, DC2, and DC3 may be a direct current ("DC") voltage, but is not limited thereto. In one embodiment, for example, the first to third test pads TP1, TP2, and TP3 may be connected to a lighting device or a power supply device, and may receive first to third lighting voltages DC1, DC2, and DC 3.

The test transistors may include first to fourth test transistors TT1 to TT 4. The first test transistor TT1 may be connected between the first test pad TP1 and the j-th data line DLj, and the second test transistor TT2 may be connected between the second test pad TP2 and the (j +1) -th data line DLj + 1. The third test transistor TT3 may be connected between the third test pad TP3 and the (j +2) th data line DLj +2, and the fourth test transistor TT4 may be connected between the second test pad TP2 and the (j +3) th data line DLj + 3. Each of the first to fourth test transistors TT1 to TT4 is connected between a corresponding one of the test pads TP and a corresponding one of the plurality of data lines DL, thereby selectively supplying the first to third lighting voltages DC1, DC2 and DC3 to the plurality of data lines DL. In one embodiment, for example, the first to fourth test transistors TT1 to TT4 may receive the same test gate signal TG and, thus, may be turned on or off at the same time.

The test gate pad TGP may receive a test gate signal TG and may be connected to a gate electrode of each of the first to fourth test transistors TT1 to TT 4. In one embodiment, for example, the test gate pad TGP may be connected to the lighting device, and may receive a test gate signal TG turning on the first to fourth test transistors TT1 to TT4 from the lighting device.

Fig. 9 is a waveform diagram illustrating a lighting voltage and a test gate signal in the display device according to the embodiment, and fig. 10 is a graph illustrating a result of a lighting inspection of the first pixel in the display device of fig. 9.

Referring to fig. 9 and 10, in the embodiment of the display apparatus 10, the lighting check may be performed on some of the plurality of pixels SP. In the embodiment of the display device 10, the first to third lighting voltages DC1, DC2, and DC3 may be supplied through the first to third test pads TP1, TP2, and TP3, and the test gate signal TG may be supplied through the test gate pad TGP.

The first lighting voltage DC1 may maintain the gray voltage GV of the turn-on pixel SP during one frame or during the first to eighth periods t1 to t 8. The second and third lighting voltages DC2 and DC3 may maintain the black voltage BV of the off pixel SP during one frame or during the first to eighth periods t1 to t 8. The pixel SP may be turned on when the pixel SP receives the gray voltage GV from the data line DL, and may be turned off when the pixel SP receives the black voltage BV from the data line DL.

The test gate signal TG may maintain the gate low voltage VGL during one frame or during the first to eighth periods t1 to t 8. Accordingly, each of the first to fourth test transistors TT1 to TT4 may receive the test gate signal TG to be turned on.

Referring to fig. 7 to 10, when a lighting check is performed on the first pixel RP of the first and second pixels RP and BP connected to the first or jth data line DL1 or DLj, the first start signal STS1 may have the gate low voltage VGL during the first period t1 of one frame, and the second start signal STS2 may maintain the gate high voltage VGH during one frame. The (2p-1) th stage STG (2p-1) may supply scan signals SC1, SC3, SC5,.. to the scan lines SL1, SL3, SL5,. in odd-numbered rows, and the 2p stage STG (2p) may not output the scan signals. The first lighting voltage DC1 may maintain the gray voltage GV during one frame, and the second and third lighting voltages DC2 and DC3 may maintain the black voltage BV during one frame. Accordingly, of the first and second pixels RP and BP connected to the first or jth data line DL1 or DLj, the first pixel RP connected to the scan line SL1, SL3, SL5,. in an odd-numbered row may be turned on, and the second pixel BP connected to the scan line SL2, SL4, SL6,. in an even-numbered row may be turned off. In one embodiment, for example, in the display device 10, after the first pixel RP connected to the first data line DL1 and the first scan line SL1 is turned on, by turning on the first pixel RP connected to the third scan line SL3 without turning on the second pixel BP connected to the second scan line SL2, the charging time of the first data line DL1 may be sufficiently secured. In such an embodiment of the display device 10, color mixing between the first pixel RP and the second pixel BP can be effectively prevented, and the reliability of the lighting inspection can be improved.

Fig. 11 is a waveform diagram illustrating a lighting voltage and a test gate signal in the display device according to the alternative embodiment, and fig. 12 is a diagram illustrating a result of a lighting inspection of the second pixel in the display device of fig. 11.

Referring to fig. 11 and 12, in the embodiment of the display apparatus 10, the lighting check may be performed on some of the plurality of pixels SP. In the embodiment of the display device 10, the first to third lighting voltages DC1, DC2, and DC3 may be supplied through the first to third test pads TP1, TP2, and TP3, and the test gate signal TG may be supplied through the test gate pad TGP.

The first and second lighting voltages DC1 and DC2 may maintain the black voltage BV of the turn-off pixel SP during one frame or during the first to eighth periods t1 to t 8. The third lighting voltage DC3 may maintain the gray voltage GV of the turn-on pixel SP during one frame or during the first to eighth periods t1 to t 8. The pixel SP may be turned on when the pixel SP receives the gray voltage GV from the data line DL, and may be turned off when the pixel SP receives the black voltage BV from the data line DL.

The test gate signal TG may maintain the gate low voltage VGL during one frame or during the first to eighth periods t1 to t 8. Accordingly, each of the first to fourth test transistors TT1 to TT4 may receive the test gate signal TG to be turned on.

Referring to fig. 7, 8, 11, and 12, when a lighting check is performed on the first pixel RP and the second pixel BP among the second pixels BP connected to the third data line DL3 or the (j +2) th data line DLj +2, the first start signal STS1 may have the gate low voltage VGL during the first period t1 of one frame, and the second start signal STS2 may maintain the gate high voltage VGH during one frame. The (2p-1) th stage STG (2p-1) may supply scan signals SC1, SC3, SC5,.. to the scan lines SL1, SL3, SL5,. in odd-numbered rows, and the 2p stage STG (2p) may not output the scan signals. The first and second lighting voltages DC1 and DC2 may maintain the black voltage BV during one frame, and the third lighting voltage DC3 may maintain the gray voltage GV during one frame. Accordingly, of the first and second pixels RP and BP connected to the third or (j +2) th data line DL3 or DLj +2, the second pixel BP connected to the scan line SL1, SL3, SL5,. in the odd-numbered rows may be turned on, and the first pixel RP connected to the scan line SL2, SL4, SL6,. in the even-numbered rows may be turned off. In one embodiment, for example, in the display device 10, after the second pixel BP connected to the third data line DL3 and the first scan line SL1 is turned on, by turning on the second pixel BP connected to the third scan line SL3 without turning on the first pixel RP connected to the second scan line SL2, the charging time of the third data line DL3 may be sufficiently secured. In the display device 10, color mixing between the first pixel RP and the second pixel BP can be effectively prevented, and the reliability of the lighting inspection can be improved.

Fig. 13 is a waveform diagram illustrating input/output signals of even-numbered stages in the display device of fig. 5. Here, the even stage may be a 2 p-th stage STG (2p) that supplies a scan signal to the scan line SL in an even row among the plurality of stages STG1 to STGn.

Referring to fig. 13, the second start signal STS2 may be applied to the start terminal ST of the second stage STG2, and the second start signal STS2 may have a gate low voltage during the second period t2 of one frame. The second stage STG2 may output the second scan signal SC2 based on the second start signal STS2 and the second and fourth clock signals CLK2 and CLK 4. The second scan signal SC2 may be applied to the start terminal ST of the second scan line SL2 and the fourth stage STG 4.

The fourth stage STG4 may output the fourth scan signal SC4 based on the second scan signal SC2 and the second and fourth clock signals CLK2 and CLK4 of the second stage STG 2. The fourth scan signal SC4 may be applied to the start terminal ST of the fourth scan line SL4 and the sixth stage STG 6.

In such an embodiment, as described above, the 2 p-th stage STG (2p) may receive the scan signal of the (2p-2) th stage STG (2p-2), and may alternately receive the second clock signal and the fourth clock signal through the first clock terminal CT1 or the second clock terminal CT2, thereby sequentially outputting the scan signal to the pixels disposed in the even-numbered rows.

The first start signal STS1 may be applied to a start terminal ST of the first stage STG 1. When the lighting check is performed on the pixels SP disposed in the even-numbered rows, the first start signal STS1 may maintain the gate high voltage during one frame. The first stage STG1 may not output the first scan signal SC1, and the (2p-1) th stage STG (2p-1) may not output the scan signal. Therefore, the pixels SP disposed in the odd-numbered rows can maintain the turned-off state.

In one embodiment, for example, when the first pixel RP and the second pixel BP are connected to the same data line DL, the first pixel RP is connected to the scan line in the odd-numbered row, and the second pixel BP is connected to the scan line in the even-numbered row, the scan driver 400 may perform the lighting check on the second pixel BP in the first pixel RP and the second pixel BP based on the second start signal. As described above, in the embodiment of the display device 10, the lighting check may be selectively performed on the pixels in the even-numbered rows among the pixels SP disposed in the plurality of rows, thereby sufficiently securing the charging time of the corresponding data lines. In the embodiment of the display apparatus 10, when the lighting inspection is performed on the plurality of pixels SP having a high resolution, the color mixture between the first pixel RP and the second pixel BP can be effectively prevented, and the reliability of the lighting inspection can be improved.

Fig. 14 is a diagram illustrating a result of lighting inspection of the second pixel in the display device of fig. 13.

Referring to fig. 14 and fig. 8, 9, and 13, in the embodiment of the display device 10, the lighting check may be performed on some of the plurality of pixels SP. In the embodiment of the display device 10, the first to third lighting voltages DC1, DC2, and DC3 may be supplied through the first to third test pads TP1, TP2, and TP3, and the test gate signal TG may be supplied through the test gate pad TGP.

The first lighting voltage DC1 may maintain the gray voltage GV of the turn-on pixel SP during one frame or during the first to eighth periods t1 to t 8. The second and third lighting voltages DC2 and DC3 may maintain the black voltage BV of the off pixel SP during one frame or during the first to eighth periods t1 to t 8. The pixel SP may be turned on when the pixel SP receives the gray voltage GV from the data line DL, and may be turned off when the pixel SP receives the black voltage BV from the data line DL.

The test gate signal TG may maintain the gate low voltage VGL during one frame or during the first to eighth periods t1 to t 8. Accordingly, each of the first to fourth test transistors TT1 to TT4 may receive the test gate signal TG to be turned on.

When a lighting check is performed on the first pixel RP connected to the first data line DL1 or the jth data line DLj and the second pixel BP of the second pixels BP, the second start signal STS2 may have the gate low voltage VGL during the second period t2 of one frame, and the first start signal STS1 may maintain the gate high voltage VGH during one frame. The 2 p-th stage STG (2p) may supply scan signals SC2, SC4, SC6,. to scan lines SL2, SL4, SL6,. in even rows, and the (2p-1) -th stage STG (2p-1) may not output the scan signals. The first lighting voltage DC1 may maintain the gray voltage GV during one frame, and the second and third lighting voltages DC2 and DC3 may maintain the black voltage BV during one frame. Accordingly, of the first and second pixels RP and BP connected to the first or jth data line DL1 or DLj, the second pixel BP connected to the scan lines SL2, SL4, SL6,. in even rows may be turned on, and the first pixel RP connected to the scan lines SL1, SL3, SL5,. in odd rows may be turned off. In one embodiment, for example, in the display device 10, after the second pixels BP connected to the first data line DL1 and the second scan line SL2 are turned on, by turning on the second pixels BP connected to the fourth scan line SL4 without turning on the first pixels RP connected to the third scan line SL3, the charging time of the first data line DL1 may be sufficiently secured. In such an embodiment of the display device 10, color mixing between the first pixel RP and the second pixel BP can be effectively prevented, and the reliability of the lighting inspection can be improved.

Fig. 15 is a diagram illustrating a result of a lighting inspection of the first pixel in the display device of fig. 13.

Referring to fig. 15 and fig. 8, 11, and 13, in the embodiment of the display device 10, the lighting check may be performed on some of the plurality of pixels SP. In the embodiment of the display device 10, the first to third lighting voltages DC1, DC2, and DC3 may be supplied through the first to third test pads TP1, TP2, and TP3, and the test gate signal TG may be supplied through the test gate pad TGP.

The first and second lighting voltages DC1 and DC2 may maintain the black voltage BV of the turn-off pixel SP during one frame or during the first to eighth periods t1 to t 8. The third lighting voltage DC3 may maintain the gray voltage GV of the turn-on pixel SP during one frame or during the first to eighth periods t1 to t 8. The pixel SP may be turned on when the pixel SP receives the gray voltage GV from the data line DL, and may be turned off when the pixel SP receives the black voltage BV from the data line DL.

The test gate signal TG may maintain the gate low voltage VGL during one frame or during the first to eighth periods t1 to t 8. Accordingly, each of the first to fourth test transistors TT1 to TT4 may receive the test gate signal TG to be turned on.

When a lighting check is performed on the first pixel RP of the first pixel RP and the second pixel BP connected to the third data line DL3 or the (j +2) th data line DLj +2, the second start signal STS2 may have the gate low voltage VGL during the second period t2 of one frame, and the first start signal STS1 may maintain the gate high voltage VGH during one frame. The 2 p-th stage STG (2p) may supply scan signals SC2, SC4, SC6,. to scan lines SL2, SL4, SL6,. in even rows, and the (2p-1) -th stage STG (2p-1) may not output the scan signals. The first and second lighting voltages DC1 and DC2 may maintain the black voltage BV during one frame, and the third lighting voltage DC3 may maintain the gray voltage GV during one frame. Accordingly, among the first and second pixels RP and BP connected to the third or (j +2) th data line DL3 or DLj +2, the first pixel RP connected to the scan line SL2, SL4, SL6,. in even-numbered rows may be turned on, and the second pixel BP connected to the scan line SL1, SL3, SL5,. in odd-numbered rows may be turned off. In one embodiment, for example, in the display device 10, after the first pixels RP connected to the third data line DL3 and the second scan line SL2 are turned on, by turning on the first pixels RP connected to the fourth scan line SL4 without turning on the second pixels BP connected to the third scan line SL3, the charging time of the third data line DL3 may be sufficiently secured. In such an embodiment of the display device 10, color mixing between the first pixel RP and the second pixel BP can be effectively prevented, and the reliability of the lighting inspection can be improved.

Fig. 16 is a block diagram illustrating a scan driver of a display device according to an alternative embodiment.

The scan driver of the display device of fig. 16 is substantially the same as the scan driver of the display device of fig. 5 except for the start signal line STL. Accordingly, any repetitive detailed description of elements that are the same as or similar to those described above with reference to fig. 5 will be omitted or simplified hereinafter.

Referring to fig. 16, an embodiment of the scan driving circuit 410 may include a first scan driving circuit 411 and a second scan driving circuit 412. The first scan driving circuit 411 may be disposed at one side of the display panel 100, and may include a plurality of stages STG1 through STGn. The second scan driving circuit 412 may be disposed at the other side of the display panel 100, and may include a plurality of stages STG1 through STGn. In one embodiment, for example, the first scan driving circuit 411 and the second scan driving circuit 412 may be respectively disposed at opposite sides of the display panel 100 to output the same scan signal, but the present invention is not limited thereto.

Each of the plurality of stages STG1 to STGn may include first and second clock terminals CT1 and CT2, a start terminal ST, and an output terminal OUT.

The first stage STG1 may be connected to the first clock line CL1 through the first clock terminal CT1, may be connected to the third clock line CL3 through the second clock terminal CT2, and may be connected to the start signal line STL through the start terminal ST. The first clock terminal CT1 of the first stage STG1 may receive a first clock signal from the first clock line CL1, the second clock terminal CT2 of the first stage STG1 may receive a third clock signal from the third clock line CL3, and the start terminal ST of the first stage STG1 may receive a start signal from the start signal line STL. The output terminal OUT of the first stage STG1 may be connected to the start terminal ST of the first scan line SL1 and the third stage STG 3.

The second stage STG2 may be connected to the second clock line CL2 through the first clock terminal CT1, may be connected to the fourth clock line CL4 through the second clock terminal CT2, and may be connected to the start signal line STL through the start terminal ST. The first clock terminal CT1 of the second stage STG2 may receive the second clock signal from the second clock line CL2, the second clock terminal CT2 of the second stage STG2 may receive the fourth clock signal from the fourth clock line CL4, and the start terminal ST of the second stage STG2 may receive the start signal from the start signal line STL. The output terminal OUT of the second stage STG2 may be connected to the start terminal ST of the second scan line SL2 and the fourth stage STG 4.

The start terminal ST of the (2p-1) th stage STG (2p-1) may be connected to the output terminal OUT of the (2p-3) th stage STG (2p-3), and the start terminal ST of the 2p stage STG (2p) may be connected to the output terminal OUT of the (2p-2) th stage STG (2 p-2). Accordingly, the (2p-1) th stage STG (2p-1) may receive the scan signal of the (2p-3) th stage STG (2p-3), and the 2p stage STG (2p) may receive the scan signal of the (2p-2) th stage STG (2 p-2). Here, the (2p-1) th stage STG (2p-1) may be an odd stage supplying the scan signal to the pixels SP disposed in the odd-numbered rows, and the 2 p-th stage STG (2p) may be an even stage supplying the scan signal to the pixels SP disposed in the even-numbered rows.

The (2p-1) th stage STG (2p-1) may receive the scan signal of the (2p-3) th stage STG (2p-3), and may alternately receive the first clock signal and the third clock signal through the first clock terminal CT1 or the second clock terminal CT2, thereby sequentially outputting the scan signal to the pixels disposed in the odd-numbered rows. The 2 p-th stage STG (2p) may receive the scan signal of the (2p-2) th stage STG (2p-2), and may alternately receive the second clock signal and the fourth clock signal through the first clock terminal CT1 or the second clock terminal CT2, thereby sequentially outputting the scan signal to the pixels disposed in the even-numbered rows.

When the scan driver 400 receives a start signal having a gate low voltage during the first period t1 and a gate high voltage during the second period t2 from the start signal line STL, the (2p-1) th stage STG (2p-1) may supply a scan signal to the scan lines SL1, SL3,.. multidot.sln-1 in the odd-numbered rows, and the 2 p-th stage STG (2p) may not supply a scan signal to the scan lines SL2, SL4,.multidot.sln in the even-numbered rows.

In one embodiment, for example, in the case where the first pixel RP and the second pixel BP are connected to the same data line DL, the first pixel RP is connected to the scan line in the odd-numbered row, and the second pixel BP is connected to the scan line in the even-numbered row, the scan driver 400 may perform the lighting check on the first pixel RP of the first pixel RP and the second pixel BP based on the start signal having the gate low voltage only during the first period t 1. In such an embodiment, in the case where the first pixel RP and the second pixel BP are connected to the same data line DL, the first pixel RP is connected to the scan line in the odd-numbered row, and the second pixel BP is connected to the scan line in the even-numbered row, the scan driver 400 may perform the lighting check on the second pixel BP of the first pixel RP and the second pixel BP based on the start signal having the gate low voltage only during the second period t 2. Accordingly, since the display device 10 includes the plurality of stages STG1 to STGn connected to one start signal line STL to control the timing at which the start signal has the gate low voltage, it is possible to selectively perform the lighting check on the pixels in the odd-numbered rows or the pixels in the even-numbered rows among the pixels SP disposed in the plurality of rows, thereby sufficiently securing the charging time of the corresponding data line. In such an embodiment of the display device 10, color mixing between the first pixel RP and the second pixel BP can be prevented, and the reliability of the lighting inspection can be improved.

Fig. 17 is a waveform diagram illustrating input/output signals of odd stages in the display device of fig. 16.

The input/output signals of the odd-numbered stages of fig. 17 are substantially the same as those of the odd-numbered stages of fig. 7 except for the start signal STS. Accordingly, any repetitive detailed description of elements that are the same as or similar to those described above with reference to fig. 7 will be omitted or simplified hereinafter.

Referring to fig. 17, a start signal STS may be applied to a start terminal ST of the first-stage STG1 and a start terminal ST of the second-stage STG 2. When the lighting check is performed on the pixels SP disposed in the odd-numbered rows, the start signal STS may have a gate low voltage during the first period t1 of one frame and may have a gate high voltage during the second period t2 of one frame. The first stage STG1 may output the first scan signal SC1 based on the start signal STS having the gate low voltage during the first period t1 and the first and third clock signals CLK1 and CLK 3. The first scan signal SC1 may be applied to the start terminal ST of the first scan line SL1 and the third stage STG 3.

The second stage STG2 may receive the start signal having the gate high voltage during the second period t2 and may not output the second scan signal SC 2. Therefore, the pixels SP disposed in the even-numbered rows can maintain the off-state.

The third stage STG3 may output the third scan signal SC3 based on the first scan signal SC1 of the first stage STG1 and the first and third clock signals CLK1 and CLK 3. The third scan signal SC3 may be applied to the start terminal ST of the third scan line SL3 and the fifth stage STG 5.

In such an embodiment, as described above, the (2p-1) th stage STG (2p-1) may receive the scan signal of the (2p-3) th stage STG (2p-3), and may alternately receive the first clock signal and the third clock signal through the first clock terminal CT1 or the second clock terminal CT2, thereby sequentially outputting the scan signal to the pixels disposed in the odd-numbered rows.

In one embodiment, for example, in the case where the first pixel RP and the second pixel BP are connected to the same data line DL, the first pixel RP is connected to the scan line in the odd-numbered row, and the second pixel BP is connected to the scan line in the even-numbered row, the scan driver 400 may perform the lighting check on the first pixel RP of the first pixel RP and the second pixel BP based on the start signal STS having the gate low voltage during the first period t 1. As described above, in the embodiment of the display device 10, the lighting check may be selectively performed on the pixels in the odd-numbered rows among the pixels SP disposed in the plurality of rows, thereby sufficiently securing the charging time of the corresponding data lines. In such an embodiment of the display apparatus 10, when the lighting inspection is performed on the plurality of pixels SP having a high resolution, the color mixture between the first pixel RP and the second pixel BP can be effectively prevented, and the reliability of the lighting inspection can be improved.

Fig. 18 is a waveform diagram illustrating input/output signals of even-numbered stages in the display device of fig. 16.

The input/output signals of the even-numbered stages of fig. 18 are substantially the same as those of the even-numbered stages of fig. 13 except for the start signal STS. Therefore, any repetitive detailed description of elements that are the same as or similar to those described above with reference to fig. 13 will be omitted or simplified hereinafter.

Referring to fig. 18, a start signal STS may be applied to a start terminal ST of the first-stage STG1 and a start terminal ST of the second-stage STG 2. When the lighting check is performed on the pixels SP disposed in the even-numbered rows, the start signal STS may have a gate high voltage during the first period t1 of one frame and may have a gate low voltage during the second period t2 of one frame. The second stage STG2 may output the second scan signal SC2 based on the start signal STS having the gate low voltage during the second period t2 and the second and fourth clock signals CLK2 and CLK 4. The second scan signal SC2 may be applied to the start terminal ST of the second scan line SL2 and the fourth stage STG 4.

The first stage STG1 may receive a start signal having a gate high voltage during the first period t1 and may not output the first scan signal SC 1. Therefore, the pixels SP disposed in the odd-numbered rows can maintain the turned-off state.

The fourth stage STG4 may output the fourth scan signal SC4 based on the second scan signal SC2 and the second and fourth clock signals CLK2 and CLK4 of the second stage STG 2. The fourth scan signal SC4 may be applied to the start terminal ST of the fourth scan line SL4 and the sixth stage STG 6.

As described above, the 2 p-th stage STG (2p) may receive the scan signal of the (2p-2) th stage STG (2p-2), and may alternately receive the second clock signal and the fourth clock signal through the first clock terminal CT1 or the second clock terminal CT2, thereby sequentially outputting the scan signal to the pixels disposed in the even-numbered rows.

In one embodiment, for example, in the case where the first pixel RP and the second pixel BP are connected to the same data line DL, the first pixel RP is connected to the scan line in the odd-numbered row, and the second pixel BP is connected to the scan line in the even-numbered row, the scan driver 400 may perform the lighting check on the second pixel BP of the first pixel RP and the second pixel BP based on the start signal STS having the gate low voltage during the second period t 2. As described above, in the embodiment of the display device 10, the lighting check may be selectively performed on the pixels in the even-numbered rows among the pixels SP disposed in the plurality of rows, thereby sufficiently securing the charging time of the corresponding data lines. In such an embodiment of the display apparatus 10, when the lighting inspection is performed on the plurality of pixels SP having a high resolution, the color mixture between the first pixel RP and the second pixel BP can be effectively prevented, and the reliability of the lighting inspection can be improved.

Fig. 19 is a plan view of a display device according to an alternative embodiment, and fig. 20 is a diagram illustrating a process of supplying a lighting voltage in the display device according to the alternative embodiment.

The display device of fig. 19 and 20 is substantially the same as the display device of fig. 2 and 8 except for testing the transistor and testing the gate pad. Therefore, any repetitive detailed description of elements that are the same as or similar to those described above with reference to fig. 2 and 8 will be omitted or simplified hereinafter.

Referring to fig. 19 and 20, in an embodiment of the display device, the test pads TP may include first to third test pads TP1, TP2, and TP 3. The first to third test pads TP1, TP2, and TP3 may receive the first to third lighting voltages DC1, DC2, and DC3, respectively. Each of the first to third lighting voltages DC1, DC2, and DC3 may be a gray voltage of the on pixel SP or a black voltage of the off pixel SP. Each of the first to third lighting voltages DC1, DC2, and DC3 may be a DC voltage, but is not limited thereto. In one embodiment, for example, the first to third test pads TP1, TP2, and TP3 may be connected to a lighting device or a power supply device, and may receive first to third lighting voltages DC1, DC2, and DC 3.

The test transistors may include first to sixth test transistors TT1 to TT 6. The gate electrode of the first test transistor TT1 may be connected to the first test gate pad TGP 1. The first test transistor TT1 may be connected between the first test pad TP1 and the jth data line DLj. The first test transistor TT1 may selectively supply the first lighting voltage DC1 to the jth data line DLj based on the first test gate signal TG1 received from the first test gate pad TGP 1.

The gate electrode of the second test transistor TT2 may be connected to the second test gate pad TGP 2. The second test transistor TT2 may be connected between the first test pad TP1 and the (j +2) th data line DLj + 2. The second test transistor TT2 may selectively supply the first lighting voltage DC1 to the (j +2) th data line DLj +2 based on the second test gate signal TG2 received from the second test gate pad TGP 2.

The gate electrode of the third test transistor TT3 may be connected to the first test gate pad TGP 1. The third test transistor TT3 may be connected between the third test pad TP3 and the (j +2) th data line DLj + 2. The third test transistor TT3 may selectively supply the third lighting voltage DC3 to the (j +2) th data line DLj +2 based on the first test gate signal TG1 received from the first test gate pad TGP 1.

A gate electrode of the fourth test transistor TT4 may be connected to the second test gate pad TGP 2. The fourth test transistor TT4 may be connected between the third test pad TP3 and the jth data line DLj. The fourth test transistor TT4 may selectively supply the third lighting voltage DC3 to the jth data line DLj based on the second test gate signal TG2 received from the second test gate pad TGP 2.

A gate electrode of each of the fifth test transistor TT5 and the sixth test transistor TT6 may be connected to the third test gate pad TGP 3. The fifth test transistor TT5 may be connected between the second test pad TP2 and the (j +1) th data line DLj +1, and the sixth test transistor TT6 may be connected between the second test pad TP2 and the (j +3) th data line DLj + 3. The fifth test transistor TT5 may selectively supply the second lighting voltage DC2 to the (j +1) th data line DLj +1 based on the third test gate signal TG3 received from the third test gate pad TGP 3. The sixth test transistor TT6 may selectively supply the second lighting voltage DC2 to the (j +3) th data line DLj +3 based on the third test gate signal TG3 received from the third test gate pad TGP 3.

Each of the first to sixth test transistors TT1 to TT6 may be connected between a corresponding one of the test pads TP and a corresponding one of the plurality of data lines DL, thereby selectively supplying the first to third lighting voltages DC1, DC2 and DC3 to the plurality of data lines DL.

The first to third test gate pads TGP1, TGP2, and TGP3 may receive the first to third test gate signals TG1, TG2, and TG3, respectively. Each of the first to third test gate pads TGP1, TGP2, and TGP3 may be connected to a gate electrode of at least one transistor selected from the first to sixth test transistors TT1 to TT 6. In one embodiment, for example, the test gate pad TGP may be connected to the lighting device, and may receive a test gate signal turning on the first to sixth test transistors TT1 to TT6 from the lighting device.

Fig. 21 is a waveform diagram illustrating a lighting voltage and a test gate signal in a display device according to an embodiment.

Referring to fig. 21, in the embodiment of the display apparatus 10, the lighting check may be performed on some of the plurality of pixels SP. In the embodiment of the display device 10, the first to third lighting voltages DC1, DC2, and DC3 may be supplied through the first to third test pads TP1, TP2, and TP3, and the first to third test gate signals TG1, TG2, and TG3 may be supplied through the first to third test gate pads TGP1, TGP2, and TGP 3.

The first lighting voltage DC1 may maintain the gray voltage GV of the turn-on pixel SP during one frame or during the first to eighth periods t1 to t 8. The second and third lighting voltages DC2 and DC3 may maintain the black voltage BV of the off pixel SP during one frame or during the first to eighth periods t1 to t 8. The pixels SP may be turned on when the pixels SP receive the gray voltages GV from the data lines DL, and may be turned off when the pixels SP receive the black voltages BV from the data lines DL.

The first test gate signal TG1 may maintain the gate low voltage VGL during the first, third, fifth and seventh periods t1, t3, t5 and t7, and may maintain the gate high voltage VGH during the second, fourth, sixth and eighth periods t2, t4, t6 and t 8. The second test gate signal TG2 may maintain the gate high voltage VGH during the first, third, fifth and seventh periods t1, t3, t5 and t7, and may maintain the gate low voltage VGL during the second, fourth, sixth and eighth periods t2, t4, t6 and t 8.

Referring to fig. 10, 17, 20, and 21, when a lighting check is performed on the first pixel RP of the first and second pixels RP and BP connected to the first or jth data line DL1 or DLj, the start signal STS may have the gate low voltage VGL during the first period t1 of one frame and may have the gate high voltage VGH during the second period t2 of one frame. The (2p-1) th stage STG (2p-1) may supply scan signals SC1, SC3, SC5,.. to the scan lines SL1, SL3, SL5,. in odd-numbered rows, and the 2p stage STG (2p) may not output the scan signals. The first lighting voltage DC1 may maintain the gray voltage GV during one frame, and the second and third lighting voltages DC2 and DC3 may maintain the black voltage BV during one frame. Accordingly, of the first and second pixels RP and BP connected to the first or jth data line DL1 or DLj, the first pixel RP connected to the scan line SL1, SL3, SL5,. in an odd-numbered row may be turned on, and the second pixel BP connected to the scan line SL2, SL4, SL6,. in an even-numbered row may be turned off. In one embodiment, for example, in the display device 10, after the first pixel RP connected to the first data line DL1 and the first scan line SL1 is turned on, by turning on the first pixel RP connected to the third scan line SL3 without turning on the second pixel BP connected to the second scan line SL2, the charging time of the first data line DL1 may be sufficiently secured. In such an embodiment of the display device 10, color mixing between the first pixel RP and the second pixel BP can be effectively prevented, and the reliability of the lighting inspection can be improved.

In an alternative embodiment, in the case where the display apparatus 10 includes the configuration of the first start signal STS1 of fig. 7 instead of the configuration of the start signal STS of fig. 17, the lighting inspection result of fig. 10 may be obtained.

Referring to fig. 14, 18, 20 and 21, when a lighting check is performed on the second pixels BP of the first and second pixels RP and BP connected to the first or jth data line DL1 or DLj, the start signal STS may have the gate high voltage VGH during the first period t1 of one frame and may have the gate low voltage VGL during the second period t2 of one frame. The 2 p-th stage STG (2p) may supply scan signals SC2, SC4, SC6,. to scan lines SL2, SL4, SL6,. in even rows, and the (2p-1) -th stage STG (2p-1) may not output the scan signals. The first lighting voltage DC1 may maintain the gray voltage GV during one frame, and the second and third lighting voltages DC2 and DC3 may maintain the black voltage BV during one frame. Accordingly, of the first and second pixels RP and BP connected to the first or jth data line DL1 or DLj, the second pixel BP connected to the scan lines SL2, SL4, SL6,. in even rows may be turned on, and the first pixel RP connected to the scan lines SL1, SL3, SL5,. in odd rows may be turned off. In one embodiment, for example, in the display device 10, after the second pixels BP connected to the first data line DL1 and the second scan line SL2 are turned on, by turning on the second pixels BP connected to the fourth scan line SL4 without turning on the first pixels RP connected to the third scan line SL3, the charging time of the first data line DL1 may be sufficiently secured. In such an embodiment of the display device 10, color mixing between the first pixel RP and the second pixel BP can be effectively prevented, and the reliability of the lighting inspection can be improved.

In an alternative embodiment, in the case where the display apparatus 10 includes the configuration of the second start signal STS2 of fig. 13 instead of the configuration of the start signal STS of fig. 18, the lighting inspection result of fig. 14 may be obtained.

Fig. 22 is a waveform diagram illustrating a lighting voltage and a test gate signal in a display device according to an alternative embodiment.

Referring to fig. 22, in the embodiment of the display apparatus 10, the lighting check may be performed on some of the plurality of pixels SP. In the display device 10, the first to third lighting voltages DC1, DC2, and DC3 may be supplied through the first to third test pads TP1, TP2, and TP3, and the first to third test gate signals TG1, TG2, and TG3 may be supplied through the first to third test gate pads TGP1, TGP2, and TGP 3.

The first and second lighting voltages DC1 and DC2 may maintain the black voltage BV of the turn-off pixel SP during one frame or during the first to eighth periods t1 to t 8. The third lighting voltage DC3 may maintain the gray voltage GV of the turn-on pixel SP during one frame or during the first to eighth periods t1 to t 8. The pixels SP may be turned on when the pixels SP receive the gray voltages GV from the data lines DL, and may be turned off when the pixels SP receive the black voltages BV from the data lines DL.

The first test gate signal TG1 may maintain the gate low voltage VGL during the first, third, fifth and seventh periods t1, t3, t5 and t7, and may maintain the gate high voltage VGH during the second, fourth, sixth and eighth periods t2, t4, t6 and t 8. The second test gate signal TG2 may maintain the gate high voltage VGH during the first, third, fifth and seventh periods t1, t3, t5 and t7, and may maintain the gate low voltage VGL during the second, fourth, sixth and eighth periods t2, t4, t6 and t 8.

Referring to fig. 12, 17, 20 and 21, when a lighting check is performed on the first pixel RP and the second pixel BP among the first and second pixels BP connected to the third or (j +2) th data line DL3 or DLj +2, the start signal STS may have the gate low voltage VGL during the first period t1 of one frame and may have the gate high voltage VGH during the second period t2 of one frame. The (2p-1) th stage STG (2p-1) may supply scan signals SC1, SC3, SC5,.. to the scan lines SL1, SL3, SL5,. in odd-numbered rows, and the 2p stage STG (2p) may not output the scan signals. The first and second lighting voltages DC1 and DC2 may maintain the black voltage BV during one frame, and the third lighting voltage DC3 may maintain the gray voltage GV during one frame. Accordingly, of the first and second pixels RP and BP connected to the third or (j +2) th data line DL3 or DLj +2, the second pixel BP connected to the scan line SL1, SL3, SL5,. in the odd-numbered rows may be turned on, and the first pixel RP connected to the scan line SL2, SL4, SL6,. in the even-numbered rows may be turned off. In one embodiment, for example, in the display device 10, after the second pixel BP connected to the third data line DL3 and the first scan line SL1 is turned on, by turning on the second pixel BP connected to the third scan line SL3 without turning on the first pixel RP connected to the second scan line SL2, the charging time of the third data line DL3 may be sufficiently secured. In such an embodiment of the display device 10, color mixing between the first pixel RP and the second pixel BP can be effectively prevented, and the reliability of the lighting inspection can be improved.

In an alternative embodiment, in the case where the display apparatus 10 includes the configuration of the first start signal STS1 of fig. 7 instead of the configuration of the start signal STS of fig. 17, the lighting inspection result of fig. 10 may be obtained.

Referring to fig. 15, 18, 20, and 21, when a lighting check is performed on the first pixel RP of the first and second pixels RP and BP connected to the third or (j +2) th data line DL3 or DLj +2, the start signal STS may have the gate high voltage VGH during the first period t1 of one frame and may have the gate low voltage VGL during the second period t2 of one frame. The 2 p-th stage STG (2p) may supply scan signals SC2, SC4, SC6,. to scan lines SL2, SL4, SL6,. in even rows, and the (2p-1) -th stage STG (2p-1) may not output the scan signals. The first and second lighting voltages DC1 and DC2 may maintain the black voltage BV during one frame, and the third lighting voltage DC3 may maintain the gray voltage GV during one frame. Accordingly, among the first and second pixels RP and BP connected to the third or (j +2) th data line DL3 or DLj +2, the first pixel RP connected to the scan line SL2, SL4, SL6,. in even-numbered rows may be turned on, and the second pixel BP connected to the scan line SL1, SL3, SL5,. in odd-numbered rows may be turned off. In one embodiment, for example, in the display device 10, after the first pixels RP connected to the third data line DL3 and the second scan line SL2 are turned on, by turning on the first pixels RP connected to the fourth scan line SL4 without turning on the second pixels BP connected to the third scan line SL3, the charging time of the third data line DL3 may be sufficiently secured. In such an embodiment of the display device 10, color mixing between the first pixel RP and the second pixel BP can be effectively prevented, and the reliability of the lighting inspection can be improved.

In an alternative embodiment, in the case where the display apparatus 10 includes the configuration of the second start signal STS2 of fig. 13 instead of the configuration of the start signal STS of fig. 18, the lighting inspection result of fig. 14 may be obtained.

According to an embodiment of a display device, as described herein, the display device may include first and second pixels connected to the same data line to emit light of colors different from each other and a scan driver supplying a scan signal to one of the first and second pixels. When the lighting voltage is supplied to the data line, the display device may supply the lighting voltage to one of the first pixel and the second pixel, and sufficiently secure a charging time of the data line. Therefore, the display device can effectively prevent color mixing between the first pixel and the second pixel, and can improve the reliability of the lighting inspection of the first pixel and the second pixel.

The present invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

While the present invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit or scope of the present invention as defined by the following claims.