1. The control system of the medical thermal film printer is characterized by comprising a printer main body, a processor U2 for controlling the work of the printer main body, a processor U3 connected with the processor U2, a processor U4 and a processor U5; the processor U2 is connected with a PCIe expansion interface P1; the processor U4 is connected with a printing head control interface P3; the processor U5 is connected to a plurality of stepper motor interfaces.

2. The medical thermographic film printer control system of claim 1, wherein the 42 th pin, the 41 th pin, the 40 th pin, the 39 th pin, the 38 th pin, the 37 th pin, the 32 th pin, the 31 st pin, the 30 th pin, the 29 th pin, the 28 th pin and the 27 th pin of the processor U2 are connected to the 22 nd pin, the 23 rd pin, the 24 th pin, the 25 th pin, the 26 th pin, the 27 th pin, the 28 th pin, the 29 th pin, the 30 th pin, the 31 st pin, the 32 th pin and the 33 rd pin of the PCIe expansion interface P1, respectively;

the 43 rd pin, the 44 th pin, the 45 th pin, the 48 th pin, the 49 th pin, the 50 th pin, the 51 th pin, the 52 th pin, the 53 th pin, the 55 th pin, the 57 th pin, the 58 th pin, the 59 th pin, the 60 th pin, the 61 st pin, the 62 th pin, the 63 rd pin and the 66 th pin of the processor U2 are respectively connected with the 21 st pin, the 20 th pin, the 19 th pin, the 18 th pin, the 17 th pin, the 16 th pin, the 14 th pin, the 13 th pin, the 12 th pin, the 11 th pin, the 10 th pin, the 9 th pin, the 7 th pin, the 6 th pin, the 5 th pin, the 4 th pin, the 3 rd pin and the 2 nd pin of the PCIe expansion interface P1;

the 23 rd pin and the 24 th pin of the processor U2 are respectively connected with the 35 th pin and the 34 th pin of the PCIe expansion interface P1; the 21 st pin of the processor U2 is connected with the 39 th pin of the PCIe expansion interface P1; the 38 th pin of the PCIe expansion interface P1 is connected with one end of a resistor R1, and the other end of the resistor R1 is connected with the 22 nd pin of the processor U2.

3. The control system of the medical thermal film printer according to claim 2, wherein the 29 th pin, the 28 th pin, the 27 th pin, the 26 th pin, the 25 th pin, the 24 th pin, the 22 nd pin, the 21 st pin, the 19 th pin, the 18 th pin, the 17 th pin, the 16 th pin, the 15 th pin, the 13 th pin, the 12 th pin, the 11 th pin and the 10 th pin of the processor U3 are respectively connected with the 88 th pin, the 89 th pin, the 91 st pin, the 93 rd pin, the 94 th pin, the 95 th pin, the 96 th pin, the 97 th pin, the 98 th pin, the 101 th pin, the 102 th pin, the 103 th pin, the 104 th pin, the 105 th pin, the 106 th pin, the 107 th pin and the 108 th pin of the processor U2;

the 31 st pin, the 32 nd pin, the 34 th pin, the 35 th pin, the 37 th pin, the 38 th pin, the 40 th pin, the 41 th pin, the 42 th pin, the 43 th pin, the 45 th pin, the 47 th pin, the 49 th pin, the 50 th pin, the 52 th pin, the 53 th pin, the 56 th pin and the 57 th pin of the processor U3 are respectively connected with the 87 th pin, the 86 th pin, the 85 th pin, the 84 th pin, the 81 th pin, the 80 th pin, the 79 th pin, the 78 th pin, the 77 th pin, the 76 th pin, the 75 th pin, the 74 th pin, the 73 th pin, the 72 th pin, the 71 th pin, the 70 th pin, the 69 th pin and the 68 th pin of the processor U2;

the 62 nd pin and the 80 th pin of the processor U3 are respectively connected with the 114 th pin and the 110 th pin of the processor U2; the 64 th pin and the 74 th pin of the processor U3 are respectively connected with the 113 th pin and the 112 th pin of the processor U2; the 78 th pin and the 79 th pin of the processor U3 are both connected with the 111 th pin of the processor U2;

the 7 th pin, the 14 th pin, the 46 th pin, the 48 th pin, the 54 th pin, the 55 th pin, the 23 rd pin, the 30 th pin, the 33 th pin, the 39 th pin, the 61 st pin, the 63 rd pin, the 65 th pin, the 69 th pin and the 72 th pin of the processor U3 are all connected with an OGND end;

the 2 nd pin, the 4 th pin, the 36 th pin, the 67 th pin, the 70 th pin, the 77 th pin, the 9 th pin, the 20 th pin, the 44 th pin, the 51 st pin, the 58 th pin and the 60 th pin of the processor U3 are all connected with a +3.3V end.

4. The control system for medical thermographic film printer of claim 3 wherein the processor U3 is further connected to a resistor R3, a resistor R4, and a resistor R5;

the pin 6 of the processor U3 is connected with one end of a resistor R3, the pin 76 of the processor U3 is connected with one end of a resistor R4, the pin 73 of the processor U3 is connected with one end of a resistor R5, and the other ends of the resistor R3, the resistor R4 and the resistor R5 are connected with an OGND end.

5. The control system of medical thermographic film printer according to claim 4, wherein pin 9, pin 8, pin 6, pin 5, pin 3, and pin 2 of the processor U4 are connected to pin 12, pin 10, pin 8, pin 6, pin 4, and pin 2 of printhead control interface P3, respectively;

the 40 th pin, the 41 th pin, the 43 th pin, the 44 th pin, the 46 th pin and the 47 th pin of the processor U4 are respectively connected with the 122 th pin, the 121 th pin, the 120 th pin, the 119 th pin, the 118 th pin and the 117 th pin of the processor U2;

the 35 th pin and the 36 th pin of the processor U4 are respectively connected with the 123 th pin and the 124 th pin of the processor U2; the 33 rd pin and the 32 th pin of the processor U4 are respectively connected with the 125 th pin and the 127 th pin of the processor U2; the 30 th pin and the 29 th pin of the processor U4 are respectively connected with the 129 th pin and the 130 th pin of the processor U2; the 26 th pin and the 27 th pin of the processor U4 are respectively connected with the 131 st pin and the 132 th pin of the processor U2; the 25 th pin and the 48 th pin of the processor U4 are both connected with the 133 th pin of the processor U2; the 4 th, 10 th, 15 th and 21 st pins of the processor U4 are connected to ground, respectively.

6. The control system of medical thermographic film printer according to claim 5, wherein pin 13 and pin 14 of the processor U4 are connected to pin 15 and pin 17, respectively, of a printhead control interface P3; the 16 th pin and the 17 th pin of the processor U4 are connected with the 19 th pin and the 20 th pin of the printing head control interface P3 respectively; the 19 th and 20 th pins of processor U4 are connected to the 22 nd and 23 rd pins, respectively, of printhead control interface P3.

7. The medical thermographic film printer control system of claim 6, wherein a resistor R6, a resistor R7, a capacitor C9, and a capacitor C10 are also connected to the processor U4;

the 1 st pin of the processor U4 is connected with one end of a resistor R6, and the other end of the resistor R6 is connected with a +3.3V end; a 48 th pin of the processor U4 is connected with one end of a resistor R7, and the other end of the resistor R7 is connected with a +3.3V end; the 7 th pin of the processor U4 is connected with one end of a capacitor C9, and the other end of the capacitor C9 is connected with a GND terminal; the 42 th pin of the processor U4 is connected to one end of a capacitor C10, and the other end of the capacitor C10 is connected to the OGND terminal.

8. The control system for medical thermal film printer according to claim 7, wherein the print head control interface P3 is connected with a current output terminal P2 and a logic power supply P4;

the 1 st pin, the 3 rd pin, the 5 th pin, the 7 th pin and the 9 th pin of the current output terminal P2 are all connected with the 44 th pin of a printing head control interface P3;

pin 1 of the logic power supply P4 is connected to pin 46 of printhead control interface P3.

9. The control system of the medical thermographic film printer according to claim 8, wherein the 95 th pin, the 96 th pin, the 97 th pin, the 98 th pin, the 99 th pin, the 100 th pin, the 1 st pin and the 2 nd pin of the processor U5 are connected to the 14 th pin, the 13 th pin, the 12 th pin, the 11 th pin, the 8 th pin, the 7 th pin, the 6 th pin and the 5 th pin of the processor U2, respectively;

the No. 3 pin, the No. 4 pin, the No. 5 pin, the No. 6 pin, the No. 7 pin, the No. 8 pin, the No. 14 pin and the No. 15 pin of the processor U5 are respectively connected with the No. 4 pin, the No. 3 pin, the No. 2 pin, the No. 1 pin, the No. 144 pin, the No. 143 pin, the No. 141 pin and the No. 140 pin of the processor U2; the 30 th and 40 th pins of the processor U5 are connected to the 134 th and 40 th pins of the processor U2.

10. The medical thermographic film printer control system of claim 9, wherein a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C16, and a polarity capacitor C41 are also connected to the processor U5;

the 11 th pin and the 13 th pin of the processor U5 are respectively connected with two ends of a capacitor C11; the 31 st pin and the 32 nd pin of the processor U5 are respectively connected with two ends of a capacitor C12; the 93 rd pin and the 94 th pin of the processor U5 are respectively connected with two ends of the capacitor C13; the 63 st pin and the 65 th pin of the processor U5 are respectively connected with two ends of a capacitor C16; the 9 th pin and the 10 th pin of the processor U5 are respectively connected with the positive pole and the negative pole of the polarity capacitor C41.

11. The medical thermal film printer control system of claim 10 wherein the stepper motor interface comprises stepper motor interface P5, stepper motor interface P6, stepper motor interface P7, stepper motor interface P8, stepper motor interface P9, stepper motor interface P10, stepper motor interface P11, and stepper motor interface P12;

the 49 th pin, the 50 th pin and the 51 th pin of the processor U5 are respectively connected with the 2 nd pin, the 3 rd pin and the 4 th pin of the stepping motor interface P5; the 52 nd pin, the 53 th pin and the 54 th pin of the processor U5 are respectively connected with the 2 nd pin, the 3 rd pin and the 4 th pin of the stepping motor interface P6; the 55 th pin, the 56 th pin and the 57 th pin of the processor U5 are respectively connected with the 2 nd pin, the 3 rd pin and the 4 th pin of the stepping motor interface P7; the 58 th pin, the 61 st pin and the 66 th pin of the processor U5 are respectively connected with the 2 nd pin, the 3 rd pin and the 4 th pin of the stepping motor interface P8; the 67 th pin, the 68 th pin and the 69 th pin of the processor U5 are respectively connected with the 2 nd pin, the 3 rd pin and the 4 th pin of the stepping motor interface P9; the 70 th pin, the 71 th pin and the 72 th pin of the processor U5 are respectively connected with the 2 nd pin, the 3 rd pin and the 4 th pin of the stepping motor interface P10; the 73 rd pin, the 74 th pin and the 75 th pin of the processor U5 are respectively connected with the 2 nd pin, the 3 rd pin and the 4 th pin of the stepping motor interface P11; the 73 rd pin, the 74 th pin and the 75 th pin of the processor U5 are respectively connected with the 2 nd pin, the 3 rd pin and the 4 th pin of the stepping motor interface P11; the 76 th pin, the 77 th pin and the 78 th pin of the processor U5 are respectively connected with the 2 nd pin, the 3 rd pin and the 4 th pin of the stepping motor interface P12; first pins of a stepping motor interface P5, a stepping motor interface P6, a stepping motor interface P7, a stepping motor interface P8, a stepping motor interface P9, a stepping motor interface P10, a stepping motor interface P11 and a stepping motor interface P12 are all connected with the end of VDD 5V.

12. The medical thermographic film printer control system of claim 11, wherein a capacitor C4, a capacitor C6, a capacitor C2, and a capacitor C3 are connected to the processor U2;

the 54 th pin and the 56 th pin of the processor U2 are respectively connected with two ends of a capacitor C4; the 90 th pin and the 92 th pin of the processor U2 are respectively connected with two ends of the capacitor C6; the 17 th pin and the 19 th pin of the processor U2 are respectively connected with two ends of a capacitor C2; the 128 th pin and the 126 th pin of the processor U2 are respectively connected with two ends of the capacitor C3.

Background

The thermal printer works on the principle that a semiconductor heating element is arranged on a printing head, the printing head can print required patterns after being heated and contacted with thermal printing paper, the principle is similar to that of a thermal fax machine, the images are generated by heating and generating chemical reaction in a film, the chemical reaction of the thermal printer is carried out at a certain temperature, the high temperature can accelerate the chemical reaction, when the temperature is lower than 60 ℃, the paper can be changed into dark color after a long time, even for several years, and when the temperature is 200 ℃, the reaction can be completed within a few microseconds.

Because the quality of the thermal paper used in the market at present is uneven, and the thermal paint used on the surface of the thermal paper is different, the same effect cannot be printed out when the same thermal printer product uses thermal paper consumables of different models, the thermal printing depth needs to be manually reset, and the printing depth is continuously adjusted, so that the better printing effect can be realized. Known thermal printers and thermal transfer printers generally lack a function, namely, an automatic paper feeding function. The paper feeding mode is that the printing paper is manually passed through the printing medium channel and placed at the printing preparation position. Since the printing channel is generally narrower than the printing channel, this method of feeding paper is obviously very inconvenient, and more importantly: when printing, especially when printing a valuable ticket, the requirement on the position precision of paper is high, and the position precision is difficult to meet by manually feeding paper, so that the first printing effect is often poor.

Therefore, how to design a control system of a medical thermosensitive film printer is an urgent need to be solved at present.

Disclosure of Invention

The present invention is directed to a control system for a thermal print film printer for medical use, which solves the above-mentioned problems of the prior art.

The embodiment of the invention is realized by the following steps:

the embodiment of the application provides a control system of a medical thermal film printer, which comprises a printer main body, a processor U2 for controlling the printer main body to work, and a processor U3, a processor U4 and a processor U5 which are connected with the processor U2; the processor U2 is connected with a PCIe expansion interface P1; the processor U4 is connected with a printing head control interface P3; a plurality of stepper motor interfaces are connected to the processor U5.

In some embodiments of the present invention, the 42 th pin, the 41 th pin, the 40 th pin, the 39 th pin, the 38 th pin, the 37 th pin, the 32 th pin, the 31 th pin, the 30 th pin, the 29 th pin, the 28 th pin and the 27 th pin of the processor U2 are respectively connected to the 22 nd pin, the 23 rd pin, the 24 th pin, the 25 th pin, the 26 th pin, the 27 th pin, the 28 th pin, the 29 th pin, the 30 th pin, the 31 th pin, the 32 th pin and the 33 th pin of the PCIe expansion interface P1;

the 43 rd pin, the 44 th pin, the 45 th pin, the 48 th pin, the 49 th pin, the 50 th pin, the 51 th pin, the 52 th pin, the 53 th pin, the 55 th pin, the 57 th pin, the 58 th pin, the 59 th pin, the 60 th pin, the 61 st pin, the 62 nd pin, the 63 rd pin and the 66 th pin of the processor U2 are respectively connected with the 21 st pin, the 20 th pin, the 19 th pin, the 18 th pin, the 17 th pin, the 16 th pin, the 14 th pin, the 13 th pin, the 12 th pin, the 11 th pin, the 10 th pin, the 9 th pin, the 7 th pin, the 6 th pin, the 5 th pin, the 4 th pin, the 3 rd pin and the 2 nd pin of the PCIe expansion interface P1;

the 23 rd pin and the 24 th pin of the processor U2 are respectively connected with the 35 th pin and the 34 th pin of a PCIe expansion interface P1; the 21 st pin of the processor U2 is connected with the 39 th pin of a PCIe expansion interface P1; the 38 th pin of the PCIe expansion interface P1 is connected with one end of the resistor R1, and the other end of the resistor R1 is connected with the 22 nd pin of the processor U2.

In some embodiments of the present invention, the 29 th pin, the 28 th pin, the 27 th pin, the 26 th pin, the 25 th pin, the 24 th pin, the 22 th pin, the 21 st pin, the 19 th pin, the 18 th pin, the 17 th pin, the 16 th pin, the 15 th pin, the 13 th pin, the 12 th pin, the 11 th pin and the 10 th pin of the processor U3 are respectively connected to the 88 th pin, the 89 th pin, the 91 st pin, the 93 th pin, the 94 th pin, the 95 th pin, the 96 th pin, the 97 th pin, the 98 th pin, the 101 th pin, the 102 th pin, the 103 th pin, the 104 th pin, the 105 th pin, the 106 th pin, the 107 th pin and the 108 th pin of the processor U2;

the 31 st pin, the 32 nd pin, the 34 th pin, the 35 th pin, the 37 th pin, the 38 th pin, the 40 th pin, the 41 th pin, the 42 th pin, the 43 th pin, the 45 th pin, the 47 th pin, the 49 th pin, the 50 th pin, the 52 th pin, the 53 th pin, the 56 th pin and the 57 th pin of the processor U3 are respectively connected with the 87 th pin, the 86 th pin, the 85 th pin, the 84 th pin, the 81 th pin, the 80 th pin, the 79 th pin, the 78 th pin, the 77 th pin, the 76 th pin, the 75 th pin, the 74 th pin, the 73 th pin, the 72 th pin, the 71 th pin, the 70 th pin, the 69 th pin and the 68 th pin of the processor U2;

the 62 nd pin and the 80 th pin of the processor U3 are respectively connected with the 114 th pin and the 110 th pin of the processor U2; the 64 th pin and the 74 th pin of the processor U3 are respectively connected with the 113 th pin and the 112 th pin of the processor U2; the 78 th pin and the 79 th pin of the processor U3 are both connected with the 111 th pin of the processor U2;

the 7 th pin, the 14 th pin, the 46 th pin, the 48 th pin, the 54 th pin, the 55 th pin, the 23 rd pin, the 30 th pin, the 33 th pin, the 39 th pin, the 61 st pin, the 63 rd pin, the 65 th pin, the 69 th pin and the 72 th pin of the processor U3 are all connected with the OGND end;

the 2 nd pin, the 4 th pin, the 36 th pin, the 67 th pin, the 70 th pin, the 77 th pin, the 9 th pin, the 20 th pin, the 44 th pin, the 51 st pin, the 58 th pin and the 60 th pin of the processor U3 are all connected with a +3.3V end.

In some embodiments of the present invention, the processor U3 is further connected to a resistor R3, a resistor R4 and a resistor R5;

the pin 6 of the processor U3 is connected with one end of a resistor R3, the pin 76 of the processor U3 is connected with one end of a resistor R4, the pin 73 of the processor U3 is connected with one end of a resistor R5, and the other ends of the resistor R3, the resistor R4 and the resistor R5 are connected with an OGND end.

In some embodiments of the present invention, the 9 th pin, the 8 th pin, the 6 th pin, the 5 th pin, the 3 rd pin and the 2 nd pin of the processor U4 are respectively connected to the 12 th pin, the 10 th pin, the 8 th pin, the 6 th pin, the 4 th pin and the 2 nd pin of the printhead control interface P3;

the 40 th pin, the 41 th pin, the 43 th pin, the 44 th pin, the 46 th pin and the 47 th pin of the processor U4 are respectively connected with the 122 th pin, the 121 th pin, the 120 th pin, the 119 th pin, the 118 th pin and the 117 th pin of the processor U2;

the 35 th pin and the 36 th pin of the processor U4 are respectively connected with the 123 th pin and the 124 th pin of the processor U2; the 33 rd pin and the 32 th pin of the processor U4 are respectively connected with the 125 th pin and the 127 th pin of the processor U2; the 30 th pin and the 29 th pin of the processor U4 are respectively connected with the 129 th pin and the 130 th pin of the processor U2; the 26 th pin and the 27 th pin of the processor U4 are respectively connected with the 131 st pin and the 132 th pin of the processor U2; the 25 th pin and the 48 th pin of the processor U4 are both connected with the 133 th pin of the processor U2; the 4 th, 10 th, 15 th and 21 st pins of the processor U4 are connected to ground, respectively.

In some embodiments of the present invention, the 13 th pin and the 14 th pin of the processor U4 are connected to the 15 th pin and the 17 th pin of the printhead control interface P3, respectively; the 16 th pin and the 17 th pin of the processor U4 are connected with the 19 th pin and the 20 th pin of the printing head control interface P3 respectively; the 19 th and 20 th pins of processor U4 are connected to the 22 nd and 23 rd pins, respectively, of printhead control interface P3.

In some embodiments of the present invention, the processor U4 is further connected to a resistor R6, a resistor R7, a capacitor C9, and a capacitor C10;

the 1 st pin of the processor U4 is connected with one end of a resistor R6, and the other end of the resistor R6 is connected with a +3.3V end; a 48 th pin of the processor U4 is connected with one end of a resistor R7, and the other end of the resistor R7 is connected with a +3.3V end; the 7 th pin of the processor U4 is connected with one end of a capacitor C9, and the other end of the capacitor C9 is connected with a GND terminal; the 42 th pin of the processor U4 is connected to one end of a capacitor C10, and the other end of the capacitor C10 is connected to the OGND terminal.

In some embodiments of the present invention, the printhead control interface P3 is connected to a current output terminal P2 and a logic power supply P4;

the 1 st pin, the 3 rd pin, the 5 th pin, the 7 th pin and the 9 th pin of the current output terminal P2 are all connected with the 44 th pin of a printing head control interface P3;

pin 1 of logic power supply P4 is connected to pin 46 of printhead control interface P3.

In some embodiments of the present invention, the 95 th pin, the 96 th pin, the 97 th pin, the 98 th pin, the 99 th pin, the 100 th pin, the 1 st pin and the 2 nd pin of the processor U5 are respectively connected to the 14 th pin, the 13 th pin, the 12 th pin, the 11 th pin, the 8 th pin, the 7 th pin, the 6 th pin and the 5 th pin of the processor U2;

the No. 3 pin, the No. 4 pin, the No. 5 pin, the No. 6 pin, the No. 7 pin, the No. 8 pin, the No. 14 pin and the No. 15 pin of the processor U5 are respectively connected with the No. 4 pin, the No. 3 pin, the No. 2 pin, the No. 1 pin, the No. 144 pin, the No. 143 pin, the No. 141 pin and the No. 140 pin of the processor U2; the 30 th and 40 th pins of the processor U5 are connected to the 134 th and 40 th pins of the processor U2.

In some embodiments of the present invention, the processor U5 is further connected to a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C16 and a polarity capacitor C41;

the 11 th pin and the 13 th pin of the processor U5 are respectively connected with two ends of a capacitor C11; the 31 st pin and the 32 nd pin of the processor U5 are respectively connected with two ends of a capacitor C12; the 93 rd pin and the 94 th pin of the processor U5 are respectively connected with two ends of the capacitor C13; the 63 st pin and the 65 th pin of the processor U5 are respectively connected with two ends of a capacitor C16; the 9 th pin and the 10 th pin of the processor U5 are respectively connected with the positive pole and the negative pole of the polarity capacitor C41.

In some embodiments of the present invention, the stepping motor interface includes a stepping motor interface P5, a stepping motor interface P6, a stepping motor interface P7, a stepping motor interface P8, a stepping motor interface P9, a stepping motor interface P10, a stepping motor interface P11, and a stepping motor interface P12;

the 49 th pin, the 50 th pin and the 51 th pin of the processor U5 are respectively connected with the 2 nd pin, the 3 rd pin and the 4 th pin of the stepping motor interface P5; the 52 nd pin, the 53 th pin and the 54 th pin of the processor U5 are respectively connected with the 2 nd pin, the 3 rd pin and the 4 th pin of the stepping motor interface P6; the 55 th pin, the 56 th pin and the 57 th pin of the processor U5 are respectively connected with the 2 nd pin, the 3 rd pin and the 4 th pin of the stepping motor interface P7; the 58 th pin, the 61 st pin and the 66 th pin of the processor U5 are respectively connected with the 2 nd pin, the 3 rd pin and the 4 th pin of the stepping motor interface P8; the 67 th pin, the 68 th pin and the 69 th pin of the processor U5 are respectively connected with the 2 nd pin, the 3 rd pin and the 4 th pin of the stepping motor interface P9; the 70 th pin, the 71 th pin and the 72 th pin of the processor U5 are respectively connected with the 2 nd pin, the 3 rd pin and the 4 th pin of the stepping motor interface P10; the 73 rd pin, the 74 th pin and the 75 th pin of the processor U5 are respectively connected with the 2 nd pin, the 3 rd pin and the 4 th pin of the stepping motor interface P11; the 73 rd pin, the 74 th pin and the 75 th pin of the processor U5 are respectively connected with the 2 nd pin, the 3 rd pin and the 4 th pin of the stepping motor interface P11; the 76 th pin, the 77 th pin and the 78 th pin of the processor U5 are respectively connected with the 2 nd pin, the 3 rd pin and the 4 th pin of the stepping motor interface P12; first pins of a stepping motor interface P5, a stepping motor interface P6, a stepping motor interface P7, a stepping motor interface P8, a stepping motor interface P9, a stepping motor interface P10, a stepping motor interface P11 and a stepping motor interface P12 are all connected with the end of VDD 5V.

In some embodiments of the present invention, the processor U2 is connected to a capacitor C4, a capacitor C6, a capacitor C2 and a capacitor C3;

the 54 th pin and the 56 th pin of the processor U2 are respectively connected with two ends of the capacitor C4; the 90 th pin and the 92 th pin of the processor U2 are respectively connected with two ends of the capacitor C6; the 17 th pin and the 19 th pin of the processor U2 are respectively connected with two ends of a capacitor C2; the 128 th pin and the 126 th pin of the processor U2 are respectively connected with two ends of the capacitor C3.

Compared with the prior art, the embodiment of the invention has at least the following advantages or beneficial effects: through the control of the control system to the printer main body, complicated manual operation can be reduced, the situation that the thermal sensitive printing depth needs to be set manually is avoided, the printing depth is continuously adjusted, a better printing effect can be realized, and the printing precision of the film during printing is improved after each set of mechanism series of the printer main body operates.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

FIG. 1 is a schematic structural diagram of a printer body according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a PCIe expansion interface P1 in the embodiment of the invention;

FIG. 3 is a schematic diagram of another connection of a PCIe expansion interface P1 in the embodiment of the invention;

FIG. 4 is a schematic diagram of the connection of a processor U5 according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of the connection of a processor U2 according to an embodiment of the present invention;

FIG. 6 is a schematic connection diagram of an interface of a stepping motor according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of the connection of a sensor in an embodiment of the invention;

FIG. 8 is a schematic diagram of the connection of a sensor to processor U12 in an embodiment of the present invention;

FIG. 9 is a schematic diagram of the connection of processor U3 according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of the connection of processor U4 and printhead control interface P3 in an embodiment of the present invention;

FIG. 11 is a schematic diagram of power supply connections in an embodiment of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

In the description of the present application, it should be noted that the terms "upper", "lower", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships conventionally found in use of products of the application, and are used only for convenience in describing the present application and for simplification of description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present application.

In the description of the present application, it is also to be noted that, unless otherwise explicitly specified or limited, the terms "disposed" and "connected" are to be interpreted broadly, e.g., as being either fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the individual features of the embodiments can be combined with one another without conflict.

Examples

Referring to fig. 1 to 10, fig. 1 is a schematic structural diagram of a printer body according to an embodiment of the invention;

FIG. 2 is a schematic diagram of a PCIe expansion interface P1 in the embodiment of the invention; FIG. 3 is a schematic diagram of another connection of a PCIe expansion interface P1 in the embodiment of the invention; FIG. 4 is a schematic diagram of the connection of a processor U5 according to an embodiment of the present invention; FIG. 5 is a schematic diagram of the connection of a processor U2 according to an embodiment of the present invention; FIG. 6 is a schematic connection diagram of an interface of a stepping motor according to an embodiment of the present invention; FIG. 7 is a schematic diagram of the connection of a sensor in an embodiment of the invention; FIG. 8 is a schematic diagram of the connection of a sensor to processor U12 in an embodiment of the present invention; FIG. 9 is a schematic diagram of the connection of processor U3 according to an embodiment of the present invention; FIG. 10 is a schematic diagram of the connection of processor U4 and printhead control interface P3 in an embodiment of the present invention; FIG. 11 is a schematic diagram of power supply connections in an embodiment of the invention.

The embodiment of the application provides a control system of a medical thermal film printer, which comprises a printer main body, a processor U2 for controlling the printer main body to work, a processor U3, a processor U4 and a processor U5, wherein the processor U3 is connected with the processor U2; the processor U2 is connected with a PCIe expansion interface P1; the processor U4 is connected with a printing head control interface P3; a plurality of stepper motor interfaces are connected to the processor U5.

The processor U2 is used for printing control, the processor U5 is used for assisting printing control, a stepping motor interface and a connecting motor, and the printing operation is realized by the control of the processor on the motor; processor U3 is for caching of print data; the processor U4 is connected to the processor U2 and the printhead control interface P3, thereby realizing the operation of printing.

In this embodiment, the 42 th pin, the 41 th pin, the 40 th pin, the 39 th pin, the 38 th pin, the 37 th pin, the 32 th pin, the 31 th pin, the 30 th pin, the 29 th pin, the 28 th pin and the 27 th pin of the processor U2 are respectively connected with the 22 nd pin, the 23 rd pin, the 24 th pin, the 25 th pin, the 26 th pin, the 27 th pin, the 28 th pin, the 29 th pin, the 30 th pin, the 31 th pin, the 32 th pin and the 33 rd pin of the PCIe expansion interface P1;

the 43 rd pin, the 44 th pin, the 45 th pin, the 48 th pin, the 49 th pin, the 50 th pin, the 51 th pin, the 52 th pin, the 53 th pin, the 55 th pin, the 57 th pin, the 58 th pin, the 59 th pin, the 60 th pin, the 61 st pin, the 62 nd pin, the 63 rd pin and the 66 th pin of the processor U2 are respectively connected with the 21 st pin, the 20 th pin, the 19 th pin, the 18 th pin, the 17 th pin, the 16 th pin, the 14 th pin, the 13 th pin, the 12 th pin, the 11 th pin, the 10 th pin, the 9 th pin, the 7 th pin, the 6 th pin, the 5 th pin, the 4 th pin, the 3 rd pin and the 2 nd pin of the PCIe expansion interface P1;

the 23 rd pin and the 24 th pin of the processor U2 are respectively connected with the 35 th pin and the 34 th pin of a PCIe expansion interface P1; the 21 st pin of the processor U2 is connected with the 39 th pin of a PCIe expansion interface P1; the 38 th pin of the PCIe expansion interface P1 is connected with one end of the resistor R1, and the other end of the resistor R1 is connected with the 22 nd pin of the processor U2.

In this embodiment, the 29 th pin, the 28 th pin, the 27 th pin, the 26 th pin, the 25 th pin, the 24 th pin, the 22 nd pin, the 21 st pin, the 19 th pin, the 18 th pin, the 17 th pin, the 16 th pin, the 15 th pin, the 13 th pin, the 12 th pin, the 11 th pin and the 10 th pin of the processor U3 are respectively connected with the 88 th pin, the 89 th pin, the 91 st pin, the 93 rd pin, the 94 th pin, the 95 th pin, the 96 th pin, the 97 th pin, the 98 th pin, the 101 th pin, the 102 th pin, the 103 th pin, the 104 th pin, the 105 th pin, the 106 th pin, the 107 th pin and the 108 th pin of the processor U2;

the 31 st pin, the 32 nd pin, the 34 th pin, the 35 th pin, the 37 th pin, the 38 th pin, the 40 th pin, the 41 th pin, the 42 th pin, the 43 th pin, the 45 th pin, the 47 th pin, the 49 th pin, the 50 th pin, the 52 th pin, the 53 th pin, the 56 th pin and the 57 th pin of the processor U3 are respectively connected with the 87 th pin, the 86 th pin, the 85 th pin, the 84 th pin, the 81 th pin, the 80 th pin, the 79 th pin, the 78 th pin, the 77 th pin, the 76 th pin, the 75 th pin, the 74 th pin, the 73 th pin, the 72 th pin, the 71 th pin, the 70 th pin, the 69 th pin and the 68 th pin of the processor U2;

the 62 nd pin and the 80 th pin of the processor U3 are respectively connected with the 114 th pin and the 110 th pin of the processor U2; the 64 th pin and the 74 th pin of the processor U3 are respectively connected with the 113 th pin and the 112 th pin of the processor U2; the 78 th pin and the 79 th pin of the processor U3 are both connected with the 111 th pin of the processor U2;

the 7 th pin, the 14 th pin, the 46 th pin, the 48 th pin, the 54 th pin, the 55 th pin, the 23 rd pin, the 30 th pin, the 33 th pin, the 39 th pin, the 61 st pin, the 63 rd pin, the 65 th pin, the 69 th pin and the 72 th pin of the processor U3 are all connected with the OGND end;

the 2 nd pin, the 4 th pin, the 36 th pin, the 67 th pin, the 70 th pin, the 77 th pin, the 9 th pin, the 20 th pin, the 44 th pin, the 51 st pin, the 58 th pin and the 60 th pin of the processor U3 are all connected with a +3.3V end.

In this embodiment, the processor U3 is further connected with a resistor R3, a resistor R4 and a resistor R5;

the pin 6 of the processor U3 is connected with one end of a resistor R3, the pin 76 of the processor U3 is connected with one end of a resistor R4, the pin 73 of the processor U3 is connected with one end of a resistor R5, and the other ends of the resistor R3, the resistor R4 and the resistor R5 are connected with an OGND end.

In this embodiment, the 9 th pin, the 8 th pin, the 6 th pin, the 5 th pin, the 3 rd pin and the 2 nd pin of the processor U4 are respectively connected to the 12 th pin, the 10 th pin, the 8 th pin, the 6 th pin, the 4 th pin and the 2 nd pin of the printhead control interface P3;

the 40 th pin, the 41 th pin, the 43 th pin, the 44 th pin, the 46 th pin and the 47 th pin of the processor U4 are respectively connected with the 122 th pin, the 121 th pin, the 120 th pin, the 119 th pin, the 118 th pin and the 117 th pin of the processor U2;

the 35 th pin and the 36 th pin of the processor U4 are respectively connected with the 123 th pin and the 124 th pin of the processor U2; the 33 rd pin and the 32 th pin of the processor U4 are respectively connected with the 125 th pin and the 127 th pin of the processor U2; the 30 th pin and the 29 th pin of the processor U4 are respectively connected with the 129 th pin and the 130 th pin of the processor U2; the 26 th pin and the 27 th pin of the processor U4 are respectively connected with the 131 st pin and the 132 th pin of the processor U2; the 25 th pin and the 48 th pin of the processor U4 are both connected with the 133 th pin of the processor U2; the 4 th, 10 th, 15 th and 21 st pins of the processor U4 are connected to ground, respectively.

In this embodiment, the 13 th pin and the 14 th pin of the processor U4 are connected to the 15 th pin and the 17 th pin of the printhead control interface P3, respectively; the 16 th pin and the 17 th pin of the processor U4 are connected with the 19 th pin and the 20 th pin of the printing head control interface P3 respectively; the 19 th and 20 th pins of processor U4 are connected to the 22 nd and 23 rd pins, respectively, of printhead control interface P3.

In this embodiment, the processor U4 is further connected to a resistor R6, a resistor R7, a capacitor C9, and a capacitor C10;

the 1 st pin of the processor U4 is connected with one end of a resistor R6, and the other end of the resistor R6 is connected with a +3.3V end; a 48 th pin of the processor U4 is connected with one end of a resistor R7, and the other end of the resistor R7 is connected with a +3.3V end; the 7 th pin of the processor U4 is connected with one end of a capacitor C9, and the other end of the capacitor C9 is connected with a GND terminal; the 42 th pin of the processor U4 is connected to one end of a capacitor C10, and the other end of the capacitor C10 is connected to the OGND terminal.

In the present embodiment, the above-described printhead control interface P3 is connected with a current output terminal P2 and a logic power supply P4;

the 1 st pin, the 3 rd pin, the 5 th pin, the 7 th pin and the 9 th pin of the current output terminal P2 are all connected with the 44 th pin of a printing head control interface P3;

pin 1 of logic power supply P4 is connected to pin 46 of printhead control interface P3.

In this embodiment, the 95 th pin, the 96 th pin, the 97 th pin, the 98 th pin, the 99 th pin, the 100 th pin, the 1 st pin and the 2 nd pin of the processor U5 are respectively connected to the 14 th pin, the 13 th pin, the 12 th pin, the 11 th pin, the 8 th pin, the 7 th pin, the 6 th pin and the 5 th pin of the processor U2;

the No. 3 pin, the No. 4 pin, the No. 5 pin, the No. 6 pin, the No. 7 pin, the No. 8 pin, the No. 14 pin and the No. 15 pin of the processor U5 are respectively connected with the No. 4 pin, the No. 3 pin, the No. 2 pin, the No. 1 pin, the No. 144 pin, the No. 143 pin, the No. 141 pin and the No. 140 pin of the processor U2; the 30 th and 40 th pins of the processor U5 are connected to the 134 th and 40 th pins of the processor U2.

In this embodiment, the processor U5 is further connected to a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C16 and a polar capacitor C41;

the 11 th pin and the 13 th pin of the processor U5 are respectively connected with two ends of a capacitor C11; the 31 st pin and the 32 nd pin of the processor U5 are respectively connected with two ends of a capacitor C12; the 93 rd pin and the 94 th pin of the processor U5 are respectively connected with two ends of the capacitor C13; the 63 st pin and the 65 th pin of the processor U5 are respectively connected with two ends of a capacitor C16; the 9 th pin and the 10 th pin of the processor U5 are respectively connected with the positive pole and the negative pole of the polarity capacitor C41.

In this embodiment, the stepping motor interface includes a stepping motor interface P5, a stepping motor interface P6, a stepping motor interface P7, a stepping motor interface P8, a stepping motor interface P9, a stepping motor interface P10, a stepping motor interface P11, and a stepping motor interface P12;

the 49 th pin, the 50 th pin and the 51 th pin of the processor U5 are respectively connected with the 2 nd pin, the 3 rd pin and the 4 th pin of the stepping motor interface P5; the 52 nd pin, the 53 th pin and the 54 th pin of the processor U5 are respectively connected with the 2 nd pin, the 3 rd pin and the 4 th pin of the stepping motor interface P6; the 55 th pin, the 56 th pin and the 57 th pin of the processor U5 are respectively connected with the 2 nd pin, the 3 rd pin and the 4 th pin of the stepping motor interface P7; the 58 th pin, the 61 st pin and the 66 th pin of the processor U5 are respectively connected with the 2 nd pin, the 3 rd pin and the 4 th pin of the stepping motor interface P8; the 67 th pin, the 68 th pin and the 69 th pin of the processor U5 are respectively connected with the 2 nd pin, the 3 rd pin and the 4 th pin of the stepping motor interface P9; the 70 th pin, the 71 th pin and the 72 th pin of the processor U5 are respectively connected with the 2 nd pin, the 3 rd pin and the 4 th pin of the stepping motor interface P10; the 73 rd pin, the 74 th pin and the 75 th pin of the processor U5 are respectively connected with the 2 nd pin, the 3 rd pin and the 4 th pin of the stepping motor interface P11; the 73 rd pin, the 74 th pin and the 75 th pin of the processor U5 are respectively connected with the 2 nd pin, the 3 rd pin and the 4 th pin of the stepping motor interface P11; the 76 th pin, the 77 th pin and the 78 th pin of the processor U5 are respectively connected with the 2 nd pin, the 3 rd pin and the 4 th pin of the stepping motor interface P12; first pins of a stepping motor interface P5, a stepping motor interface P6, a stepping motor interface P7, a stepping motor interface P8, a stepping motor interface P9, a stepping motor interface P10, a stepping motor interface P11 and a stepping motor interface P12 are all connected with the end of VDD 5V.

In this embodiment, the processor U2 is connected to a capacitor C4, a capacitor C6, a capacitor C2 and a capacitor C3;

the 54 th pin and the 56 th pin of the processor U2 are respectively connected with two ends of the capacitor C4; the 90 th pin and the 92 th pin of the processor U2 are respectively connected with two ends of the capacitor C6; the 17 th pin and the 19 th pin of the processor U2 are respectively connected with two ends of a capacitor C2; the 128 th pin and the 126 th pin of the processor U2 are respectively connected with two ends of the capacitor C3.

In this embodiment, a plurality of sensors for sensing and a processor U12 for sensor connection are further disposed in the printer body, and referring to fig. 7 and 8, the connection between the sensors and the processor U12 and the connection between the processor U12 and other processors are shown in fig. 7 and 8.

Of course, a switching power supply for supplying power is also included, and the connection circuit thereof is as shown in fig. 11.

The processor may be an integrated circuit chip having signal processing capabilities. The Processor may be a general-purpose Processor including a Central Processing Unit (CPU), a Network Processor (NP), etc.; but also Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.