1. The method for upgrading the programmable logic device on line is characterized by being applied to a first programmable logic device, wherein the first programmable logic device comprises a first IO pin group, a second IO pin group and a first bus pin group, the first IO pin group is connected with the first bus pin group, the second IO pin group is connected with a serial port pin group of a CPU, and the method comprises the following steps:

receiving a target serial port signal which is sent by the CPU through the serial port pin group and carries an upgrade file through the second IO pin group;

determining a target bus signal corresponding to the target serial port signal based on a mapping relation between a preset serial port signal and a bus signal, wherein the target bus signal carries the upgrade file;

and sending the target bus signal to the first bus pin group through the first IO pin group so as to write the upgrade file into the first programmable logic device through the target bus signal.

2. The method of claim 1, wherein the first IO pin set comprises a first IO pin, a second IO pin, a third IO pin, and a fourth IO pin, and wherein the first bus pin set comprises a first TCK pin, a first TMS pin, a first TDI pin, and a first TDO pin; the first IO pin is connected with the TCK pin, the second IO pin is connected with the first TMS pin, the third IO pin is connected with the first TDI pin, and the fourth IO pin is connected with the first TDO pin;

the target bus signals comprise target TCK sub-signals, target TMS sub-signals and target TDI sub-signals, and the target TDI sub-signals carry the upgrade file;

the first IO pin group is configured to transmit the target bus signal to the first bus pin group, including:

and the target TCK sub-signal is sent to the first TCK pin through the first IO pin, the target TMS sub-signal is sent to the first TMS pin through the second IO pin, and the target TDI sub-signal is sent to the first TDI pin through the third IO pin.

3. The method of claim 2, wherein the first IO pin set is connected to a second bus pin set of at least one second programmable logic device, wherein the second bus pin set of each second programmable logic device comprises: the first TCK pin, the first TMS pin, the first TDI pin and the first TDO pin are connected in series;

the first IO pin is connected with a second TCK pin of each second programmable logic device, and the second IO pin is connected with a second TMS pin of each second programmable logic device;

and the first TDO pin is connected with a second TDI pin in a first-bit second programmable logic device; except the second programmable logic device positioned at the last bit, a second TDO pin in each second programmable logic device is connected with a second TDI pin in a second programmable logic device positioned at the next bit of the second programmable logic device; a second TDO pin in the second programmable logic device at the last bit is connected with the fourth IO pin;

the method further comprises the following steps:

the target TCK sub-signal is sent to each second TCK pin through the first IO pin, the target TMS sub-signal is sent to each second TMS pin through the second IO pin, and the target TDI sub-signal is sent to a second TDI pin in a first programmable logic device through the first TDO pin;

each second programmable logic device is used for sending the target TDI sub-signal to a second TDI pin of a second programmable logic which is positioned at the next bit of the second programmable logic device through a second TDO pin in the second programmable logic device; and determining whether the second programmable logic device is selected by the target TMS sub-signal according to the target TMS sub-signal, and if so, performing online upgrade according to the received target TCK sub-signal and the target TDI sub-signal.

4. The method of claim 3, wherein a driver is disposed between the first programmable logic device and the second programmable logic device, the driver being configured to redrive at least one of the target TCK sub-signal, the target TMS sub-signal, and the target TDI sub-signal.

5. The method of claim 2, wherein the second IO pin group comprises a fifth IO pin, a sixth IO pin, a seventh IO pin, and an eighth IO pin; the serial port pin group comprises a CLK pin, a MISO pin, a MOSI pin and a CS pin; the fifth IO pin is connected with the CLK pin, the sixth IO pin is connected with the MISO pin, the seventh IO pin is connected with the MOSI pin, and the eighth IO pin is connected with the CS pin;

the receiving, by the second IO pin group, the target serial port signal carrying the upgrade file sent by the CPU through the serial port pin group includes:

and writing a target serial port signal sent by the CPU through the MOSI pin into the first programmable logic device according to a timing signal sent by the CPU through the CLK pin and a control signal sent by the CS pin.

6. An online upgrade system for programmable logic devices, the system comprising: a CPU, a first programmable logic device;

the CPU comprises a serial port pin group, the first programmable logic device comprises a first IO pin group, a second IO pin group and a first bus pin group, the first IO pin group is connected with the first bus pin group, and the second IO pin group is connected with the serial port pin group;

the CPU is used for sending a target serial port signal carrying an upgrading file to the first programmable logic device through the serial port pin group;

the first programmable logic device is used for determining a target bus signal corresponding to the target serial port signal based on a mapping relation between a preset serial port signal and a bus signal, and the target bus signal carries the upgrade file; and sending the target bus signal to the first bus pin group through the first IO pin group so as to write the upgrade file into the first programmable logic device through the target bus signal.

7. The system of claim 6, wherein the first IO pin set comprises a first IO pin, a second IO pin, a third IO pin, and a fourth IO pin, the first bus pin set comprises a first TCK pin, a first TMS pin, a first TDI pin, and a first TDO pin; the first IO pin is connected with the TCK pin, the second IO pin is connected with the first TMS pin, the third IO pin is connected with the first TDI pin, and the fourth IO pin is connected with the first TDO pin;

the target bus signals comprise target TCK sub-signals, target TMS sub-signals and target TDI sub-signals, and the target TDI sub-signals carry the upgrade file;

the first programmable logic device sends the target bus signal to the first bus pin group through the first IO pin group, including:

and the target TCK sub-signal is sent to the first TCK pin through the first IO pin, the target TMS sub-signal is sent to the first TMS pin through the second IO pin, and the target TDI sub-signal is sent to the first TDI pin through the third IO pin.

8. The system of claim 7, further comprising at least one second programmable logic device; wherein each second programmable logic device comprises a second bus pin group, the second bus pin group comprising: the first TCK pin, the first TMS pin, the first TDI pin and the first TDO pin are connected in series;

the first IO pin is connected with a second TCK pin of each second programmable logic device, and the second IO pin is connected with a second TMS pin of each second programmable logic device;

and the first TDO pin is connected with a second TDI pin in a first-bit second programmable logic device; except the second programmable logic device positioned at the last bit, a second TDO pin in each second programmable logic device is connected with a second TDI pin in a second programmable logic device positioned at the next bit of the second programmable logic device; a second TDO pin in the second programmable logic device at the last bit is connected with the fourth IO pin;

the first programmable logic device is further configured to send the target TCK sub-signal to each second TCK pin through the first IO pin, send the target TMS sub-signal to each second TMS pin through the second IO pin, and send the target TDI sub-signal to the second TDI pin in the first second programmable logic device through the first TDO pin;

the second programmable logic device is used for sending the target TDI sub-signal to a second TDI pin of a second programmable logic device positioned at the next bit behind the second programmable logic device through a second TDO pin in the second programmable logic device; and determining whether the second programmable logic device is selected by the target TMS sub-signal according to the target TMS sub-signal, and if so, performing online upgrade according to the received target TCK sub-signal and the target TDI sub-signal.

9. The system of claim 8, further comprising a driver; the driver is connected with the first IO pin group and connected with a second bus pin group of at least one second programmable logic device;

the driver is used for redriving the target bus signal.

10. The system of claim 7, wherein the second IO pin set comprises a fifth IO pin, a sixth IO pin, a seventh IO pin, and an eighth IO pin; the serial port pin group comprises a CLK pin, a MISO pin, a MOSI pin and a CS pin; the fifth IO pin is connected with the CLK pin, the sixth IO pin is connected with the MISO pin, the seventh IO pin is connected with the MOSI pin, and the eighth IO pin is connected with the CS pin;

the CPU is specifically configured to write a target serial port signal sent by the CPU through the MOSI pin into the first programmable logic device according to a timing signal sent by the CPU through the CLK pin and a control signal sent by the CS pin.

11. The system of claim 6, further comprising a load base, the load base comprising a third bus pin group, the third bus pin group connected to the first bus pin group;

the loading seat is used for sending a loading bus signal carrying an upgrading file to the first bus pin group through the third bus pin group;

the first programmable logic device is also used for upgrading according to the loading bus signal.

12. A first programmable logic device is characterized by comprising a first IO pin group, a second IO pin group, a first bus pin group, a storage unit and a processing unit, wherein the first IO pin group is connected with the first bus pin group, and the second IO pin group is connected with a serial port pin group of a CPU;

the storage unit is used for storing a logic program;

the processing unit, when executing the program stored in the first storage unit, implementing the method steps of any of claims 1-5.

Background

In the related art, during the online upgrade process of a CPLD (Programmable Logic Device), a GPIO (General-purpose input/output) pin of a CPU needs to be occupied to simulate a JTAG (Joint Test Action Group) timing sequence, so as to send an upgrade file to the CPLD, thereby implementing the online upgrade of the CPLD.

However, the online upgrade mode will fixedly occupy 4 GPIO pins in the CPU, and the GPIO pins of the CPU are often function-multiplexed, so if the 4 GPIO pins are fixedly used for online upgrade, resources of the GPIO pins that can be used by other functions will be reduced, and normal implementation of other functions will be affected.

Disclosure of Invention

The embodiment of the invention aims to provide a method and a system for upgrading a programmable logic device on line so as to realize the on-line upgrading of the programmable logic device under the condition of not occupying GPIO (general purpose input/output) resources of a CPU (Central processing Unit).

The specific technical scheme is as follows:

in a first aspect of the embodiments of the present invention, an online upgrade method for a programmable logic device is provided, where the method is applied to a first programmable logic device, where the first programmable logic device includes a first IO pin group, a second IO pin group, and a first bus pin group, the first IO pin group is connected to the first bus pin group, and the second IO pin group is connected to a serial pin group of a CPU, and the method includes:

receiving a target serial port signal which is sent by the CPU through the serial port pin group and carries an upgrade file through the second IO pin group;

determining a target bus signal corresponding to the target serial port signal based on a mapping relation between a preset serial port signal and a bus signal, wherein the target bus signal carries the upgrade file;

and sending the target bus signal to the first bus pin group through the first IO pin group so as to write the upgrade file into the first programmable logic device through the target bus signal.

In a possible embodiment, the first IO pin group includes a first IO pin, a second IO pin, a third IO pin, and a fourth IO pin, and the first bus pin group includes a first TCK pin, a first TMS pin, a first TDI pin, and a first TDO pin; the first IO pin is connected with the TCK pin, the second IO pin is connected with the first TMS pin, the third IO pin is connected with the first TDI pin, and the fourth IO pin is connected with the first TDO pin;

the target bus signals comprise target TCK sub-signals, target TMS sub-signals and target TDI sub-signals, and the target TDI sub-signals carry the upgrade file;

the first IO pin group is configured to transmit the target bus signal to the first bus pin group, including:

and the target TCK sub-signal is sent to the first TCK pin through the first IO pin, the target TMS sub-signal is sent to the first TMS pin through the second IO pin, and the target TDI sub-signal is sent to the first TDI pin through the third IO pin.

In a possible embodiment, the first IO pin set is connected to a second bus pin set of at least one second programmable logic device, where the second bus pin set in each second programmable logic device includes: the first TCK pin, the first TMS pin, the first TDI pin and the first TDO pin are connected in series;

the first IO pin is connected with a second TCK pin of each second programmable logic device, and the second IO pin is connected with a second TMS pin of each second programmable logic device;

and the first TDO pin is connected with a second TDI pin in a first-bit second programmable logic device; except the second programmable logic device positioned at the last bit, a second TDO pin in each second programmable logic device is connected with a second TDI pin in a second programmable logic device positioned at the next bit of the second programmable logic device; a second TDO pin in the second programmable logic device at the last bit is connected with the fourth IO pin;

the method further comprises the following steps:

the target TCK sub-signal is sent to each second TCK pin through the first IO pin, the target TMS sub-signal is sent to each second TMS pin through the second IO pin, and the target TDI sub-signal is sent to a second TDI pin in a first programmable logic device through the first TDO pin;

each second programmable logic device is used for sending the target TDI sub-signal to a second TDI pin of a second programmable logic which is positioned at the next bit of the second programmable logic device through a second TDO pin in the second programmable logic device; and determining whether the second programmable logic device is selected by the target TMS sub-signal according to the target TMS sub-signal, and if so, performing online upgrade according to the received target TCK sub-signal and the target TDI sub-signal.

In a possible embodiment, a driver is disposed between the first programmable logic device and the second programmable logic device, and the driver is configured to redrive at least one of the target TCK sub-signal, the target TMS sub-signal and the target TDI sub-signal.

In a possible embodiment, the second IO pin group includes a fifth IO pin, a sixth IO pin, a seventh IO pin, and an eighth IO pin; the serial port pin group comprises a CLK pin, a MISO pin, a MOSI pin and a CS pin; the fifth IO pin is connected with the CLK pin, the sixth IO pin is connected with the MISO pin, the seventh IO pin is connected with the MOSI pin, and the eighth IO pin is connected with the CS pin;

the receiving, by the second IO pin group, the target serial port signal carrying the upgrade file sent by the CPU through the serial port pin group includes:

and writing a target serial port signal sent by the CPU through the MOSI pin into the first programmable logic device according to a timing signal sent by the CPU through the CLK pin and a control signal sent by the CS pin.

In a second aspect of the embodiments of the present invention, there is provided an online upgrade system for a programmable logic device, including: a CPU, a first programmable logic device;

the CPU comprises a serial port pin group, the first programmable logic device comprises a first IO pin group, a second IO pin group and a first bus pin group, the first IO pin group is connected with the first bus pin group, and the second IO pin group is connected with the serial port pin group;

the CPU is used for sending a target serial port signal carrying an upgrading file to the first programmable logic device through the serial port pin group;

the first programmable logic device is used for determining a target bus signal corresponding to the target serial port signal based on a mapping relation between a preset serial port signal and a bus signal, and the target bus signal carries the upgrade file; and sending the target bus signal to the first bus pin group through the first IO pin group so as to write the upgrade file into the first programmable logic device through the target bus signal.

In a possible embodiment, the first IO pin group includes a first IO pin, a second IO pin, a third IO pin, and a fourth IO pin, and the first bus pin group includes a first TCK pin, a first TMS pin, a first TDI pin, and a first TDO pin; the first IO pin is connected with the TCK pin, the second IO pin is connected with the first TMS pin, the third IO pin is connected with the first TDI pin, and the fourth IO pin is connected with the first TDO pin;

the target bus signals comprise target TCK sub-signals, target TMS sub-signals and target TDI sub-signals, and the target TDI sub-signals carry the upgrade file;

the first programmable logic device sends the target bus signal to the first bus pin group through the first IO pin group, including:

and the target TCK sub-signal is sent to the first TCK pin through the first IO pin, the target TMS sub-signal is sent to the first TMS pin through the second IO pin, and the target TDI sub-signal is sent to the first TDI pin through the third IO pin.

In one possible embodiment, the system further comprises at least one second programmable logic device; wherein each second programmable logic device comprises a second bus pin group, the second bus pin group comprising: the first TCK pin, the first TMS pin, the first TDI pin and the first TDO pin are connected in series;

the first IO pin is connected with a second TCK pin of each second programmable logic device, and the second IO pin is connected with a second TMS pin of each second programmable logic device;

and the first TDO pin is connected with a second TDI pin in a first-bit second programmable logic device; except the second programmable logic device positioned at the last bit, a second TDO pin in each second programmable logic device is connected with a second TDI pin in a second programmable logic device positioned at the next bit of the second programmable logic device; a second TDO pin in the second programmable logic device at the last bit is connected with the fourth IO pin;

the first programmable logic device is further configured to send the target TCK sub-signal to each second TCK pin through the first IO pin, send the target TMS sub-signal to each second TMS pin through the second IO pin, and send the target TDI sub-signal to the second TDI pin in the first second programmable logic device through the first TDO pin;

the second programmable logic device is used for sending the target TDI sub-signal to a second TDI pin of a second programmable logic device positioned at the next bit behind the second programmable logic device through a second TDO pin in the second programmable logic device; and determining whether the second programmable logic device is selected by the target TMS sub-signal according to the target TMS sub-signal, and if so, performing online upgrade according to the received target TCK sub-signal and the target TDI sub-signal.

In a possible embodiment, the system further comprises a driver; the driver is connected with the first IO pin group and connected with a second bus pin group of at least one second programmable logic device;

the driver is used for redriving the target bus signal.

In a possible embodiment, the second IO pin group includes a fifth IO pin, a sixth IO pin, a seventh IO pin, and an eighth IO pin; the serial port pin group comprises a CLK pin, a MISO pin, a MOSI pin and a CS pin; the fifth IO pin is connected with the CLK pin, the sixth IO pin is connected with the MISO pin, the seventh IO pin is connected with the MOSI pin, and the eighth IO pin is connected with the CS pin;

the CPU is specifically configured to write a target serial port signal sent by the CPU through the MOSI pin into the first programmable logic device according to a timing signal sent by the CPU through the CLK pin and a control signal sent by the CS pin.

In a possible embodiment, the system further comprises a load base, the load base comprising a third bus pin group, the third bus pin group being connected to the first bus pin group;

the loading seat is used for sending a loading bus signal carrying an upgrading file to the first bus pin group through the third bus pin group;

the first programmable logic device is also used for upgrading according to the loading bus signal.

In a third aspect of the embodiments of the present invention, a first programmable logic device is provided, where the first programmable logic device includes a first IO pin group, a second IO pin group, a first bus pin group, a storage unit, and a processing unit, the first IO pin group is connected to the first bus pin group, and the second IO pin group is connected to a serial pin group of a CPU;

the storage unit is used for storing a logic program;

the processing unit is configured to implement the method steps of any one of the first aspect described above when executing the program stored in the first storage unit.

The embodiment of the invention has the following beneficial effects:

according to the method and the system for the on-line upgrading of the programmable logic device, the CPU can be accessed into the first CPLD through the serial port pin group, so that a target serial port signal carrying an upgrading file is sent to the first CPLD, the first CPLD converts the target serial port signal into a target bus signal carrying the upgrading file based on the preset mapping relation between the serial port signal and the bus signal, and sends the target bus signal to the first bus pin group of the first CPLD through the second IO pin group, so that the first bus pin group can receive the target bus signal carrying the upgrading file, and the first CPLD can write the upgrading file into the first CPLD to realize the on-line upgrading. In the scheme, only the serial port pin group in the CPU is occupied, but the GPIO pin of the CPU is not occupied, and because IO pin resources in the CPLD are more abundant, even if the first IO pin group and the second IO pin group are fixedly occupied for online upgrading, the realization of other functions of the CPLD is not influenced (or the influence is less). Therefore, the CPLD can be upgraded on line under the condition of not occupying GPIO pin resources of the CPU, and the influence of the online upgrade on other functions is reduced.

Of course, not all of the advantages described above need to be achieved at the same time in the practice of any one product or method of the invention.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by referring to these drawings.

Fig. 1 is a schematic flowchart of an online upgrade method for a programmable logic device according to an embodiment of the present invention;

fig. 2 is a schematic circuit diagram of an online upgrade system for a programmable logic device according to an embodiment of the present invention;

FIG. 3 is another circuit diagram of an online upgrade system for a programmable logic device according to an embodiment of the present invention;

FIG. 4a is a schematic circuit diagram of an online upgrade system for a programmable logic device according to an embodiment of the present invention;

FIG. 4b is a schematic circuit diagram of an online upgrade system for a programmable logic device according to an embodiment of the present invention;

FIG. 5 is a schematic circuit diagram of an online upgrade system for a programmable logic device according to an embodiment of the present invention;

FIG. 6 is a schematic circuit diagram of an online upgrade system for a programmable logic device according to an embodiment of the present invention;

FIG. 7 is a schematic circuit diagram of an online upgrade system for a programmable logic device according to an embodiment of the present invention;

FIG. 8 is a schematic circuit diagram of an online upgrade system for a programmable logic device according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of a first programmable logic device according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived from the embodiments given herein by one of ordinary skill in the art, are within the scope of the invention.

Referring to fig. 1, fig. 1 is a schematic flow chart of an online upgrade method for a programmable logic device according to an embodiment of the present invention, where the online upgrade method for a programmable logic device is applied to a first CPLD, where the first CPLD includes a first IO pin group, a second IO pin group, and a first bus pin group, the first IO pin group is connected to the first bus pin group, and the second IO pin group is connected to a serial pin group of a CPU, and the online upgrade method for a programmable logic device may include:

and S101, receiving a target serial port signal which is sent by the CPU through the serial port pin group and carries an upgrade file through the second IO pin group.

S102, determining a target bus signal corresponding to the target serial port signal based on a preset mapping relation between the serial port signal and the bus signal, wherein the target bus signal carries an upgrade file.

S103, sending the target bus signal to the first bus pin group through the first IO pin group so as to write the upgrade file into the first programmable logic device through the target bus signal.

According to the embodiment, the CPU can be accessed into the first CPLD through the serial port pin group, so that a target serial port signal carrying an upgrade file is sent to the first CPLD, the first CPLD converts the target serial port signal into a target bus signal carrying the upgrade file based on the preset mapping relation between the serial port signal and the bus signal, and sends the target bus signal to the first bus pin group of the first CPLD through the second IO pin group, so that the first bus pin group can receive the target bus signal carrying the upgrade file, and the first CPLD can write the upgrade file into the first CPLD to realize online upgrade. In the scheme, only the serial port pin group in the CPU is occupied, but the GPIO pin of the CPU is not occupied, and because IO pin resources in the CPLD are more abundant, even if the first IO pin group and the second IO pin group are fixedly occupied for online upgrading, the realization of other functions of the CPLD is not influenced (or the influence is less). Therefore, the CPLD can be upgraded on line under the condition of not occupying GPIO pin resources of the CPU, and the influence of the online upgrade on other functions is reduced.

In S101, the Serial port pin group may be a pin group that has a capability of sending a Serial port signal and can be connected to the first IO pin group at will in the CPU, for example, an MDIO (Management Data Input/Output) pin group, an SPI (Serial Peripheral Interface) pin group, and the like.

In S102, it can be understood that the bus signal can be regarded as a combination of a high-level signal and a low-level signal with time sequence, so in one possible embodiment, the first CPLD may record the target serial port signal by using data in a specific form, such as characters, numerical values, and the like, and map the recorded data into a combination of the high-level signal and the low-level signal, so as to obtain the target bus signal corresponding to the target serial port signal. How the first CPLD records the target serial port signal and how to map the recorded value to the combination of the high level signal and the low level signal will be described in detail hereinafter, and therefore will not be described in detail herein.

In S103, the first bus pin group may be any pin group of the first CPLD that has the capability of writing the upgrade file into the first CPLD and can be butted with the second IO pin group, and the capability of writing the upgrade file into the first CPLD means that the first CPLD can write the upgrade file received by the pin group into the first CPLD. For example, the first bus pin group may be a JTAG pin group, and for convenience of description, the first bus pin group will be described as an example of the JTAG pin group, and the same principle can be obtained for the case where the first bus pin group is another pin group, and details are not repeated.

In order to more clearly describe the online upgrade method for the programmable logic device provided in the embodiment of the present invention, in the following, how the first CPLD maps the target serial port signal to the target bus signal is described in an example manner with reference to a specific embodiment, referring to fig. 2, where fig. 2 is a schematic structural diagram of the online upgrade system for CPLDs provided in the embodiment of the present invention, and the schematic structural diagram may include: a CPU210, a first CPLD 220.

The CPU210 includes a serial pin group 211. The CPU210 sends the target serial signal to the first CPLD through the serial pin group 211.

The first CPLD220 includes a first IO pin group 221, a second IO pin group 222, and a first bus pin group 223. The first IO pin group 221 includes a first IO pin, a second IO pin, a third IO pin, and a fourth IO pin, and the first IO pin group includes a first TCK (test clock input) pin, a first TMS (test mode select) pin, a first TDI (test data input) pin, and a first TDO (test data output) pin. The first IO pin is connected with the TCK pin, the second IO pin is connected with the first TMS pin, the third IO pin is connected with the first TDI pin, and the fourth IO pin is connected with the first TDO pin.

In this embodiment, the target bus signals may include a target TCK sub-signal, a target TMS sub-signal, and a target TDI sub-signal. The first CPLD sending the target bus signal to the first bus pin group through the first IO pin group may include:

and sending a target TCK sub-signal to the first TCK pin through the first IO pin group, sending a target TMS sub-signal to the first TMS pin through the second IO pin, and sending a target TDI sub-signal to the first TDI pin through the third IO pin.

The first CPLD can write a numerical value into a target bit in a register of the first CPLD according to the target serial port signal, determine a target TCK sub-signal according to the value of the target bit corresponding to the TCK sub-signal, determine a target TMS sub-signal according to the value of the target bit corresponding to the TMS sub-signal, and determine a target TDI sub-signal according to the value of the target bit corresponding to the TDI sub-signal.

The target bit may be a plurality of bits in a register, and the number of possible values of the target bit should be greater than the possible kinds of the target bus signals. Illustratively, since any one of the target TCK sub-signal, the target TMS sub-signal and the target TDI sub-signal is a high-level signal or a low-level signal, there are theoretically 2^3 ^ 8 possibilities for the target bus signal composed of the target TCK sub-signal, the target TMS sub-signal and the target TDI sub-signal, and therefore the possible values of the target bits should be at least 8. Assuming that the value of each target bit is 0 or 1, when the number of target bits is 1, the possible values of the target bits are 0 and 1, that is, the number of possible values of the target bits is 2, and when the number of target bits is 2, the possible values of the target bits are 00, 01, 10, and 11, that is, the number of possible values of the target bits is 4. It can be seen that in this embodiment, the number of target bits should be at least 3, and in some possible embodiments, the number of target bits may be only 3, and in other embodiments, the number of target bits may also be more than 3, for example, 5, 8, 11, 16, and the like, which is not limited in this embodiment. For convenience of description, only the case of 8 target bits is described below, and the same applies to the case of other numbers of target bits, which is not described again.

Each sub-signal may correspond to one or more target bits, each corresponding to at most one sub-signal, for example, in one possible embodiment, a total of 8 target bits, denoted as target bits 1-8, may be target bit 1 corresponding to the TCK sub-signal, target bit 2 corresponding to the TMS sub-signal, target bit 3 corresponding to the TDI sub-signal, target bits 4-8 corresponding to other signals or none, e.g., target bit 4 may correspond to the TDO sub-signal, and target bits 5-8 are reserved target bits not corresponding to any signal.

When the target TCK sub-signal is determined based on the value of the target bit corresponding to the TCK sub-signal, it may be determined that the target TCK sub-signal is a high level signal when the value of the target bit corresponding to the TCK sub-signal is 1, and the target TCK sub-signal is a low level signal when the value of the target bit corresponding to the TCK sub-signal is 0. Similarly, the target TMS sub-signal may be determined to be a high level signal when the value of the target bit corresponding to the TMS sub-signal is 1, and the target TMS sub-signal may be determined to be a low level signal when the value of the target bit corresponding to the TMS sub-signal is 0. Determining the target TDI sub-signal as a high-level signal when the value of the target bit corresponding to the TDI sub-signal is 1, and determining the target TDI sub-signal as a low-level signal when the value of the target bit corresponding to the TDI sub-signal is 0

In order to more clearly describe the online upgrade method of the programmable logic device provided in the embodiment of the present invention, how the first CPLD records the target serial port signal will be described below with reference to a specific embodiment, that is, how the CPU writes the target serial port signal into the first CPLD will be described. Referring to fig. 3, fig. 3 is a schematic structural diagram of another CPLD online upgrade system according to an embodiment of the present invention.

In this embodiment, the second IO pin group 222 includes a fifth IO pin, a sixth IO pin, a seventh IO pin, and an eighth IO pin. The serial port pin group includes a CLK (Clock) pin, a MISO (Master In Slave Out) pin, a MOSI (Master Out Slave In) pin, and a CS (Chip Select enable) pin. A fifth IO pin is connected with a CLK pin, a sixth IO pin is connected with a MISO pin, a seventh IO pin is connected with a MOSI pin, and an eighth IO pin is connected with a CS pin;

in this embodiment, the receiving, by the first CPLD220, the target serial port signal carrying the upgrade file, sent by the CPU through the serial port pin group 211 through the second IO pin group 222 may include: and writing a target serial port signal sent by the CPU through the MOSI pin into the first programmable logic device according to a timing signal sent by the CPU through the CLK pin and a control signal sent by the CS pin.

The target serial port signal sent by the CPU210 through the MOSI pin may be regarded as a code stream, and in a possible embodiment, the CPU210 may send a total of 32 bit code streams in 4 times through the MOSI pin each time the code stream is sent. And after the 32-bit code stream is sent, the CPU210 may set the signal of the CS pin as a high-level signal, and reset the signal of the CS pin as a low-level signal before the next code stream is sent.

Register address fields and value fields may be included in the codestream. The register address field is used to indicate a register address, and the value field is used to indicate a value to be written, where the value to be written is a value to be written into a register when the CPU210 executes a write operation. When the CPU210 performs a read operation, since there is no value to be written to the register, the value to be written represented by the value field may be an arbitrary value.

After receiving the code stream, the first CPLD220 may analyze the register address field and the value field therein, thereby obtaining the register address represented by the register address field and the value to be written represented by the value field, and writing the value to be written into the register with the address being the bit of the register address. Therefore, the CPU210 writes a value into the register of the first CPLD220, and the CPU210 can write the serial port signal carrying the upgrade file into the first CPLD220 by writing a value into the register. It is understood that, according to actual requirements, the CPU210 may write a target value in the target bit of the register, and may also write a corresponding value in the non-target bit of the register, which is not limited in this embodiment.

And, in a possible embodiment, the code stream may further include a command field, where the command field is used to indicate an operation that needs to be executed by the CPU210, and the first CPLD220 may determine the operation indicated by the command field by parsing the command field, write the value to be written into the register with the address of the bit of the register address if the command field indicates a write operation, read the value in the register with the address of the bit of the register address if the command indicates a read operation, and send the read value to the CPU210, so as to enable the CPU210 to read the value in the register.

For a clearer description of the code stream, the following description will exemplarily take the length of the code stream as 32 bits, and will respectively record the 32 bits in the code stream as bits 0-31, and in one possible embodiment, bits 0-7 are a value field, bits 8-23 are a register address field, and bits 24-31 are a command field.

The command field is 8 bits in length and may be represented as a 2-bit 16-ary number, which in one possible embodiment represents a read operation when the command field is 0x55 and a write operation when the command field is 0xaa, where 0x is the prefix of the 16-ary number, i.e., 0x55 represents 55 in hexadecimal and 01010101 as a binary number.

The register address field is 16 bits in length and can represent 2^16 ≈ 32000 address spaces. The length of the value field is 8 bits. For convenience of description, the code stream of 32 bits is represented by an 8-bit 16-ary code for illustrative purposes, and in one possible embodiment, when the CPU210 needs to read a value at a bit address of 0001 in the register, the code stream 0x550001 may be sent, where x represents an arbitrary value, and when the CPU210 needs to write 0x5a at a bit address of 0001 in the register, the code stream 0xaa00015a may be sent.

In addition, in a possible embodiment, the CPU may drive other CPLDs through the serial port pin group for online upgrade, for example, as shown in fig. 4a, fig. 4a is another circuit schematic diagram of the online upgrade system of the programmable logic device provided in the embodiment of the present invention, and the diagram includes a second CPLD230 in addition to the first CPLD 220.

Although fig. 4a only includes two second CPLDs 230, in other possible embodiments, only one second CPLD230 may be included, and 3 or more than 3 second CPLDs 230 may also be included, which is not limited in this embodiment. In addition, for the case of only including one second CPLD230, see fig. 4b, for the case of 3 or more than 3 second CPLDs 230, the connection relationship between the CPU210, the first CPLD220, and each second CPLD230 is the same as that shown in fig. 4a, and is not described herein again.

In this embodiment, each second CPLD includes a second bus pin group, which includes: the first TCK pin, the second TMS pin, the second TDI pin and the second TDO pin.

The first IO pin is connected with the second TCK pin of each second CPLD, and the second IO pin is connected with the second TMS pin of each second CPLD. The first TDO pin is connected with the second TDI pin of the second CPLD positioned at the head position, and except the second CPLD positioned at the tail position, the second TDO pin in each second CPLD is connected with the second TDI pin in the second CPLD positioned at the rear position of the second CPLD; and a second TDO pin in the second CPLD at the last bit is connected with a fourth IO pin.

In other possible embodiments, the second CPLD230 far from the first CPLD220 may also be the second CPLD230 at the head, and the second CPLD230 near the first CPLD220 is the second CPLD230 at the end, in these embodiments, the connection relationship between the first CPLD220 and each second CPLD230 will be changed accordingly.

In the embodiment shown in fig. 4a, the first CPLD220 may send the target TCK sub-signal to each second TCK pin through the first IO pin, send the target TMS sub-signal to each second TMS pin through the second IO pin, and send the target TDI sub-signal to the second TDI pin in the first second programmable logic device through the first TDO pin.

Each second CPLD230 may send a target TDI sub-signal to a second TDI pin of the second programmable logic 230 located at a bit behind the second programmable logic device 230 through the second TDO pin in the second CPLD, and determine whether the second CPLD230 is selected by the target TMS sub-signal according to the target TMS sub-signal, and if so, perform online upgrade according to the received target TCK sub-signal and the target TDI sub-signal.

It can be understood that, for each second CPLD230, the signals received through the second bus pin group are the same as the signals received through the first bus pin group of the first CPLD220, and are bus signals carrying an upgrade file, so that the second CPLD230 can perform online upgrade according to the signals received through the second bus pin group.

By selecting the embodiment, the CPU can drive the CPLDs to carry out online upgrade through one serial port pin group, and the first CPLD can drive the CPLDs to carry out online upgrade through one first IO pin group, so that the pin resources of the CPU and the first CPLD can be further saved.

It can be understood that the second CPLD230 located at the last bit does not have the second CPLD230 located at the next bit, and therefore the second CPLD230 located at the last bit may or may not send the target TDI sub-signal to the fourth IO pin of the first CPLD220 through the second TDO pin.

In a possible embodiment, in order to avoid the signal quality degradation caused by the simultaneous driving of multiple CPLDs by the first IO pin, and further cause the CPLD online upgrade to be abnormal, as shown in fig. 5, a driver 240 may be disposed between the first CPLD220 and the second CPLD230, and the driver 240 may be configured to redrive at least one sub-signal of the target TCK sub-signal, the target TMS sub-signal, and the target TDI sub-signal, so as to improve the sub-signal quality, and further avoid the CPLD online upgrade abnormality caused by the degradation of the factor signal quality.

Referring to fig. 6, fig. 6 is a schematic structural diagram of an online upgrade system for a programmable logic device according to an embodiment of the present invention, where the online upgrade system may include:

a CPU210, a first CPLD 220;

the CPU210 includes a serial port pin group 211, the first CPLD220 includes a first IO pin group 221, a second IO pin group 222, and a first bus pin group 223, the first IO pin group 221 is connected to the first bus pin group 223, and the second IO pin group 222 is connected to the serial port pin group 211;

the CPU210 is configured to send a target serial port signal carrying an upgrade file to the first CPLD220 through the serial port pin group 211;

the first CPLD220 is configured to determine a target bus signal corresponding to the target serial port signal based on a mapping relationship between a preset serial port signal and a bus signal, where the target bus signal carries the upgrade file; and sends the target bus signal to the first bus pin group 223 through the first IO pin group 221, so as to write the upgrade file into the first programmable logic device 220 through the target bus signal.

In a possible embodiment, the first IO pin group 221 includes a first IO pin, a second IO pin, a third IO pin, and a fourth IO pin, and the first bus pin group 223 includes a first TCK pin, a first TMS pin, a first TDI pin, and a first TDO pin; the first IO pin is connected with the TCK pin, the second IO pin is connected with the first TMS pin, the third IO pin is connected with the first TDI pin, and the fourth IO pin is connected with the first TDO pin;

the target bus signals comprise target TCK sub-signals, target TMS sub-signals and target TDI sub-signals, and the target TDI sub-signals carry the upgrade file;

the first CPLD sends the target bus signal to the first bus pin group 223 through the first IO pin group 221, including:

and the target TCK sub-signal is sent to the first TCK pin through the first IO pin, the target TMS sub-signal is sent to the first TMS pin through the second IO pin, and the target TDI sub-signal is sent to the first TDI pin through the third IO pin.

In a possible embodiment, the system further comprises at least one second CPLD 230; wherein each second CPLD230 includes a second bus pin group 231, and the second bus pin group 231 includes: the first TCK pin, the first TMS pin, the first TDI pin and the first TDO pin are connected in series;

the first IO pin is connected with the second TCK pin of each second CPLD230, and the second IO pin is connected with the second TMS pin of each second CPLD 230;

and the first TDO pin is connected with a second TDI pin in a first second CPLD; except for the second programmable logic device positioned at the last position, a second TDO pin in each second CPLD is connected with a second TDI pin in the second CPLD positioned at the position behind the second CPLD; a second TDO pin in the second CPLD at the last position is connected with the fourth IO pin;

the first CPLD220 is further configured to send the target TCK sub-signal to each second TCK pin through the first IO pin, send the target TMS sub-signal to each second TMS pin through the second IO pin, and send the target TDI sub-signal to the second TDI pin in the first second CPLD through the first TDO pin;

the second CPLD230 is configured to send the target TDI sub-signal to a second TDI pin of the second CPLD230 located one bit behind the second CPLD230 through a second TDO pin in the second CPLD 230; and determining whether the second CPLD230 is selected by the target TMS sub-signal according to the target TMS sub-signal, and if so, performing online upgrade according to the received target TCK sub-signal and the target TDI sub-signal.

In one possible embodiment, the system further comprises a driver 240; the driver 240 is connected to the first IO pin set 221 and to the second bus pin set 231 of the at least one second CPLD 230;

the driver 240 is configured to redrive the target bus signal.

In a possible embodiment, the second IO pin group includes a fifth IO pin, a sixth IO pin, a seventh IO pin, and an eighth IO pin; the serial port pin group 211 comprises a CLK pin, a MISO pin, a MOSI pin and a CS pin; the fifth IO pin is connected with the CLK pin, the sixth IO pin is connected with the MISO pin, the seventh IO pin is connected with the MOSI pin, and the eighth IO pin is connected with the CS pin;

the CPU210 is specifically configured to write a target serial port signal sent by the CPU210 through the MOSI pin into the first CPLD220 according to a timing signal sent by the CPU through the CLK pin and a control signal sent by the CS pin.

In a possible embodiment, the system may further include a load base 250, the load base 250 includes a third bus pin group 251, and the third bus pin group 251 is connected to the first bus pin group 223;

the loading base 250 is configured to send a loading bus signal carrying an upgrade file to the first bus pin group 223 through the third bus pin group 251;

the first CPLD220 is further configured to upgrade according to the loading bus signal.

For example, as shown in fig. 7, the third bus pin group 251 in the loading dock 250 may include a third TDI pin, a third TDO pin, a third TMS pin, and a third TCK pin, where the third TDI pin is connected to the first TDO pin, the third TDO pin is connected to the first TDI pin, the third TMS pin is connected to the first TMS pin, and the third TCK pin is connected to the first TCK pin.

The loading bus signals may include a loading TMS sub-signal, a loading TCK sub-signal, and a loading TDI sub-signal, where the loading TDI sub-signal carries an upgrade file. The loading base 250 may write the upgrade file carried by the load TDI signal sent through the third TDI pin into the first CPLD220 according to the load CLK sub-signal sent through the third CLK pin and the load TMS sub-signal sent through the third TMS pin, so as to control the upgrade of the first CPLD 220.

By adopting the embodiment, the CPLD can be upgraded on line under the drive of the CPU and can also be upgraded under the drive of the loader, so that the applicability is improved.

In addition, in a scenario where a plurality of CPLDs and drivers exist, the CPLD online upgrade system may also include a loader, for example, see fig. 8, and for the CPU210, the first CPLD220, the second CPLD230, the driver 240, and the loader 250 in fig. 8, reference may be made to the foregoing related description, which is not described herein again.

The embodiment of the present invention further provides a first CPLD, which may include, as shown in fig. 9, a first IO pin group, a second IO pin group, a first bus pin group, a storage unit, and a processing unit, where the first IO pin group is connected to the first bus pin group, and the second IO pin group is connected to a serial pin group of a CPU;

the storage unit 901 is used for storing logic programs;

the processing unit 902 is configured to, when executing the program stored in the first storage unit, execute the following steps:

receiving a target serial port signal which is sent by the CPU through the serial port pin group and carries an upgrade file through the second IO pin group;

determining a target bus signal corresponding to the target serial port signal based on a mapping relation between a preset serial port signal and a bus signal, wherein the target bus signal carries the upgrade file;

and sending the target bus signal to the first bus pin group through the first IO pin group so as to write the upgrade file into the first programmable logic device through the target bus signal.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the invention to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the system, the first CPLD embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for the relevant points, refer to the partial description of the method embodiment.

The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.