1. A method for generating multiple signals of ultra wide band time-varying motion multiple systems is characterized in that: the multichannel parallel processing architecture technology is used for editing and rapidly processing multiple signals of ultra-wideband time-varying motion in real time, when a user needs to generate a dynamic signal, a signal library developed by the user is selected, an API (application program interface) of a system is called, all signal information is configured through algorithm logic, and parameters such as a sampling rate matching, a frequency shift, a phase, an amplitude and a time delay are changed, so that parameters such as a time domain, an energy domain, a frequency domain, a modulation mode and a space domain of a test system signal are changed, and then the parameters are read circularly to generate an infinite-time scene signal; the method comprises the following steps:

a single signal independent configuration method comprises the following steps:

the method comprises the following steps of adopting single-signal independent configuration to support each signal to carry out independent parameter configuration, namely independently generating independent signals with different data lengths and even different sampling rates, and then respectively downloading the signals;

during playing, the bottom layer logic controls single signal output and synthesizes and outputs all signals, and the adjustment of single signal parameters is adjusted before all signals are synthesized, so that the single signal can be independently adjusted and can be adjusted in real time on line; the single-signal independent configuration parameters comprise configurations of signal systems, central frequency, reference power, attenuation, time delay, phase offset and frequency shift, and are packaged in an API function calling mode when the system is actually designed;

the parameters of each signal can be independently controlled on line and can be independently set when static target simulation is carried out; under the dynamic target antenna scanning, the method is directly realized by configuring antenna scanning parameters of reference power;

second, a method for generating multi-channel signals of FPGA,

in the process of processing the multi-channel real-time signals, the signal parameters of each channel are controlled on line through an API (application program interface) interface, so that the capabilities of on-line switching, editing and switching are obtained;

the hardware system comprises: the PC software drives the system interface, control each digital module; each digital module comprises independent FPGA and DAC circuits from CH1 of channel 1 to CHn of channel n; meanwhile, the PC software drives a system interface to control the synchronization module; the synchronization module comprises a local oscillator and a synchronization circuit; the synchronous module sends a synchronous signal to each digital module, and real-time modulation is carried out according to the amplitude and the phase of the feedback signal of each digital module, so that each digital module with good amplitude-phase consistency is obtained;

a plurality of channel signal generating structures are designed in the FPGA, each channel can independently configure signals and corresponding parameters, and the signals do not influence each other;

in the process of processing the multi-channel real-time signals, the signal parameters of each channel are controlled on line through an API (application program interface) interface, so that the capabilities of on-line switching, editing and switching are obtained; the multi-signal channel acquires parameters such as the number and the system of each baseband signal from a DDR memory, baseband oversampling is carried out after baseband buffering, signal resolution is improved, noise is reduced, time delay parameters of the signals are changed in real time according to requirements of users, 8-time interpolation is carried out on the signals, the sampling rate of each path of signals reaches 2.5Gsps to meet the requirement of broadband signal generation, then fundamental wave signals are modulated to corresponding carrier frequencies through orthogonal modulation, finally, generation of the signals is completed through multi-path synthesis and gain control, and the signals are output through DA;

(1) the baseband BUFF can improve the driving capability and isolate the front stage and the rear stage, and the buffer mostly has a tri-state output function; the baseband buffer area is used for buffering baseband signals to be sent and is realized by using an internal memory in the FPGA; the baseband BUFF circuit and the RAM IP core circuit work;

when the load does not have the non-gating output and has high resistance, the isolation effect can be achieved;

when the driving capacity of the bus is not enough to drive the load, the driving function can be achieved; the CPU working at high speed and the peripheral working at low speed play a role in coordination and buffering, and the synchronization of data transmission is realized;

the simulation of the initial speed output signal ensures that the data transmission image is smooth so as to realize the smooth data transmission;

(2) the oversampling design is adopted, the oversampling rate is the sampling frequency which is 2 times higher than the highest frequency of the signal, and the original signal can be recovered from the sampling signal by oversampling the baseband signal;

when a very high sampling frequency is used, the energy of noise is dispersed to a wider frequency range during quantization, and if a digital filter is used for filtering, most of the noise is filtered while a useful signal is kept, so that the signal-to-noise ratio (SNR) is improved;

from the formula SNR 6.02N +1.76+10 log (fs/2B): when the sampling rate fs is larger, the SNR is also larger, and B in the formula is the bandwidth; the Nyquist sampling frequency is 2 times of the highest frequency of the signal, the undersampling frequency is lower than 2 times of the highest frequency of the signal, and the oversampling frequency is higher than 2 times of the highest frequency of the signal;

(3) variable time delay, which is needed to ensure synchronization when performing synchronization between FPGA boards or performing signal output externally, so that information can be correctly received; the delay amount is automatically changed at any time according to actual requirements;

in a digital circuit, signal delay is realized by using a register and a trigger, when different ABCD binary numbers are input, different numbers of unit clock delay are realized, Din is an input signal, and Dout is a signal output after delay;

a digital circuit is built by using a D trigger, a counter and a logic gate, is programmed by using hardware description languages VHDL and Verilog, and is downloaded into an FPGA chip, so that the variable delay function is completed, the synchronism of signal output is ensured, and information can be correctly received;

(4) data interpolation means that sampling is carried out in a mode of 8 times of the original sampling rate, and the new sampling rate reaches 2.5 GHz; this requires that 7 interpolated values, where the interpolated value is 0, are inserted between every two points of the original sample sequence, and then a filter is connected to perform smoothing filtering;

(5) quadrature modulation, which means that a carrier with a higher frequency is used to carry a baseband signal to be transmitted, so that the baseband signal is suitable for transmission in a channel, and the baseband signal has a lower frequency, is easily interfered and is not suitable for long-distance transmission; the quadrature modulation is to use two quadrature signals with phase difference pi/2, multiply the signals of sin and cos by the signals of I path and Q path respectively, then add and synthesize a path of signal and transmit; the I path signal is also called as an in-phase signal, and the Q path signal is also called as an orthogonal signal; is expressed by the formula

s(t)＝I(t)cos2πf₀t-Q(t)sin2πf₀t

Two quadrature signals are used that differ in phase by pi/2: multiplying the sin signal and the cos signal by the I path signal and the Q path signal respectively, and then adding the signals to synthesize a path of signal; the I path signal is also called as an in-phase signal, and the Q path signal is also called as an orthogonal signal; finally, programming program codes of the multiplier and the adder by using hardware description languages VHDL and Verilog languages, and downloading the program codes into the FPGA after debugging is passed; the baseband signals are transferred at higher frequency, the method is suitable for long-distance transmission and is not easy to be interfered;

(6) the design of multipath synthesis, also called time division multiplexing, for improving the utilization rate of channels and frequency spectrums, a plurality of single-path signals are concentrated into one channel for transmission, and the power of the signals is amplified; the energy-power of the transmitted signal is increased through gain control;

the multi-channel synthesis time slot distribution and gain control circuit concentrates a plurality of single-channel signals to a channel, and then the power of each channel of signals is basically the same through the gain control circuit; the final signal gain output is obtained through simulation, the overall power output power of the signal is relatively flat, no time slot is idle, and the processor resources are utilized with the maximum efficiency;

establishing a corresponding scene in FPGA design, selecting a plurality of target signals which can exist, and generating corresponding signals through a signal library; then downloading the data to a DDR memory array through a PCIe bus so as to complete the downloading of the data; for a plurality of signals, each signal has a separate storage space; when the signal downloading is finished, the scene parameters need to be configured, and the information of amplitude, frequency, phase and the like of each signal needs to be configured; after data downloading and parameter configuration are completed, waiting for triggering, after triggering, acquiring data of each signal by controlling DDR through the multi-channel signal generation structure, completing single signal processing through a corresponding algorithm channel, and finally synthesizing all signals together through orthogonal modulation in a frequency division multiplexing mode to output; the multi-system multi-signal synthesis flow comprises the following steps:

firstly, all original target signals are generated and downloaded by software, the total data volume is limited by a memory, but the sampling rate is set to be lower because the signals are generated according to a single signal format, and the limitation of the memory is small and almost ignored under the comprehensive consideration; each target signal occupies an independent area in the memory; when playing, all target signals are read circularly at the same time, and signals of infinite time are generated; and finally, synthesizing all target signals, adjusting gain and outputting the target signals.

Background

In the field of electronic equipment measurement, in order to be close to a real electromagnetic environment and simulate the state of a real scene as much as possible, the dynamic property of a scene simulation signal needs to be ensured. The scene simulation signal dynamics mainly comprise the characteristics of time-varying property, multi-signal system, motility and the like.

(1) Time-variant refers to the temporal variation of a signal.

When the electromagnetic environment is constructed, the target positioning and track management and the signal playback are carried out, the application degree of the electronic system in each use stage is changed, so that the state of the electromagnetic environment is changed continuously. With time, the environment state of the tested device is changed continuously. Such as changes in season, weather, ionosphere, dielectrics, etc., the electromagnetic environment may also change. Only by continuously setting a time-varying scene, the electromagnetic environment situation changing along with the time can be completely expressed.

(2) The multi-signal system refers to the change of energy domain (amplitude), frequency domain and modulation mode of signals.

When an electromagnetic scene is constructed, electronic equipment systems with different quantities are in a working state, an energy domain (amplitude), a frequency domain and a modulation mode are continuously changed, and quantitative description and visual expression are required to be carried out on the aspects.

(3) Motion, refers to spatial variation of the signal.

When the electromagnetic environment, the target positioning and the track management are constructed, because the position of the electronic system is constantly changed in a real scene, corresponding electromagnetic environments are different in different positions, and signals generated by the corresponding electromagnetic environments are different. It is necessary to define different signal states at different orientations.

In summary, when a real electromagnetic scene is constructed, the simulated scene signals of different systems are different at different times and different directions, so that a large amount of simulated data is required to ensure the authenticity of the signals. And as the bandwidth of the simulation scene signal is wider and is limited by the real-time bandwidth of a signal source, the simulation system has the capacity of synthesizing and distributing multi-channel signals so as to realize the generation of the large-data-volume scene simulation signal in the ultra-wide frequency range.

In the current general scene signal generation method, a data interface is reserved for a user, the user customizes waveforms and edits the waveforms into data types and formats which can be identified by arbitrary waveform generator software, then the data types and formats are guided into a DDR memory of a digital module through the arbitrary waveform generator software, and then the data types and formats are triggered and output after appropriate parameters are configured, so that signals which are expected by the user are obtained. When the signal systems, time and positions need to be processed, the generation of the general scene signal can encounter the following problems:

1. the signal generation operation quantity is large, so that the scene signal time is short and the number of azimuth points is small.

Taking as an example a chirp radar signal and a continuous wave modulated communication signal of a scene signal, as shown in fig. 1. The scene signal can be described as:

s_cw(t)＝A(t)cos(ω_ct+θ(t))

the signal energy domain (amplitude) a, the frequency domain f and the modulation mode are continuously adjusted, and the number of corresponding signals s is continuously increased.

The longer the test system running time, the greater the number of time domains t.

The more the test system sets the azimuth, the more the number of airspaces p.

The total number of permutation and combination of the signal s, the time domain t and the space domain p is close to k (the total number of the signal s) x n (the total number of the time t) x m (the total number of the position p).

When the bandwidth of each signal is wide, the total data amount generated by the permutation combination of the total number of the signals s, the total number of the time t and the total number of the positions p is huge. The system is tested by using a general arbitrary waveform generator M8190A, the storage depth is 2GS, the 16-bit vertical resolution is realized, and the following limitations are caused.

(1) Short system test time

Let 10 signals with 10MHz bandwidth be generated, and there are 5 square points (trace points). The total bandwidth of 10 signals is 10 × 10 ═ 100MHz ═ 0.1 GHz. The 5 square points (trace points) produce a signal bandwidth of 0.1 × 5 — 0.5 GHz. Based on the Nyquist sampling theorem, with a 16-bit vertical resolution at 2.5 times the sampling rate, the amount of data per second is 0.5 × 2.5 × (16/8) ═ 2.5 GB.

The total playing time of any wave generator is 2 × 16/8/2.5 — 1.6 seconds.

When an arbitrary waveform generator is used to generate 10 signals with 10MHz bandwidth, and simulation is performed on a track consisting of only 5 azimuth points, the system can only support 1.6 seconds of scene signal generation. Such a short simulation time does not satisfy most of the task requirements.

(2) The number of the azimuth points of the system is small

Assuming that 10 signals with 10MHz bandwidth are generated, the total bandwidth of the 10 signals is 10 × 10 — 100MHz — 0.1 GHz. Based on the Nyquist sampling theorem, with a 16-bit vertical resolution at 2.5 times the sampling rate, the amount of data per second is 0.1 × 2.5 × (16/8) ═ 0.5 GB.

Assuming that only 10 seconds of simulation are performed (of course 10 seconds is not sufficient for many scene simulations), the total number of square points supported by M8190A: 2 to 0.8 in each of 16/8 and 0.5 to 10.

When an arbitrary waveform generator M8190A is used to generate 10 signals with 10MHz bandwidth, only 10 seconds of test is performed, the number of square points (track points) supported by the system is less than 1, a complete motion track is difficult to form, and most scene simulation requirements cannot be met.

2. When the number of the analog scene signals is large, the periodic difference is very large due to uncertainties such as the type, the bandwidth and the length of each signal, so that the memory is limited, the signals are complicated to edit and merge, and the playing time is short. Taking radar pulse signals as an example, the basic principle of multi-target signal synthesis is to combine a plurality of pulse signals in the time domain according to information such as Delay, pulse width τ, pulse repetition interval PRI, amplitude and the like of each pulse signal input by the system, as shown in fig. 2. The original signal envelope (e.g. signal s corresponding to signal segment 2 of the following diagram) is preserved during the time period in which the single signal is present₁Pulse 2) of (t), performing signal envelope superposition in a time period in which a plurality of signals simultaneously appear (such as signal segment 1 and signal segment 3 shown in the following figure), then counting the number of segments of the combined signals, the number of segment samples and pulse timing information in the segments, and finally processing intra-pulse modulation information in the combined signal segments to form a signal waveform file and generate signals through a signal generating device.

τ_points＝round((τ*f_s)/N_gran)*N_gran

PRI_points＝round((PRI*f_s)/N_gran)*N_gran

Delay_points＝round((Delay*f_s)/N_gran)*N_gran

Where τ is the signal pulse width, PRI is the signal pulse repetition interval, Delay is the signal initial Delay, f_sIs the system sampling rate, N_granIs the granularity of the signal that the system can process, tau_pointsAnd PRI_pointsIs the pulse width and pulse repetition interval, Delay, of the signal after digitization and adjustment of the granularity relationship_pointsIs the discrete number of points of the delay.

And generating a data configuration file according to the initial position of the synthesized signal, the number of the waveform files, the merging mode and other data, and playing the data configuration file in sequence according to the information in the data configuration file during playing.

In order to ensure the integrity of the scene signal simulation, the periodicity of the scene signal needs to be ensured, that is, the period of the scene signal is the least common multiple of the periods of different signals. When the number of signals of the test system is large, the periodic difference may be very large because the type, bandwidth, length, etc. of each signal are uncertain, so that the limited memory data length is used up, and a proper length cannot be found to meet the requirement that all signals are periodic. Even in some cases, a data file satisfying all signal periods is generated, and in this process, the dynamic sequence design is very complicated, and the signal is processed every frame. Often it takes several hours to edit the signal file, and finally only a few seconds of short playing time, which greatly consumes manpower and material resources.

3. When the data volume of the downloaded signal is large, the phenomenon that the abnormal point of the signal is ignored exists.

Since the signal data is downloaded to the DDR memory all at once, the length of the data is limited by the DDR memory. When the download data volume is large, the file can only be divided into several segments to be downloaded in sequence. And because the playing and downloading are separated, the playing must be carried out after the signals are completely downloaded, and the downloading speed in the period is influenced by the PCIE bus transmission and the PC end operation speed. In addition, since the signal is synthesized before being downloaded, it cannot be adjusted in real time during the playing process. And as long as the adjustment requirement exists, the signal combination is required to be carried out again, and then the signal combination is downloaded and played. Due to the fact that signal segmentation playing is not consistent, abnormal points can be ignored, and the scene simulation effect is affected.

Disclosure of Invention

In order to overcome the defects of the prior art, the invention provides a method for generating multiple signals of ultra wide band time-varying motion multiple systems.

In order to achieve the purpose, the invention adopts the following technical scheme:

1. a method for generating multiple signals of ultra wide band time-varying motion multiple systems is characterized in that: the multichannel parallel processing architecture technology is used for editing and rapidly processing multiple signals of ultra-wideband time-varying motion in real time, when a user needs to generate a dynamic signal, a signal library developed by the user is selected, an API (application program interface) of a system is called, all signal information is configured through algorithm logic, and parameters such as a sampling rate matching, a frequency shift, a phase, an amplitude and a time delay are changed, so that parameters such as a time domain, an energy domain, a frequency domain, a modulation mode and a space domain of a test system signal are changed, and then the parameters are read circularly to generate an infinite-time scene signal; the method comprises the following steps:

a single signal independent configuration method comprises the following steps:

the method comprises the following steps of adopting single-signal independent configuration to support each signal to carry out independent parameter configuration, namely independently generating independent signals with different data lengths and even different sampling rates, and then respectively downloading the signals;

during playing, the bottom layer logic controls single signal output and synthesizes and outputs all signals, and the adjustment of single signal parameters is adjusted before all signals are synthesized, so that the single signal can be independently adjusted and can be adjusted in real time on line; the single-signal independent configuration parameters comprise configurations of signal systems, central frequency, reference power, attenuation, time delay, phase offset and frequency shift, and are packaged in an API function calling mode when the system is actually designed;

the parameters of each signal can be independently controlled on line and can be independently set when static target simulation is carried out; under the dynamic target antenna scanning, the method is directly realized by configuring antenna scanning parameters of reference power;

second, a method for generating multi-channel signals of FPGA,

in the process of processing the multi-channel real-time signals, the signal parameters of each channel are controlled on line through an API (application program interface) interface, so that the capabilities of on-line switching, editing and switching are obtained;

the hardware system comprises: the PC software drives the system interface, control each digital module; each digital module comprises independent FPGA and DAC circuits from CH1 of channel 1 to CHn of channel n; meanwhile, the PC software drives the system interface to control the synchronous module. The synchronization module includes a local oscillator and a synchronization circuit. The synchronous module sends a synchronous signal to each digital module, and real-time modulation is carried out according to the amplitude and the phase of the feedback signal of each digital module, so that each digital module with good amplitude-phase consistency is obtained;

a plurality of channel signal generating structures are designed in the FPGA, each channel can independently configure signals and corresponding parameters, and the signals do not influence each other;

in the process of processing the multi-channel real-time signals, the signal parameters of each channel are controlled on line through an API (application program interface) interface, so that the capabilities of on-line switching, editing and switching are obtained; the multi-signal channel acquires parameters such as the number and the system of each baseband signal from a DDR memory, baseband oversampling is carried out after baseband buffering, signal resolution is improved, noise is reduced, time delay parameters of the signals are changed in real time according to requirements of users, 8-time interpolation is carried out on the signals, the sampling rate of each path of signals reaches 2.5Gsps to meet the requirement of broadband signal generation, then fundamental wave signals are modulated to corresponding carrier frequencies through orthogonal modulation, finally, generation of the signals is completed through multi-path synthesis and gain control, and the signals are output through DA;

(1) the baseband BUFF can improve the driving capability and isolate the front stage and the rear stage, and the buffer mostly has a tri-state output function; the baseband buffer area is used for buffering baseband signals to be sent and is realized by using an internal memory in the FPGA; the baseband BUFF circuit and the RAM IP core circuit work;

when the load does not have the non-gating output and has high resistance, the isolation effect can be achieved;

when the driving capacity of the bus is not enough to drive the load, the driving function can be achieved; the CPU working at high speed and the peripheral working at low speed play a role in coordination and buffering, and the synchronization of data transmission is realized;

the simulation of the initial speed output signal ensures that the data transmission image is smooth so as to realize the smooth data transmission;

(2) the oversampling design is adopted, the oversampling rate is the sampling frequency which is 2 times higher than the highest frequency of the signal, and the original signal can be recovered from the sampling signal by oversampling the baseband signal;

when a very high sampling frequency is used, the energy of noise is dispersed to a wider frequency range during quantization, and if a digital filter is used for filtering, most of the noise is filtered while a useful signal is kept, so that the signal-to-noise ratio (SNR) is improved;

from the formula SNR 6.02N +1.76+10 log (fs/2B): when the sampling rate fs is larger, the SNR is also larger, and B in the formula is the bandwidth; the Nyquist sampling frequency is 2 times of the highest frequency of the signal, the undersampling frequency is lower than 2 times of the highest frequency of the signal, and the oversampling frequency is higher than 2 times of the highest frequency of the signal;

(3) variable time delay, which is needed to ensure synchronization when performing synchronization between FPGA boards or performing signal output externally, so that information can be correctly received; the delay amount is automatically changed at any time according to actual requirements;

in a digital circuit, signal delay is realized by using a register and a trigger, when different ABCD binary numbers are input, different numbers of unit clock delay are realized, Din is an input signal, and Dout is a signal output after delay;

a digital circuit is built by using a D trigger, a counter and a logic gate, is programmed by using hardware description languages VHDL and Verilog, and is downloaded into an FPGA chip, so that the variable delay function is completed, the synchronism of signal output is ensured, and information can be correctly received;

(4) data interpolation means that sampling is carried out in a mode of 8 times of the original sampling rate, and the new sampling rate reaches 2.5 GHz; this requires that 7 interpolated values, where the interpolated value is 0, are inserted between every two points of the original sample sequence, and then a filter is connected to perform smoothing filtering;

(5) quadrature modulation, which means that a carrier with a higher frequency is used to carry a baseband signal to be transmitted, so that the baseband signal is suitable for transmission in a channel, and the baseband signal has a lower frequency, is easily interfered and is not suitable for long-distance transmission; the quadrature modulation is to use two quadrature signals with phase difference pi/2, multiply the signals of sin and cos by the signals of I path and Q path respectively, then add and synthesize a path of signal and transmit; the I path signal is also called as an in-phase signal, and the Q path signal is also called as an orthogonal signal; is expressed by the formula

s(t)＝I(t)cos2πf₀t-Q(t)sin2πf₀t

Two quadrature signals are used that differ in phase by pi/2: multiplying the sin signal and the cos signal by the I path signal and the Q path signal respectively, and then adding the signals to synthesize a path of signal; the I path signal is also called as an in-phase signal, and the Q path signal is also called as an orthogonal signal; finally, programming program codes of the multiplier and the adder by using hardware description languages VHDL and Verilog languages, and downloading the program codes into the FPGA after debugging is passed; the baseband signals are transferred at higher frequency, the method is suitable for long-distance transmission and is not easy to be interfered;

(6) the design of multipath synthesis, also called time division multiplexing, for improving the utilization rate of channels and frequency spectrums, a plurality of single-path signals are concentrated into one channel for transmission, and the power of the signals is amplified; the energy-power of the transmitted signal is increased through gain control;

the multi-channel synthesis time slot distribution and gain control circuit concentrates a plurality of single-channel signals to a channel, and then the power of each channel of signals is basically the same through the gain control circuit; the final signal gain output is obtained through simulation, the overall power output power of the signal is relatively flat, no time slot is idle, and the processor resources are utilized with the maximum efficiency;

establishing a corresponding scene in FPGA design, selecting a plurality of target signals which can exist, and generating corresponding signals through a signal library; and then downloading the data to the DDR memory array through the PCIe bus, thereby completing the downloading of the data. For a plurality of signals, each signal has a separate storage space; when the signal downloading is finished, the scene parameters need to be configured, and the information of amplitude, frequency, phase and the like of each signal needs to be configured; after data downloading and parameter configuration are completed, waiting for triggering, after triggering, acquiring data of each signal by controlling DDR through the multi-channel signal generation structure, completing single signal processing through a corresponding algorithm channel, and finally synthesizing all signals together through orthogonal modulation in a frequency division multiplexing mode to output; the multi-system multi-signal synthesis flow comprises the following steps:

firstly, all original target signals are generated and downloaded by software, the total data size is limited by a memory, but the sampling rate setting is low because the signals are generated according to a single signal format, and the limitation of the memory is small and almost ignored under the comprehensive consideration. Each target signal occupies an independent area in the memory; when playing, all target signals are read circularly at the same time, and signals of infinite time are generated; and finally, synthesizing all target signals, adjusting gain and outputting the target signals.

Due to the adoption of the technical scheme, the invention has the following advantages:

a method for generating multiple signals of ultra-wideband time-varying motion in multiple systems is based on the construction of an electromagnetic environment test system, a target positioning and track test system and a signal playback system and has the dynamic characteristics of time variation, multiple signal systems, motion and the like. When a system is tested, parameters such as a time domain, an energy domain, a frequency domain, a modulation mode, a space domain and the like need to be adjusted continuously. The ultra-wideband time-varying motion multi-system multi-signal synthesis has three difficulties of large signal generation and operation quantity, complex editing and merging, discontinuous downloading and playing, incapability of real-time adjustment and the like. The ultra-wideband time-varying motion multi-system multi-signal synthesis method based on single-signal independent configuration, an FPGA multi-channel signal generation structure and a multi-system multi-signal generation process can greatly reduce the dependence of a test system on an equipment memory and reduce the waveform operation time. Under the condition that the current memory cannot be infinitely increased, three difficulties of ultra-wideband time-varying motion multi-system signal generation are fundamentally solved.

Drawings

FIG. 1 is a prior art scene signal description diagram;

FIG. 2 is a prior art multiple radar pulse signal synthesis diagram;

FIG. 3 single signal independent configuration parameter diagram

FIG. 4 illustration of center frequency independent configuration

FIG. 5 reference power independent configuration diagram

FIG. 6 multi-channel real-time signal processing circuit

FIG. 7 FPGA multichannel signal generation architecture

FIG. 8 baseband BUFF circuit diagram

FIG. 9 RAM IP core block diagram

FIG. 10 oversampling schematic

FIG. 11 variable delay circuit

FIG. 12 interpolation scheme

FIG. 13 Quadrature modulation circuit diagram

FIG. 14 initial signal gain output plot

FIG. 15 is a schematic diagram of a circuit design for multiplexing timeslot assignment and gain control

FIG. 16 is a graph of the final signal gain output;

FIG. 17 is a flow chart of multi-system multi-signal synthesis.

Detailed Description

As shown in fig. 1 to 17, the method is based on a multichannel parallel processing architecture technology, and can edit and rapidly process the ultra-wideband time-varying motion multi-system multi-signal in real time, so that the problem of ultra-wideband time-varying motion multi-system signal synthesis can be fundamentally solved. When a user needs to generate a dynamic signal, a signal library developed by the user is selected, an API of a system is called, all signal information is configured through algorithm logic, and sampling rate matching, frequency shift, phase, amplitude, time delay and the like are carried out, so that parameters of a time domain, an energy domain, a frequency domain, a modulation mode, a space domain and the like of a test system signal are changed, and then cyclic reading is carried out, and an infinite-time scene signal can be generated theoretically.

The ultra-wideband time-varying motion multi-system multi-signal synthesis method mainly relates to the following three aspects:

the single-signal independent configuration method adopts single-signal independent configuration, supports each signal to carry out independent parameter configuration, namely only generating independent signals in software, wherein the data length and even the sampling rate of the signals can be different, and then downloading the signals respectively. When playing, the bottom logic will control the single signal output and combine all the signals to output. And the adjustment of the parameters of the single signal is adjusted before all the signals are synthesized, so that the single signal can be independently adjusted and the adjustment can be carried out in real time and on line. The single-signal independent configuration parameters include signal system, center frequency, reference power, attenuation, time delay, phase offset, frequency shift, and the like, and the configuration parameters are schematically shown in fig. 3. And when the system is actually designed, the system is packaged in an API function calling mode. The parameters of each signal can be independently controlled on line and can be independently set when static target simulation is carried out. The center frequency configuration is shown in fig. 4. Under dynamic target antenna scanning, this can be directly achieved by configuring the antenna scanning parameters of the reference power, as shown in fig. 5.

Two, FPGA multichannel signal generation structure

In the process of processing the multi-channel real-time signals, the signal parameters of each channel are controlled on line through software or an API (application program interface), so that the capabilities of on-line switching, editing and switching are obtained.

The hardware system design block 6 is as follows.

The PC software drives the system interface to control each digital module. Each digital block includes independent FPGA and DAC circuits, from channel 1(CH1) through channel n (chn). Meanwhile, the PC software drives the system interface to control the synchronous module. The synchronization module includes a local oscillator and a synchronization circuit. The synchronous module sends synchronous signals to each digital module, and real-time modulation is carried out according to the amplitude and the phase of the feedback signals of each digital module, so that each digital module with good amplitude-phase consistency is obtained.

A plurality of channel signal generation structures are designed in the FPGA, and each channel can independently configure signals and corresponding parameters, and the signals do not affect each other, as shown in fig. 7. In the process of processing the multi-channel real-time signals, the signal parameters of each channel are controlled on line through software or an API (application program interface), so that the capabilities of on-line switching, editing and switching are obtained. The multi-signal channel acquires parameters such as the number and the system of each baseband signal from a DDR memory, baseband oversampling is carried out after baseband buffering, signal resolution is improved, noise is reduced, time delay parameters of the signals are changed in real time according to requirements of users, 8-time interpolation is carried out on the signals, the sampling rate of each path of signals reaches 2.5Gsps to meet the requirement of broadband signal generation, then fundamental wave signals are modulated to corresponding carrier frequencies through orthogonal modulation, finally, generation of the signals is completed through multi-path synthesis and gain control, and the signals are output through DA.

(1) Baseband BUFF

The baseband BUFF can improve the driving capability and isolate the front stage and the rear stage, and the buffer mostly has a tri-state output function. The baseband buffer is used for buffering baseband signals to be transmitted and is realized by using an internal memory in the FPGA. The baseband BUFF circuit and the RAM IP core circuit are shown in figures 8 and 9.

After the design is adopted, when the load does not have the non-gating output and has the high-resistance characteristic, the isolation effect can be achieved; when the driving capability of the bus is not enough to drive the load, the driving function can be achieved. The CPU working at high speed and the peripheral working at low speed play a role in coordination and buffering, and the synchronization of data transmission is realized.

The initial speed output signal simulation is shown in fig. 10 below.

The data transmission image is smooth, so that the data can be smoothly transmitted.

(2) Oversampling design

The sampling frequency 2 times higher than the highest frequency of the signal is the oversampling rate, and the baseband signal is oversampled to recover the original signal from the sampled signal. When a very high sampling frequency is used, the energy of the noise is dispersed to a wider frequency range during quantization, and then if a digital filter is used for filtering, most of the noise can be filtered while the useful signal is kept, so that the signal-to-noise ratio (SNR) is improved. From the equation SNR 6.02N +1.76+10 log (fs/2B), it can be seen that the SNR is larger as the sampling rate fs is larger (B is the bandwidth in the equation). Three examples of sampling are shown in fig. 10. The nyquist sampling frequency is 2 times the highest frequency of the signal, the undersampling frequency is lower than 2 times the highest frequency of the signal, and the oversampling frequency is higher than 2 times the highest frequency of the signal.

(3) Variable time delay

The synchronization is ensured by delaying when the FPGA boards are synchronized or the signals are output externally, so that the information can be received correctly. The delay amount can be changed independently at any time according to actual requirements. In a digital circuit, signal delay is realized using a register, a flip-flop, or the like, and a variable delay circuit is shown in fig. 11. When different ABCD binary numbers are input, different numbers of unit clock delays can be realized, Din is an input signal, and Dout is a signal output after delay.

And a digital circuit is built by using a D trigger, a counter and a logic gate, is programmed by using a hardware description language (VHDL, Verilog) language and is downloaded into an FPGA chip, so that the variable delay function is completed. The synchronism of signal output is ensured so that information can be correctly received.

(4) Data interpolation

The meaning is that sampling is carried out by adopting a mode of 8 times of the original sampling rate, and the new sampling rate reaches 2.5 GHz. This requires that 7 interpolated values be inserted between every two points of the original sample sequence. The interpolated value here may be 0, and then smoothed by a filter. A schematic of the 3-fold interpolation is shown in fig. 12.

(5) Quadrature modulation

Modulation is to use a carrier with a higher frequency to carry a signal to be transmitted (baseband signal) so that the signal is suitable for transmission in a channel (the frequency of the baseband signal is low, is easily interfered, and is not suitable for long-distance transmission). In the quadrature modulation, two quadrature signals (generally, sin and cos signals) with a phase difference pi/2 are multiplied by an I signal (also called an in-phase signal) and a Q signal (also called a quadrature signal), and then added to form a single signal, which is then transmitted. The basic functional block diagram of quadrature modulation is shown in fig. 13.

Is expressed by the formula

s(t)＝I(t)cos2πf₀t-Q(t)sin2πf₀t

Two quadrature signals (sin and cos signals) with a phase difference pi/2 are multiplied by an I signal (also called an in-phase signal) and a Q signal (also called a quadrature signal) respectively, and then added to synthesize a signal. And finally, programming program codes of the multiplier and the adder by using hardware description languages (VHDL and Verilog), and downloading the program codes into the FPGA after debugging. The baseband signal can be shifted at higher frequency, and the method is suitable for long-distance transmission and is not easy to be interfered.

(6) Multipath synthesis design

Multiplexing is also called time division multiplexing, and in order to improve the channel and spectrum utilization rate, a plurality of single-channel signals are concentrated into one channel for transmission, and meanwhile, the power of the signals is amplified. To overcome the signal loss, the energy (power) of the transmitted signal can be increased by gain control, which allows a receiver at a long distance to receive the signal with a certain energy.

The initial signal gain output plot is as follows:

it can be seen that the overall power output power of the signal is uneven, a large time slot is provided, processor resources are wasted, and the efficiency is low.

The design diagram of the multiplex synthesis time slot allocation and gain control circuit is as follows:

a plurality of single-channel signals are concentrated into one channel. Then the power of each path of signal is basically the same through a gain control circuit.

Simulation results in the final signal gain output diagram 16 as follows:

the overall power output power of the signal is relatively flat, no time slot is idle, and processor resources are utilized to the maximum efficiency.

Three-body multi-signal synthesis process

In FPGA design, a corresponding scene is established, a plurality of target signals which possibly exist are selected, and corresponding signals are generated through a signal library. And then downloading the data to the DDR memory array through the PCIe bus, thereby completing the downloading of the data. For multiple signals, each signal has separate storage space. When the downloading of the signals is completed, the scene parameters need to be configured, mainly the information of amplitude, frequency, phase and the like of each signal needs to be configured. After the data download and parameter configuration are completed, the trigger may be waited for. After triggering, the multichannel signal generating structure obtains data of each signal by controlling DDR, completes single signal processing through a corresponding algorithm channel, and finally synthesizes all signals together in a frequency division multiplexing mode through an orthogonal modulation mode for outputting. The multi-system multi-signal synthesis flow is shown in fig. 17.

Firstly, all original target signals are generated and downloaded by software, the total data size is limited by a memory, but the sampling rate can be set to be lower because the signals are generated according to a single signal format, and the limitation on the memory is small and almost negligible under the comprehensive consideration. Each target signal occupies a separate slice of area in memory. When playing, all target signals are read circularly at the same time, theoretically, signals of infinite time can be generated. And finally, all target signals are synthesized and output after gain is adjusted.