1. The test method for the performance test of the speed vibration combined type sensor is characterized by comprising the following steps of:

the CPLD main control chip collects and calculates the vibration signal and the speed signal and then stores the vibration signal and the speed signal into a storage unit;

after sampling is finished, the motor is controlled to stop rotating through a control signal generated by the upper computer;

comparing the test data of the memory cell with a theoretical value to test;

the speed signal and the vibration signal are generated by driving a speed vibration combined sensor by the motor, the vibration signal is converted into a pulse signal through a digital-to-analog converter and then transmitted to the CPLD main control chip, and the speed signal is directly transmitted to the CPLD main control chip.

2. The test method according to claim 1, wherein the speed signal and the vibration signal are filtered before being transmitted to the CPLD main control chip.

3. The method according to claim 1, wherein in the testing process, the CPLD master chip includes a frequency divider for providing different clock input signals, so as to realize selectable sampling frequency.

4. The method according to claim 1, wherein during the testing, a negative delay counter is included in the CPLD master chip, and the negative delay counter counts to cancel sampling delay and read/write delay.

5. The method according to claim 1, wherein during the test, the axial acceleration of the sensor is used for triggering to stop sampling, and the method for triggering specifically comprises: and the sampling values of continuous ten points are larger than the trigger value, and the trigger condition is judged to be met.

6. A testing arrangement for speed vibration combination formula sensor capability test, its characterized in that includes:

an acquisition module: the CPLD main control chip collects and calculates the speed signal and the vibration signal and then stores the speed signal and the vibration signal into a storage unit;

the speed signal and the vibration signal are generated by driving a speed vibration combined sensor by the motor module, the vibration signal is converted into a pulse signal through digital-to-analog conversion and then transmitted to the CPLD main control chip, and the speed signal is directly transmitted to the CPLD main control chip;

a test module: comparing the test data with a theoretical value to perform a test;

a motor module: and receiving a signal of the CPLD main control chip, and driving the equipment to be tested to generate a speed signal and a vibration signal.

7. A computer-readable storage medium, on which a computer program is stored, characterized in that the program, when executed, carries out the steps of the method of any one of claims 1 to 5.

8. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the steps of the method according to any of claims 1-5 are implemented when the program is executed by the processor.

Background

The speed vibration combined sensor is a multifunctional sensor specially used in the field of rail transit, namely the rotating speed of train wheels can be output to a control system through pulses or a bus interface, and the vibration state of an axle can be monitored. At present, no test method and device for testing the functions and the performance of the speed vibration combined sensor exist in the market.

In view of the above, the present invention is particularly proposed.

Disclosure of Invention

The invention aims to provide a testing method and a testing device for testing the performance of a speed vibration combined sensor, the testing device and the testing method can test the speed vibration combined sensor, the testing device and the testing device adopt a negative delay counter mode to offset delay and an error trigger prevention mechanism to ensure the accuracy and precision of the test to the maximum extent, and meanwhile, the testing device also has the functions of selectable sampling frequency, high overload resistance, temporary modification of a testing protocol and the like, can adapt to different testing requirements, and has better applicability to different devices to be tested. In order to achieve the above purpose of the present invention, the following technical solutions are adopted:

in a first aspect, the invention discloses a testing method for a performance test of a speed vibration combined sensor, which comprises the following steps:

the CPLD main control chip collects and calculates the vibration signal and the speed signal and then stores the vibration signal and the speed signal into a storage unit;

after sampling is finished, the motor is controlled to stop rotating through a control signal generated by the upper computer;

comparing the test data of the memory cell with a theoretical value to test;

the speed signal and the vibration signal are generated by driving the speed vibration combined sensor by the motor, the vibration signal is converted into a pulse signal through digital-to-analog conversion and then transmitted to the main control chip, and the speed signal is directly transmitted to the main control chip.

In a second aspect, the invention discloses a method and a device for testing the performance of a speed vibration combined sensor, wherein the device comprises:

the acquisition module is used for acquiring and calculating the vibration signal and the speed signal and storing the vibration signal and the speed signal into the storage unit;

the test module compares the test data with a theoretical value to test;

and the motor module receives the signal of the main control chip and drives the equipment to be tested to generate a speed signal and a vibration signal.

In a third aspect, the invention discloses a computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the method according to the first aspect.

In a fourth aspect, the invention discloses a computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the method according to the first aspect when executing the program.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

FIG. 1 is a schematic flow chart of a testing method according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a testing apparatus according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a computer device according to an embodiment of the present invention.

Detailed Description

The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings and the detailed description, but those skilled in the art will understand that the following described embodiments are some, not all, of the embodiments of the present invention, and are only used for illustrating the present invention, and should not be construed as limiting the scope of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. The examples, in which specific conditions are not specified, were conducted under conventional conditions or conditions recommended by the manufacturer. The reagents or instruments used are not indicated by the manufacturer, and are all conventional products available commercially.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

The invention discloses a testing method for testing the performance of a speed vibration combined sensor, which comprises the following steps:

the CPLD main control chip collects and calculates the vibration signal and the speed signal and then stores the vibration signal and the speed signal into a storage unit;

comparing the test data of the memory cell with a theoretical value to test;

after the test is passed, the motor is controlled to stop rotating by a control signal generated by the upper computer;

the speed signal and the vibration signal are generated by driving the speed vibration combined sensor by the motor, the vibration signal is converted into a pulse signal through digital-to-analog conversion and then transmitted to the main control chip, and the speed signal is directly transmitted to the main control chip.

At present, speed vibration combined sensors exist in the market, but a testing method and a testing device specially aiming at the sensors to perform performance testing are not provided, so that the performance of a factory product cannot be guaranteed, and the importance of the invention is particularly highlighted.

Fig. 1 is a schematic flow chart of a method for testing performance of a speed vibration combined sensor, which is applied to the testing apparatus and shown in fig. 1, when a device to be tested is to be tested for performance, the method includes the following steps:

and S101, sampling the vibration signal and the speed signal by the CPLD main control chip, and storing the vibration signal and the speed signal into a storage unit after calculation.

Before starting to sample, the main control chip can firstly adjust the sampling frequency, the negative delay counter, the motor rotating speed and other numerical values, and the specific implementation mode is as follows:

the master control chip is internally provided with a frequency divider, and different clock input signals can be provided by using the frequency divider so as to realize selectable sampling frequency.

The main control chip offsets delay brought by sampling and reading and writing by adjusting a negative delay counter inside the main control chip and by means of sampling in advance and reading and writing in advance, so that a test result is more accurate. For example, sample data is acquired every five seconds, and if each sampling is delayed by one second, the sampling is performed one second in advance, so that the data can be acquired just after the sampling delay of one second, and the function is realized by a negative delay counter; the read and write delays are the same.

The main control chip sends a control signal to the server, and the server can realize accurate control over the motor in the following specific mode:

the servo is mainly positioned by pulses, and the servo motor can rotate by an angle corresponding to 1 pulse after receiving 1 pulse, so that the displacement is realized. The servo motor has the function of sending out pulses, so that the servo motor can send out a corresponding number of pulses every time the servo motor rotates for one angle. Thus, a pulse received by the servo motor forms a response, or closed loop. Therefore, the system can know how many pulses are sent to the servo motor and how many pulses are received. Therefore, the rotation of the motor can be accurately controlled, and accurate positioning is realized.

Before the main control chip calculates and processes the data to be measured, the data to be measured needs to be filtered through a signal conditioning module, and common signal conditioning devices are provided with low-pass filters aiming at 50hz or 60hz and used for filtering part of noise mainly coming from electric wires and mechanical equipment.

It is worth mentioning that the rotation speed of the motor is set in advance, is not constant, and generally is gradually increased in a step shape.

And S102, stopping the motor from rotating through the control signal and enabling the test bench to be in standby.

The testing device is triggered by adopting the axial acceleration of the equipment to be tested, when the axial acceleration value is greater than a set value, the testing device is triggered, the CPLD main control chip sends out a control signal to stop the motor from rotating, and the specific triggering method comprises the following steps: and the sampling values of continuous ten points are larger than the trigger value, and the trigger condition is judged to be met. Therefore, the influence of unnecessary influence on false triggering, which is mainly the instantaneous peak pulse of the motor starting, can be avoided, and the influence of external conditions such as personnel walking, mechanical noise and the like can be avoided.

And S103, analyzing and judging the test data by the upper computer.

And after the upper computer takes out the test data from the storage unit, analyzing the test data by using a test program in the upper computer, comparing the test data with a theoretical value, and if the difference value is within a certain interval, judging that the tested equipment passes the test. The size of the interval value is determined according to specific parameters of the equipment to be tested.

The invention correspondingly discloses a speed vibration combined sensor performance testing device, which comprises the following components:

the acquisition module 201 is used for acquiring and calculating the vibration signal and the speed signal and storing the vibration signal and the speed signal into a storage unit;

a test module 202 for comparing the test data with a theoretical value to perform a test;

and the motor module 203 receives the signal of the main control chip and drives the device to be tested to generate a speed signal and a vibration signal.

When the test device is used, the motor module drives the equipment to be tested to generate a signal to be tested, the signal to be tested is simply calculated after being collected by the collection module, finally, the test module analyzes test data and compares the test data with a theoretical value to obtain a test result, so that the operation flow of the whole test device is completed, the test on the speed and the vibration characteristic value of the equipment to be tested can be realized by using the test device, and the performance of the equipment to be tested is ensured.

If the specific parameters of the equipment to be tested are unknown, the sampling frequency, the negative delay counter, the rotating speed and the like cannot be set, the parameter condition of the equipment to be tested needs to be tested step by step, and the condition of overhigh load can possibly occur.

Fig. 3 is a schematic structural diagram of a computer device disclosed in the present invention, and referring to fig. 3, the computer device 300 at least includes a memory 302 and a processor 301; the memory 302 is connected to the processor via a communication bus 303 for storing computer instructions executable by the processor 301, and the processor 301 is configured to read the computer instructions from the memory 302 to implement the steps of the sensor performance testing method according to any of the embodiments.

Technical solutions of the present invention have been described with reference to preferred embodiments shown in the drawings, but it is apparent that the scope of the present invention is not limited to these specific embodiments, as will be readily understood by those skilled in the art. Equivalent changes or substitutions of related technical features can be made by those skilled in the art without departing from the principle of the invention, and the technical scheme after the changes or substitutions can fall into the protection scope of the invention.

For the above-mentioned apparatus embodiments, since they basically correspond to the method embodiments, reference may be made to the partial description of the method embodiments for relevant points. The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the disclosed solution. One of ordinary skill in the art can understand and implement it without inventive effort.

Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including by way of example semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices), magnetic disks (e.g., internal magnetic disks or removable disks), magneto-optical disks, and CD ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

Finally, it should be noted that: while this specification contains many specific implementation details, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features specific to particular embodiments of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. In other instances, features described in connection with one embodiment may be implemented as discrete components or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

Thus, particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results. Further, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some implementations, multitasking and parallel processing may be advantageous.

The above description is only exemplary of the present disclosure and should not be taken as limiting the disclosure, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.