1. A driving circuit, applied to a display panel, the driving circuit comprising: a multi-stage shift register;

the shift register comprises an input module, a voltage division module, a turn-off module and an output module;

the input module is connected between a first voltage signal end and a first node and is used for starting in an input stage so as to output a first voltage signal provided by the first voltage signal end to the first node;

the voltage division module is internally provided with a second node, a first end of the voltage division module is connected to a second voltage signal end, a second end of the voltage division module is connected to a third voltage signal end, a first control end of the voltage division module is connected to a first shift register signal end, a second control end of the voltage division module is connected to a second shift register signal end, a third control end of the voltage division module is connected to the first node, and the voltage division module is used for adjusting the potential of the second node;

the turn-off module is connected between the first node and a fourth voltage signal end and is used for turning on in a turn-off stage so as to pull down the potential of the first node to a fourth voltage signal provided by the fourth voltage signal end;

the output module is connected between a first clock signal end and the output end of the shift register, a coupling capacitor is coupled between the output end of the shift register and the first node, and the output module is used for being started in an output stage so as to output the first clock signal provided by the first clock signal end to the output end of the shift register.

2. The driving circuit of claim 1, wherein the voltage divider module further has a third terminal and a fourth terminal, the third terminal of the voltage divider module is connected to the first voltage signal terminal and the fourth terminal is connected to the fourth voltage signal terminal.

3. The driving circuit according to claim 1, wherein the control terminal of the shutdown module is connected to the first shift register signal terminal.

4. The driving circuit according to claim 1, wherein the first shift register signal terminal is connected to an output terminal of the next stage of the shift register, and the second shift register signal terminal is connected to an output terminal of the previous stage of the shift register.

5. The drive circuit according to claim 1 or 2, wherein the shift register includes a first scan mode and a second scan mode;

in the first scanning mode, the voltage signals provided by the first voltage signal terminal and the second voltage signal terminal are high level signals greater than 0V, and the voltage signals provided by the third voltage signal terminal and the fourth voltage signal terminal are low level signals less than or equal to 0V;

in the second scan mode, the voltage signals provided by the first voltage signal terminal and the third voltage signal terminal are low level signals smaller than or equal to 0V, and the voltage signals provided by the fourth voltage signal terminal and the second voltage signal terminal are high level signals larger than 0V.

6. The driving circuit of claim 1, wherein the input module comprises a first transistor;

the first transistor is connected between the first voltage signal end and the first node, and the control end of the first transistor is connected to the second shift register signal end.

7. The driving circuit of claim 1, wherein the output module comprises a second transistor;

the second transistor is connected between the first clock signal terminal and the output terminal of the shift register, and the control terminal of the second transistor is connected to the first node.

8. The driving circuit according to claim 7, further comprising: the gate metal layer, the source drain metal layer and the first metal layer are arranged in different layers, and the first metal layer comprises a first bridge structure;

the grid electrode of the second transistor and the first node are connected to the same first bridge-spanning structure through a first bridge wire-changing hole, and the grid metal layer and the metal layer where the first node is located are arranged on different layers.

9. The driving circuit of claim 8, wherein the first node is on the same layer as the source-drain metal layer.

10. The driving circuit according to claim 1, wherein the voltage dividing module comprises a first voltage dividing unit and a second voltage dividing unit;

the first voltage division unit is connected between the second voltage signal end and the second node, and a first control end of the first voltage division unit is connected to the first shift register signal end;

the second voltage division unit is connected between the third voltage signal end and the second node, and a first control end of the second voltage division unit is connected to the second shift register signal end;

the first voltage division unit is used for outputting a second voltage signal provided by the second voltage signal end to the second node when the first voltage division unit is started;

the second voltage division unit is used for outputting a third voltage signal provided by the third voltage signal end to the second node when the second voltage division unit is started.

11. The drive circuit according to claim 10,

the first voltage division unit comprises a third transistor and a fourth transistor, the third transistor and the fourth transistor are both connected between the second voltage signal end and the second node, a control end of the third transistor is connected to the first shift register signal end, and a control end of the fourth transistor is connected to the second voltage signal end;

the second voltage division unit comprises a fifth transistor and a sixth transistor, the fifth transistor and the sixth transistor are both connected between the third voltage signal end and the second node, the control end of the fifth transistor is connected to the second shift register signal end, and the control end of the sixth transistor is connected to the first node.

12. The driving circuit according to claim 2, wherein the voltage dividing module comprises a first voltage dividing unit and a second voltage dividing unit;

the first end of the first voltage division unit is connected to the first voltage signal end, the second end of the first voltage division unit is connected to the second voltage signal end, the third end of the first voltage division unit is connected to the second node, and the first control end of the first voltage division unit is connected to the first shift register signal end;

the first end of the second voltage division unit is connected to the third voltage signal end, the second end of the second voltage division unit is connected to the fourth voltage signal end, the third end of the second voltage division unit is connected to the second node, and the first control end of the second voltage division unit is connected to the second shift register signal end;

the first voltage division unit is used for outputting a first voltage signal provided by the first voltage signal end or a second voltage signal provided by the second voltage signal end to the second node when the first voltage division unit is started;

the second voltage division unit is configured to output a third voltage signal provided by the third voltage signal terminal or a fourth voltage signal provided by the fourth voltage signal terminal to the second node when the second voltage division unit is turned on.

13. The drive circuit according to claim 12,

the first voltage division unit includes a third transistor and a fourth transistor, the third transistor is connected between the first voltage signal terminal and the second node, the fourth transistor is connected between the second voltage signal terminal and the second node, a control terminal of the third transistor is connected to the first shift register signal terminal, and a control terminal of the fourth transistor is connected to the second voltage signal terminal;

the second voltage division unit comprises a fifth transistor and a sixth transistor, the fifth transistor is connected between the fourth voltage signal end and the second node, the sixth transistor is connected between the third voltage signal end and the second node, the control end of the fifth transistor is connected to the second shift register signal end, and the control end of the sixth transistor is connected to the first node.

14. The driving circuit according to claim 11 or 13, wherein during the input phase, the input module, the second voltage dividing unit and the fourth transistor are all turned on, the first voltage signal is written into the first node, and a third voltage signal provided by the third voltage signal terminal is written into the second node.

15. The driving circuit according to claim 11 or 13, wherein in the output stage, the output module, the fourth transistor and the sixth transistor are all turned on, and a first clock signal provided by the first clock signal terminal is output to an output terminal of the shift register.

16. The drive circuit according to claim 11 or 13, further comprising: the gate metal layer, the source drain metal layer and the first metal layer are arranged in different layers, and the first metal layer comprises a second bridge-spanning structure;

and the grid electrode of the fourth transistor and the source electrode of the fourth transistor are connected to the same second bridge-spanning structure by adopting a second bridge wire-changing hole.

17. The drive circuit according to claim 1, wherein the shift register further comprises: a pull-down module;

the control end of the pull-down module is connected to the second node, the first end of the pull-down module is connected to the first node, the second end of the pull-down module is connected to the output end of the shift register, and the third end of the pull-down module is connected to the third voltage signal end, so that when the pull-down module is started, the potential of the first node and the potential of the output end of the shift register are pulled down.

18. The driving circuit of claim 17, wherein the pull-down module comprises a first pull-down unit and a second pull-down unit;

the first pull-down unit is connected between the first node and the third voltage signal end, and the control end of the first pull-down unit is connected to the second node;

the second pull-down unit is connected between the output end of the shift register and the third voltage signal end, and the control end of the second pull-down unit is connected to the second node;

the first pull-down unit and the second pull-down unit are turned on or turned off simultaneously, and when the first pull-down unit and the second pull-down unit are turned on, the potential of the first node and the potential of the output end of the shift register are pulled down to a third voltage signal provided by the third voltage signal end.

19. The drive circuit according to claim 18,

the first pull-down unit includes a seventh transistor,

the second pull-down unit includes an eighth transistor.

20. The driving circuit according to claim 19, further comprising: the gate metal layer, the source drain metal layer and the first metal layer are arranged in different layers, and the first metal layer comprises a third bridge structure;

and the grid electrode of the seventh transistor and the second node are connected to the same third bridging structure by adopting a third bridging wire changing hole, and the grid electrode metal layer and the second node are arranged on different layers of the metal layer.

21. The driving circuit of claim 20, wherein the second node is on the same layer as the source-drain metal layer.

22. The driving circuit according to claim 17, wherein the operation phase of the shift register comprises a first pull-down phase and a second pull-down phase;

the first pull-down stage is executed before the input stage, the pull-down module executes first pull-down operation, and the potential of the output end of the shift register is pulled down;

and the second pull-down stage is executed after the output stage, and the pull-down module executes second pull-down operation to pull down the potential of the output end of the shift register.

23. The driving circuit according to claim 22, wherein the turn-off phase and the second pull-down phase are performed sequentially; alternatively, the first and second electrodes may be,

the turn-off phase and the second pull-down phase are sequentially executed, and at least partial time periods of the turn-off phase and the second pull-down phase are overlapped.

24. The driving circuit according to claim 1, wherein the turn-off module comprises a ninth transistor, the ninth transistor is connected between the first node and the fourth voltage signal terminal, and a control terminal of the ninth transistor is connected to the first shift register signal terminal.

25. The drive circuit according to claim 1, wherein the shift register further comprises: the reset module is connected between the first node and the third voltage signal end and is used for starting in a reset stage so as to reset the potential of the first node to a third voltage signal provided by the third voltage signal end;

the shift register further includes: the initialization module is connected between the output end of the shift register and the third voltage signal end and is used for starting at an initialization stage so as to initialize the potential of the output end of the shift register to the third voltage signal.

26. A display device, comprising: a driver circuit as claimed in any one of claims 1 to 25.

Background

In the display device, the pixel array comprises grid scanning lines and data lines which are staggered horizontally and vertically. In order to realize the progressive scanning of the pixel array, a gate driving circuit is generally used to drive the pixel units in the pixel array.

The gate driving circuit includes a plurality of cascaded shift registers, and a circuit constituting the shift register includes a plurality of transistors and capacitors. With the rapid development of display technology, users have higher and higher requirements for the display effect of the display panel, and accordingly, the requirements for the stability of the gate driving circuit are higher and higher.

The circuit of the shift register has a connection node, and in the working process of the shift register, if the potential of the connection node cannot be adjusted to the required potential in time, the output signal of the shift register is affected, and the stability of the gate driving circuit is affected.

Disclosure of Invention

The embodiment of the invention provides a driving circuit and a display device, which are used for improving the stability of the driving circuit.

In a first aspect, an embodiment of the present invention provides a driving circuit, which is applied in a display panel, and the driving circuit includes: a multi-stage shift register;

the shift register comprises an input module, a voltage division module, a turn-off module and an output module;

the input module is connected between a first voltage signal end and a first node and is used for starting in an input stage so as to output a first voltage signal provided by the first voltage signal end to the first node;

the voltage division module is internally provided with a second node, a first end of the voltage division module is connected to a second voltage signal end, a second end of the voltage division module is connected to a third voltage signal end, a first control end of the voltage division module is connected to a first shift register signal end, a second control end of the voltage division module is connected to a second shift register signal end, a third control end of the voltage division module is connected to the first node, and the voltage division module is used for adjusting the potential of the second node;

the turn-off module is connected between the first node and a fourth voltage signal end and is used for turning on in a turn-off stage so as to pull down the potential of the first node to a fourth voltage signal provided by the fourth voltage signal end;

the output module is connected between a first clock signal end and the output end of the shift register, a coupling capacitor is coupled between the output end of the shift register and the first node, and the output module is used for being started in an output stage so as to output the first clock signal provided by the first clock signal end to the output end of the shift register.

In a second aspect, an embodiment of the present invention further provides a display device, including the driving circuit provided in the above aspect.

In the driving circuit provided in the embodiment of the present invention, by setting that the first control end of the voltage dividing module of the shift register is connected to the first shift register signal end, the second control end is connected to the second shift register signal end, and the third control end is connected to the first node, the voltage dividing module can be controlled to rapidly adjust the potential of the second node to a desired potential through the first shift register signal of the first shift register signal end, the second shift register signal of the second shift register signal end, and the potential of the first node, so as to improve the output performance of the shift register and improve the stability of the driving circuit.

Drawings

FIG. 1 is a circuit diagram of a shift register of the prior art;

fig. 2 is a schematic structural diagram of a shift register according to an embodiment of the present invention;

FIG. 3 is a circuit diagram of a shift register according to an embodiment of the present invention;

FIG. 4 is a timing diagram of a shift register according to an embodiment of the present invention;

FIG. 5 is a diagram illustrating a shift register at a first pull-down stage according to an embodiment of the present invention;

FIG. 6 is a diagram illustrating a shift register in an input stage according to an embodiment of the present invention;

FIG. 7 is a diagram of a shift register in an output stage according to an embodiment of the present invention;

FIG. 8 is a diagram illustrating a shift register at a second pull-down stage according to an embodiment of the present invention;

FIG. 9 is a circuit diagram of another shift register according to an embodiment of the present invention;

FIG. 10 is a diagram illustrating an alternative shift register according to an embodiment of the present invention;

FIG. 11 is a circuit diagram of another shift register according to an embodiment of the present invention;

fig. 12 is a schematic diagram of a partial structure of a shift register according to an embodiment of the present invention;

FIG. 13 is a partial schematic diagram of another shift register according to an embodiment of the present invention;

FIG. 14 is a partial schematic diagram of another shift register according to an embodiment of the present invention;

fig. 15 is a schematic structural diagram of a driving circuit according to an embodiment of the present invention;

FIG. 16 is a schematic diagram of a driving timing sequence of a driving circuit according to an embodiment of the present invention;

fig. 17 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Fig. 1 is a circuit diagram of a shift register in the prior art, and as shown in fig. 1, the circuit of the shift register includes a first node P and a second node Q, wherein a high and a low of the second node Q determine turning on or off of transistors M2 and M5, which in turn affects a potential of the first node P and an output signal of an output terminal OUT of the shift register. In the conventional circuit shown in fig. 1, the potential of the second node Q is determined by the on-off states of the transistors M7 and M3, the on-off state of the transistor M7 is controlled by the output signal of the transistor M8, and the on-off state of the transistor M3 is controlled by the potential of the first node P, which results in a delay in the adjustment of the potential of the second node Q, and it is difficult to quickly adjust the potential of the second node Q to a desired potential, which may affect the output signal of the shift register, such as causing a delay in the output signal and affecting the stability of the driving circuit.

In order to solve the above problem, an embodiment of the present application provides a driving circuit, which is applied in a display panel, and includes a multi-stage shift register; the shift register comprises an input module, a voltage division module, a turn-off module and an output module; the input module is connected between the first voltage signal end and the first node and is used for starting in an input stage so as to output a first voltage signal provided by the first voltage signal end to the first node; the voltage dividing module is internally provided with a second node, the first end of the voltage dividing module is connected to the second voltage signal end, the second end of the voltage dividing module is connected to the third voltage signal end, the first control end of the voltage dividing module is connected to the first shift register signal end, the second control end of the voltage dividing module is connected to the second shift register signal end, the third control end of the voltage dividing module is connected to the first node, and the voltage dividing module is used for adjusting the potential of the second node; the turn-off module is connected between the first node and the fourth voltage signal end and is used for turning on in a turn-off stage so as to pull down the potential of the first node to a fourth voltage signal provided by the fourth voltage signal end; the output module is connected between the first clock signal terminal and the output terminal of the shift register, a coupling capacitor is coupled between the output terminal of the shift register and the first node, and the output module is used for being started in an output stage so as to output the first clock signal provided by the first clock signal terminal to the output terminal of the shift register.

By adopting the technical scheme, the voltage division module can be controlled to rapidly adjust the potential of the second node to the required potential through the first shift register signal of the first shift register signal end, the second shift register signal of the second shift register signal end and the potential of the first node, so that the output performance of the shift register is improved, and the stability of the driving circuit is improved.

The above is the core idea of the present application, and based on the embodiments in the present application, a person skilled in the art can obtain all other embodiments without making creative efforts, which belong to the protection scope of the present application. The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

Fig. 2 is a schematic structural diagram of a shift register according to an embodiment of the present invention. The present embodiment provides a driving circuit, which is applied to a display panel, and includes a plurality of stages of shift registers 100 as shown in fig. 2; referring to fig. 2, the shift register 100 includes an input module 10, a voltage dividing module 20, a shutdown module 30, and an output module 40; the input module 10 is connected between the first voltage signal terminal FW and the first node P, and is configured to be turned on in an input phase to output a first voltage signal provided by the first voltage signal terminal FW to the first node P; the voltage dividing module 20 has a second node Q inside, the first end of the voltage dividing module 20 is connected to the second voltage signal terminal VGH and the second end is connected to the third voltage signal terminal VGL, the first control end of the voltage dividing module 20 is connected to the first shift register signal terminal Gn +1, the second control end is connected to the second shift register signal terminal Gn-1, and the third control end is connected to the first node P, the voltage dividing module 20 is configured to adjust the potential of the second node Q; the shutdown module 30 is connected between the first node P and the fourth voltage signal terminal BW, and is configured to turn on in a shutdown phase to pull down a potential of the first node P to a fourth voltage signal provided by the fourth voltage signal terminal BW; the output module 40 is connected between the first clock signal terminal CLK and the output terminal OUT of the shift register, a coupling capacitor C is coupled between the output terminal OUT of the shift register and the first node P, and the output module 40 is configured to be turned on in the output stage to output the first clock signal provided by the first clock signal terminal CLK to the output terminal OUT of the shift register.

The driving circuit includes a plurality of stages of shift registers 100, and each stage of shift registers 100 may sequentially provide a scan signal to a corresponding gate line. Specifically, for one shift register, the first shift register signal terminal Gn +1 may be connected to the output terminal OUT of the next shift register, and the second shift register signal terminal Gn-1 may be connected to the output terminal OUT of the previous shift register, so that cascade connection of multiple shift registers in the driving circuit may be implemented, and each shift register sequentially provides a scanning signal to a corresponding gate line.

In one duty cycle of the shift register 100, an input stage, an output stage, and a shutdown stage are sequentially performed. In the input stage, the input module 10 is turned on, and outputs the first voltage signal provided by the first voltage signal terminal FW to the first node P to charge the first node P, and the coupling capacitor C stores the potential of the first node P; then, in the output stage, the output module 40 is turned on, outputs the first clock signal provided by the first clock signal terminal CLK to the output terminal OUT of the shift register, and provides the scan signal to the corresponding gate line; then, the shutdown phase is entered, the shutdown module 30 is turned on, and the potential of the first node P is pulled down to the fourth voltage signal provided by the fourth voltage signal terminal BW.

In this embodiment, the shift register further includes a voltage dividing module 20, the voltage dividing module 20 has a second node Q inside, and is connected between the second voltage signal end VGH and the third voltage signal end VGL, and by controlling the on-off state of the circuit between the second voltage signal end VGH and the second node Q and between the second node Q and the third voltage signal end VGL, the second voltage signal provided by the second voltage signal end VGH or the third voltage signal provided by the third voltage signal end VGL can be transmitted to the second node Q, so as to adjust the potential of the second node Q.

Specifically, when the second voltage signal terminal VGH is turned on and the second node Q is turned off, the voltage dividing module 20 outputs the second voltage signal of the second voltage signal terminal VGH to the second node Q; when the second voltage signal terminal VGH is turned on, and the second node Q is turned on, the voltage divider module 20 outputs the third voltage signal of the third voltage signal terminal VGL to the second node Q. The second voltage signal may be, for example, a high level signal greater than 0V, and the third voltage signal may be, for example, a low level signal less than or equal to 0V.

In this embodiment, the voltage dividing module 20 has a plurality of control terminals, the first control terminal is connected to the first shift register signal terminal Gn +1, the second control terminal is connected to the second shift register signal terminal Gn-1, and the third control terminal is connected to the first node P, so that a plurality of transmission paths can be provided among the second voltage signal terminal VGH, the second node Q, and the third voltage signal terminal VGL in the voltage dividing module 20, the plurality of control terminals respectively control on/off of the plurality of transmission paths, and the plurality of transmission paths are used to rapidly adjust the potential of the second node Q to a desired potential, thereby solving the delay problem in the prior art, improving the output performance of the shift register, and improving the stability of the driving circuit.

To sum up, in the driving circuit provided in the embodiment of the present invention, by setting that the first control end of the voltage dividing module of the shift register is connected to the first shift register signal end, the second control end is connected to the second shift register signal end, and the third control end is connected to the first node, the voltage dividing module can be controlled to rapidly adjust the potential of the second node to the required potential through the first shift register signal of the first shift register signal end, the second shift register signal of the second shift register signal end, and the potential of the first node, so as to improve the output performance of the shift register and improve the stability of the driving circuit.

As shown in fig. 2, in the present embodiment, the shift register includes a first voltage signal terminal FW, a second voltage signal terminal VGH, a third voltage signal terminal VGL, a fourth voltage signal terminal BW, and a shutdown module 30, so that the shutdown module 30 is controlled to be turned on and off, and the voltage signals input to the first voltage signal terminal FW and the fourth voltage signal terminal BW are controlled, so that the pixel array can be scanned in two different scanning manners, namely, in a forward scanning manner and in a reverse scanning manner, so that the shift register includes a first scanning mode (forward scanning mode) and a second scanning mode (reverse scanning mode), where the forward scanning manner is scanning from a first row of the pixel array to an nth row of the pixel array, the reverse scanning manner is scanning from the nth row of the pixel array to the first row of the pixel array, and N is an integer greater than 1. Specifically, in the selectable first scan mode (forward scan mode), the voltage signals provided by the first voltage signal terminal FW and the second voltage signal terminal VGH are high-level signals greater than 0V, and the voltage signals provided by the third voltage signal terminal VGL and the fourth voltage signal terminal BW are low-level signals less than or equal to 0V; in the second scan mode (reverse scan mode), the voltage signals provided by the first voltage signal terminal FW and the third voltage signal terminal VGL are low level signals less than or equal to 0V, and the voltage signals provided by the fourth voltage signal terminal BW and the second voltage signal terminal VGH are high level signals greater than 0V.

Next, the structure of the shift register and the operation thereof will be further explained in conjunction with the operation principle of the first scan mode (forward scan mode).

Referring to fig. 2, optionally, the shift register further includes a pull-down module 50; the control terminal of the pull-down module 50 is connected to the second node Q, the first terminal of the pull-down module 50 is connected to the first node P, the second terminal of the pull-down module is connected to the output terminal OUT of the shift register, and the third terminal of the pull-down module 50 is connected to the third voltage signal terminal VGL, so that when the shift register is turned on, the voltage level of the first node P and the voltage level of the output terminal OUT of the shift register are pulled down.

Since the control terminal of the pull-down module 50 is connected to the second node Q, and the pull-down module 50 is connected between the first node P and the third voltage signal terminal VGL, and between the output terminal OUT of the shift register and the third voltage signal terminal VGL, the potential of the second node Q determines the on-off state of the pull-down module 50, and further determines the potentials of the first node P and the output terminal OUT of the shift register, obviously, the potential of the second node Q can be rapidly adjusted in different working stages, which is an important condition for improving the output performance of the shift register.

Specifically, when the potential of the second node Q is in the state of the enable level, the pull-down module 50 is turned on, so that the third voltage signal of the third voltage signal terminal VGL is transmitted to the first node P and the output terminal OUT of the shift register, and the potential of the first node P and the potential of the output terminal OUT of the shift register are pulled down; when the potential of the second node Q is in the non-enabled level state, the pull-down module 50 is turned off, and the third voltage signal of the third voltage signal terminal VGL is not transmitted to the first node P and the output terminal OUT of the shift register, so that the potential of the first node P and the potential of the output terminal OUT of the shift register are not affected.

Optionally, the working phase of the shift register 100 includes a first pull-down phase and a second pull-down phase; the first pull-down stage is executed before the input stage, the pull-down module 50 executes the first pull-down operation, and pulls down the potential of the output end OUT of the shift register; the second pull-down stage is performed after the output stage, and the pull-down module 50 performs the second pull-down operation to pull down the potential of the output terminal OUT of the shift register.

Specifically, referring to fig. 2, in the first pull-down phase, under the control of the enable level of the second node Q, the pull-down module 50 is turned on, transmits the third voltage signal of the third voltage signal terminal VGL to the first node P and the output terminal OUT of the shift register, and pulls down the potential of the first node P and the potential of the output terminal OUT of the shift register.

In the input stage, the input module 10 is turned on under the control of the enable level of the second shift register signal terminal Gn-1, and transmits the first voltage signal of the first voltage signal terminal FW to the first node P to charge the first node P. At this time, the voltage dividing module 20 can adjust the potential of the second node Q to be in a non-enable level state, and the pull-down module 50 is turned off, so that the third voltage signal of the third voltage signal terminal VGL is not transmitted to the first node P and the output terminal OUT of the shift register.

In the output stage, since the coupling capacitor C stores the potential of the first node P, the potential of the first node P maintains the state of the enable level, the output module 40 is turned on under the control of the potential of the first node P, outputs the first clock signal provided by the first clock signal terminal CLK to the output terminal OUT of the shift register, and provides the scan signal to the corresponding gate line. At this time, the voltage dividing module 20 can adjust the potential of the second node Q to be in a non-enable level state, and the pull-down module 50 is turned off, so that the third voltage signal of the third voltage signal terminal VGL is not transmitted to the first node P and the output terminal OUT of the shift register.

In the second pull-down stage, under the control of the enable level of the second node Q, the pull-down module 50 is turned on, transmits the third voltage signal of the third voltage signal terminal VGL to the first node P and the output terminal OUT of the shift register, and pulls down the potential of the first node P and the potential of the output terminal OUT of the shift register.

And ending the working process of one period of the shift register till the potential of the signal end Gn-1 of the second shift register is in the enabling level state next time, and starting the working process of the next period.

Optionally, the shutdown phase and the second pull-down phase are sequentially executed; or the turn-off phase and the second pull-down phase are sequentially executed, and at least part of time periods of the turn-off phase and the second pull-down phase are overlapped. Thus, the turn-off module 30 and the pull-down module 50 may pull down the potential of the first node P sequentially or simultaneously, so as to ensure that the potential of the first node P may be pulled down to the third voltage signal of the third voltage signal terminal VGL. When at least partial time periods of the turn-off stage and the second pull-down stage are overlapped, the gate scanning time of the shift register can be reduced, the scanning frequency of the display device is improved, and high resolution is achieved.

Fig. 3 is a circuit schematic diagram of a shift register according to an embodiment of the present invention, referring to fig. 3, alternatively, the input module 10 includes a first transistor T1; the first transistor T1 is connected between the first voltage signal terminal FW and the first node P, and the control terminal of the first transistor T1 is connected to the second shift register signal terminal Gn-1. In the input phase, the potential of the second shift register signal terminal Gn-1 is at the enable level, the first transistor T1 is turned on, and the first voltage signal of the first voltage signal terminal FW is transmitted to the first node P to charge the first node P.

Referring to fig. 3, optionally, the output module 40 includes a second transistor T2; the second transistor T2 is connected between the first clock signal terminal CLK and the output terminal OUT of the shift register, and the control terminal of the second transistor T2 is connected to the first node P. In the output phase, the potential of the first node P is at the enable level, the second transistor T2 is turned on, the first clock signal provided by the first clock signal terminal CLK is transmitted to the output terminal OUT of the shift register, and the scan signal is provided to the corresponding gate line.

Referring to fig. 2, optionally, the voltage dividing module 20 includes a first voltage dividing unit 21 and a second voltage dividing unit 22; the first voltage division unit 21 is connected between the second voltage signal terminal VGH and the second node Q, and the first control terminal of the first voltage division unit 21 is connected to the first shift register signal terminal Gn + 1; the second voltage dividing unit 22 is connected between the third voltage signal terminal VGL and the second node Q, a first control terminal of the second voltage dividing unit 22 is connected to the second shift register signal terminal Gn-1, and a second control terminal of the second voltage dividing unit 22 is connected to the first node P; the first voltage division unit 21 is configured to output a second voltage signal provided by the second voltage signal terminal VGH to the second node Q when being turned on; the second voltage dividing unit 22 is configured to output a third voltage signal provided by the third voltage signal terminal VGL to the second node Q when being turned on.

Wherein, the first control terminal of the first voltage dividing unit 21 is the first control terminal of the voltage dividing module 20, and the first control terminal of the first voltage dividing unit 21 is connected to the first shift register signal terminal Gn + 1; the first control end of the second voltage dividing unit 22 is the second control end of the voltage dividing module 20, and the first control end of the second voltage dividing unit 22 is connected to the second shift register signal end Gn-1; the second control end of the second voltage dividing unit 22 is a third control end of the voltage dividing module 20, and the second control end of the second voltage dividing unit 22 is connected to the first node P and is respectively used for controlling the on-off states of the first voltage dividing unit 21 and the second voltage dividing unit 22.

The first voltage division unit 21 is configured to output a second voltage signal provided by the second voltage signal terminal VGH to the second node Q when being turned on; the second voltage dividing unit 22 is configured to output a third voltage signal provided by the third voltage signal terminal VGL to the second node Q when being turned on. Specifically, when the first voltage dividing unit 21 is turned on and the second voltage dividing unit 22 is turned off, the second voltage signal of the second voltage signal terminal VGH is output to the second node Q, and the potential of the second node Q is pulled up; when the second voltage division unit 22 is turned on, the third voltage signal of the third voltage signal terminal VGL is output to the second node Q, and the potential of the second node Q is pulled down.

Referring to fig. 3, optionally, the first voltage division unit 21 includes a third transistor T3 and a fourth transistor T4, the third transistor T3 and the fourth transistor T4 are both connected between the second voltage signal terminal VGH and the second node Q, a control terminal of the third transistor T3 is connected to the first shift register signal terminal Gn +1, and a control terminal of the fourth transistor T4 is connected to the second voltage signal terminal VGH; the second voltage division unit 22 includes a fifth transistor T5 and a sixth transistor T6, the fifth transistor T5 and the sixth transistor T6 are both connected between the third voltage signal terminal VGL and the second node Q, a control terminal of the fifth transistor T5 is connected to the second shift register signal terminal Gn-1, and a control terminal of the sixth transistor T6 is connected to the first node P. Specifically, when the third transistor T3 and/or the fourth transistor T4 are/is turned on, the first voltage dividing unit 21 is turned on, and when both the third transistor T3 and the fourth transistor T4 are turned off, the first voltage dividing unit 21 is turned off; when the fifth transistor T5 and/or the sixth transistor T6 are turned on, the second voltage division unit 22 is turned on; when both the fifth transistor T5 and the sixth transistor T6 are turned off, the second voltage dividing unit 22 is turned off.

Referring to fig. 3, optionally, the pull-down module 50 includes a first pull-down unit 51 and a second pull-down unit 52; the first pull-down unit 51 is connected between the first node P and the third voltage signal terminal VGL, and the control terminal of the first pull-down unit 51 is connected to the second node Q; the second pull-down unit 52 is connected between the output end OUT of the shift register and the third voltage signal end VGL, and the control end of the second pull-down unit 52 is connected to the second node Q; the first pull-down unit 51 and the second pull-down unit 52 are turned on simultaneously or turned off simultaneously, and when turned on, pull down the potential of the first node P and the potential of the output terminal OUT of the shift register to the third voltage signal provided by the third voltage signal terminal VGL.

Therefore, when the potential of the second node Q is at the enable level, the first pull-down unit 51 and the second pull-down unit 52 are simultaneously turned on to pull down the potential of the first node P and the potential of the output terminal OUT of the shift register to the third voltage signal provided by the third voltage signal terminal VGL; when the potential of the second node Q is in the disable state, the first pull-down unit 51 and the second pull-down unit 52 are turned off at the same time, and the third voltage signal of the third voltage signal terminal VGL is not transmitted to the first node P and the output terminal OUT of the shift register.

Referring to fig. 3, optionally, the first pull-down unit 51 includes a seventh transistor T7, and the second pull-down unit 52 includes an eighth transistor T8. A control terminal of the seventh transistor T7 and a control terminal of the eighth transistor T8 are electrically connected to the second node Q, the seventh transistor T7 is connected between the first node P and the third voltage signal terminal VGL, and the eighth transistor T8 is connected between the output terminal OUT of the shift register and the third voltage signal terminal VGL.

Referring to fig. 2, optionally, the control terminal of the shutdown module 30 is connected to the first shift register signal terminal Gn + 1. The first shift register signal terminal Gn +1 receives the output signal of the output terminal of the next stage of shift register, so that the control terminal of the shutdown module 30 can be connected to the first shift register signal terminal Gn +1, so as to pull down the potential of the first node P in the shift register of the present stage to the third voltage signal provided by the third voltage signal terminal VGL while the next stage of shift register outputs the scan signal. Referring to fig. 3, optionally, the turn-off module 30 includes a ninth transistor T9, the ninth transistor T9 is connected between the first node P and the fourth voltage signal terminal BW, and a control terminal of the ninth transistor T9 is connected to the first shift register signal terminal Gn + 1.

For example, the transistors in the shift register may be NMOS transistors, and in this case, the enable level of the output signal of each signal terminal may be selected to be high, and the disable level may be selected to be low.

Taking the transistors in the shift register as NMOS transistors as an example, fig. 4 is a driving timing diagram of the shift register according to an embodiment of the present invention, specifically a driving timing diagram during forward scanning. Referring to fig. 4, the operation process of the shift register includes a first pull-down stage S1, an input stage S2, an output stage S3, and a second pull-down stage S4, the turn-off stage may coincide with the second pull-down stage S4, for example, during a forward scan, the first voltage signal terminal FW and the second voltage signal terminal VGH provide a high level signal greater than 0V, and the third voltage signal terminal VGL and the fourth voltage signal terminal BW provide a low level signal less than or equal to 0V.

Fig. 5 is a schematic diagram of the shift register according to the embodiment of the invention in the first pull-down stage, and referring to fig. 4 and 5, in the first pull-down stage S1, the second voltage signal of the second voltage signal terminal VGH is at a high level, and the fourth transistor T4 is turned on; the initial potential of the first node P is low, so the sixth transistor T6 is turned off, meanwhile, since the first shift register signal of the first shift register signal terminal Gn +1 is at a low level and the second shift register signal of the second shift register signal terminal Gn-1 is at a low level, both the third transistor T3 and the fifth transistor T5 are turned off, and the second voltage signal of the second voltage signal terminal VGH is transmitted to the second node Q through the fourth transistor T4, so that the potential of the second node Q is pulled up. Further, as the potential of the second node Q rises, the seventh transistor T7 and the eighth transistor T8 are turned on, and the potential of the first node P and the potential of the output terminal OUT of the shift register are pulled down to the third voltage signal provided by the third voltage signal terminal VGL.

Fig. 6 is a schematic diagram of the shift register provided by the embodiment of the invention in the input phase, and referring to fig. 4 and 6, in the input phase S2, the input module (T1), the second voltage dividing unit (T5 and T6) and the fourth transistor T4 are all turned on, the first voltage signal (FW) is written into the first node P, and the third voltage signal (VGL) is written into the second node Q. Specifically, in the input stage S2, the second shift register signal at the second shift register signal terminal Gn-1 is at a high level, so that the first transistor T1 and the fifth transistor T5 are turned on, and the first voltage signal provided by the first voltage signal terminal FW is transmitted to the first node P through the first transistor T1 to charge the first node P and pull up the potential of the first node P. Meanwhile, the potential of the first node P is increased, so that the sixth transistor T6 is turned on, and the third voltage signal of the third voltage signal terminal VGL is transmitted to the second node Q through the fifth transistor T5 and the sixth transistor T6, so that the potential of the second node Q can be quickly lowered, the seventh transistor T7 and the eighth transistor T8 are quickly turned off, and the situation that the potential of the first node P and the potential of the output end OUT of the shift register are influenced because the seventh transistor T7 and the eighth transistor T8 cannot be timely turned off due to untimely discharge of the second node Q is avoided.

Fig. 7 is a schematic diagram of the shift register in the output phase according to the embodiment of the invention, and with reference to fig. 4 and 7, in the output phase S3, the output module (T2), the fourth transistor T4 and the sixth transistor T6 are all turned on, and the first clock signal provided by the first clock signal terminal CLK is output to the output terminal OUT of the shift register. Specifically, in the output stage S3, the potential of the first node P is kept high due to the coupling capacitor C, so that the second transistor T2 is turned on, and the first clock signal of the first clock signal terminal CLK is transmitted to the output terminal OUT of the shift register through the second transistor T2. Meanwhile, since the first node P is at a high level, the sixth transistor T6 is turned on, the third voltage signal at the third voltage signal terminal VGL is transmitted to the second node Q through the sixth transistor T6, the potential of the second node Q is pulled down, the seventh transistor T7 and the eighth transistor T8 are turned off, and the third voltage signal at the third voltage signal terminal VGL is not transmitted to the first node P and the output terminal OUT of the shift register.

Fig. 8 is a schematic diagram of the shift register in the second pull-down stage according to the embodiment of the invention, and with reference to fig. 4 and 8, in the second pull-down stage S4, the first shift register signal of the first shift register signal terminal Gn +1 is at a high level, so that the third transistor T3 is turned on, and at the same time, the fourth transistor T4 is turned on, and further, since the coupling capacitor C of the output stage S3 is discharged, so that the potential of the first node P is lowered, so that the sixth transistor T6 is turned off, and at the same time, since the second shift register signal of the second shift register signal terminal Gn-1 is at a low level, so that the fifth transistor T5 is turned off, so that the second voltage signal of the second voltage signal terminal VGH can be transmitted to the second node Q through the third transistor T3 and the fourth transistor T4, so that the potential of the second node Q can be quickly raised, and the seventh transistor T7 and the eighth transistor T8 can be quickly turned on, the third voltage signal of the third voltage signal terminal VGL is transmitted to the first node P and the output terminal OUT of the shift register, so that the potential of the first node P and the potential of the output terminal OUT of the shift register are pulled down in time, and the situation that the seventh transistor T7 and the eighth transistor T8 cannot be turned on in time due to untimely charging of the second node Q is avoided, and further, the output signal of the shift register is abnormal, and normal display is influenced. In addition, since the control terminal of the ninth transistor T9 is connected to the first shift register signal terminal Gn +1, the ninth transistor T9 is turned on, and the fourth voltage signal of the fourth voltage signal terminal BW can be transmitted to the first node P through the ninth transistor T9, which plays a role of pulling up the potential of the first node P.

Fig. 9 is a circuit schematic diagram of another shift register according to an embodiment of the present invention, and referring to fig. 9, optionally, the shift register 100 further includes: the reset module 60, the reset module 60 is connected between the first node P and the third voltage signal terminal VGL, and is configured to be turned on in a reset phase, so that the potential of the first node P is reset to the third voltage signal provided by the third voltage signal terminal VGL.

Static electricity may be accumulated on the first node P, and the static electricity needs to be discharged before the input stage S2, so as to prevent the residual static electricity on the first node P from affecting the output signal of the shift register and affecting the display effect. Since the duration of the first pull-down phase S1 is usually short, when the input phase S2 starts, the potential of the first node P may not drop to the third voltage signal provided by the third voltage signal terminal VGL, in this embodiment, the reset module 60 is configured to turn on the reset module 60 in the reset phase, so as to assist the seventh transistor T7 in the pull-down module to quickly reset the potential of the first node P to the third voltage signal provided by the third voltage signal terminal VGL, thereby eliminating static electricity on the first node P, ensuring that the output signal of the shift register is normal, and further ensuring the display effect.

Optionally, the reset phase may be located after the first pull-down phase S1, before the input phase S2; alternatively, the reset phase may overlap with the first pull-down phase S1; alternatively, the reset phase may partially overlap the first pull-down phase S1, and the start time of the first pull-down phase S1 is before the reset phase.

For example, referring to fig. 9, the reset module 60 may include a tenth transistor T10, the tenth transistor T10 is connected between the first node P and the third voltage signal terminal VGL, a gate of the tenth transistor T10 is connected to the reset signal terminal RES, when a potential of the reset signal terminal RES is in an enable level state, the tenth transistor T10 is turned on, and the potential of the first node P is reset to the third voltage signal provided by the third voltage signal terminal VGL.

Similarly, referring to fig. 9, optionally, the shift register 100 further includes: and the initialization module 70, the initialization module 70 is connected between the output end OUT of the shift register and the third voltage signal end VGL, and is configured to be turned on in an initialization stage, so that the potential of the output end OUT of the shift register is initialized to the third voltage signal.

In this embodiment, the initialization module 70 is set to be turned on in the initialization stage, so as to assist the eighth transistor T8 in the pull-down module, and initialize the output end OUT of the shift register to the third voltage signal (VGL) quickly before the input stage S2, thereby avoiding the influence on the output signal caused by the residual static electricity at the output end OUT of the shift register, and ensuring the normal display effect.

Optionally, the initialization phase may be located after the first pull-down phase S1, before the input phase S2; alternatively, the initialization phase may overlap with the first pull-down phase S1; alternatively, the initialization phase may partially overlap the first pull-down phase S1, and the start time of the first pull-down phase S1 is before the initialization phase.

For example, referring to fig. 9, the initialization block 70 may include an eleventh transistor T11, the eleventh transistor T11 is connected between the output terminal OUT of the shift register and the third voltage signal terminal VGL, a gate of the eleventh transistor T11 is connected to the initialization signal terminal REF, when a potential of the initialization signal terminal REF is in an enable level state, the eleventh transistor T11 is turned on, and the potential of the output terminal OUT of the shift register is initialized to the third voltage signal provided by the third voltage signal terminal VGL.

In addition, referring to fig. 9, by providing the reset module 60 and the initialization module 70, when the second node Q fails (e.g., the potential is low) and the seventh transistor T7 and the eighth transistor T8 cannot be normally turned on, the reset module 60 may pull down the potential of the first node P to the third voltage signal provided by the third voltage signal terminal VGL, and the initialization module 70 may pull down the potential of the output terminal OUT of the shift register to the third voltage signal provided by the third voltage signal terminal VGL, instead of the pull-down module 50, so as to implement the functions of the shift register in the first pull-down phase S1 and the second pull-down phase S4, and ensure that the shift register can normally operate.

Fig. 10 is a schematic structural diagram of another shift register according to an embodiment of the present invention, and the difference between fig. 10 and fig. 2 is only that the voltage dividing module 20 is connected in a different manner, and the operation principle thereof is similar to that of fig. 2, so that the stability of the driving circuit can be improved, and two scanning modes of forward scanning and reverse scanning can be performed.

In fig. 2, the voltage divider module 20 has a first terminal and a second terminal besides the control terminal, and the first terminal and the second terminal are respectively connected to the second voltage signal terminal VGH and the third voltage signal terminal VGL. In this embodiment, referring to fig. 10, optionally, the voltage dividing module 20 further has a third terminal and a fourth terminal, the third terminal of the voltage dividing module 20 is connected to the first voltage signal terminal FW, and the fourth terminal is connected to the fourth voltage signal terminal BW.

With continued reference to fig. 2, optionally, the voltage dividing module 20 includes a first voltage dividing unit 21 and a second voltage dividing unit 22; the first terminal of the first voltage dividing unit 21 is connected to the first voltage signal terminal FW, the second terminal is connected to the second voltage signal terminal VGH, and the third terminal is connected to the second node Q, and the first control terminal of the first voltage dividing unit 21 is connected to the first shift register signal terminal Gn + 1; the first terminal of the second voltage dividing unit 22 is connected to the third voltage signal terminal VGL, the second terminal is connected to the fourth voltage signal terminal BW, and the third terminal is connected to the second node Q, and the first control terminal of the second voltage dividing unit 22 is connected to the second shift register signal terminal Gn-1, and the second control terminal of the second voltage dividing unit 22 is connected to the first node P; the first voltage dividing unit 21 is configured to output a first voltage signal provided by the first voltage signal terminal FW or a second voltage signal provided by the second voltage signal terminal VGH to the second node Q when the first voltage dividing unit is turned on; the second voltage dividing unit 22 is configured to output a third voltage signal provided by the third voltage signal terminal VGL or a fourth voltage signal provided by the fourth voltage signal terminal BW to the second node Q when being turned on.

Correspondingly, fig. 11 is a circuit schematic diagram of another shift register according to an embodiment of the invention, and referring to fig. 11, optionally, the first voltage dividing unit 21 includes a third transistor T3 and a fourth transistor T4, the third transistor T3 is connected between the first voltage signal terminal FW and the second node Q, the fourth transistor T4 is connected between the second voltage signal terminal VGH and the second node Q, a control terminal of the third transistor T3 is connected to the first shift register signal terminal Gn +1, and a control terminal of the fourth transistor T4 is connected to the second voltage signal terminal VGH; the second voltage division unit 22 includes a fifth transistor T5 and a sixth transistor T6, the fifth transistor T5 is connected between the fourth voltage signal terminal BW and the second node Q, the sixth transistor T6 is connected between the third voltage signal terminal VGL and the second node Q, a control terminal of the fifth transistor T5 is connected to the second shift register signal terminal Gn-1, and a control terminal of the sixth transistor T6 is connected to the first node P.

In summary, the above embodiments describe the circuit structure of the shift register in detail, and the following description describes the film structure of the shift register.

Fig. 12 is a schematic view of a partial structure of a shift register according to an embodiment of the present invention, referring to fig. 12, optionally, the driving circuit further includes a gate metal layer, a source/drain metal layer, and a first metal layer, the gate metal layer, the source/drain metal layer, and the first metal layer are disposed at different layers, and the first metal layer includes a first bridge structure 101; the gate 201 and the first node P of the second transistor T2 are connected to the same first bridge-spanning structure 101 through a first bridge wire-changing hole, and the gate metal layer and the first node P are disposed in different layers.

Referring to fig. 12, a film layer where the gate 201 of the second transistor T2 is located is a gate metal layer, a film layer where the source 202 and the drain 203 of the second transistor T2 are located is a source/drain metal layer, and a film layer where the first bridge structure 101 is located is a first metal layer.

As shown in fig. 9 or 11, the first node P is simultaneously connected to the gate of the second transistor T2, the gate of the sixth transistor T6, the source of the seventh transistor T7, the source of the ninth transistor T9 and the source of the tenth transistor T10, and the gate and the source of the transistor are located in different metal layers, so that it is necessary to connect metal structures located in different layers, i.e., the gates of the second transistor T2 and the sixth transistor T6 and the sources of the seventh transistor T7, the ninth transistor T9 and the tenth transistor T10, to the first node P using a bridge structure.

As shown in fig. 12, optionally, the first node P is on the same layer as the source/drain metal layer. In this way, the metal layer where the first node P is located is at the same layer as the source and drain electrodes of the seventh transistor T7, the ninth transistor T9 and the tenth transistor T10 and at a different layer from the gates of the second transistor T2 and the sixth transistor T6, and the gate 201 of the second transistor T2 can be connected to the first node P through the first bridge structure 101. The metal structures on the same layer can be connected on the film layer.

The above structure is merely an example, and is not limited, in other embodiments, the metal layer where the first node P is located may be the same as the gate metal layer, and the first node P and the source of the seventh transistor T7 are connected by a bridge structure, which may be set by a person skilled in the art according to practical situations.

Similarly, fig. 13 is a partial structural schematic diagram of another shift register provided in the embodiment of the present invention, and referring to fig. 9 (or fig. 11) and fig. 13, optionally, the first metal layer includes a second bridge structure 102; the gate 401 of the fourth transistor T4 and the source 402 of the fourth transistor T4 are connected to the same second bridge structure 102 by a second bridge wire-change hole.

Fig. 14 is a partial structural schematic diagram of another shift register provided in an embodiment of the present invention, and referring to fig. 9 (or fig. 11) and fig. 14, optionally, the first metal layer includes a third bridge structure 103; the gate 701 and the second node Q of the seventh transistor T7 are connected to the same third bridging structure 103 through a third bridging wire-changing hole, and the gate metal layer and the second node Q are disposed in different layers. Optionally, the second node Q and the source-drain metal layer are on the same layer. As shown in fig. 14, the second node Q is disposed at the same level as the source 702 and the drain 703 of the seventh transistor T7.

The above structure is merely an example, and is not limited to the above, in other embodiments, the metal layer where the second node Q is located and the gate metal layer are the same, and the drain of the third transistor T3 is connected to the second node Q through a bridge structure, which can be set by a person skilled in the art according to practical situations.

For a detailed design principle of the structure shown in fig. 13 and 14, please refer to the description related to fig. 12, which is not repeated herein. Illustratively, the material of the bridge structure may be Indium Tin Oxide (ITO).

Because the metal layer that the bridge structure is located is closer to the upper surface of display panel, consequently, under high temperature and high humidity environment, if moisture in the environment gets into display panel inside, cause bridge structure corrosion open circuit easily, lead to the screen to show unusually. In fig. 1, 9, and 11, two circular dashed boxes and a dashed line therebetween represent a bridge-crossing structure, and as can be seen from comparing fig. 1, 9, and 11, the shift register provided in this embodiment can not only improve the stability of the driving circuit, but also reduce the number of bridge-crossing structures, and reduce the probability of line corrosion.

In summary, the above embodiments briefly describe the film structure of the shift register, and the following describes the connection relationship between the shift registers in the driving circuit.

Fig. 15 is a schematic structural diagram of a driving circuit according to an embodiment of the present invention, referring to fig. 15, in the driving circuit 200, the first shift register signal terminal Gn +1 is connected to the output terminal OUT of the next shift register, and the second shift register signal terminal Gn-1 is connected to the output terminal OUT of the previous shift register, so that the cascade connection of the multiple shift registers 100 can be implemented, and fig. 15 only exemplarily shows a cascade connection structure of four shift registers 100.

As described above, the driving circuit 200 provided in the present embodiment can realize both the forward direction scanning and the reverse direction scanning modes. Fig. 16 is a schematic diagram of a driving timing sequence of a driving circuit according to an embodiment of the present invention, specifically, a driving timing sequence of a forward scanning mode. Referring to fig. 15 and 16, during forward scanning, the first voltage signal terminal FW and the second voltage signal terminal VGH provide a high level signal greater than 0V, the third voltage signal terminal VGL and the fourth voltage signal terminal BW provide a low level signal less than or equal to 0V, and the forward input signal terminal STVF is connected to the second shift register signal terminal Gn-1 of the first stage shift register ASG1 for triggering the first stage shift register ASG1 to enter the input stage S2, and the operation process of the shift register is not described herein again. When the output terminal OUT1 of the first stage shift register ASG1 outputs a scan signal to the corresponding gate line, the output signal is transmitted to the second shift register signal terminal Gn-1 of the second stage shift register ASG2, so that the second stage shift register ASG2 enters the input stage S2, and then, when the output terminal OUT2 of the second stage shift register ASG2 outputs a scan signal to the corresponding gate line, the output signal thereof is simultaneously transmitted to the first shift register signal terminal Gn +1 of the first stage shift register ASG1 and the second shift register signal terminal Gn-1 of the third stage shift register ASG3, so that the first shift register ASG1 enters the second pull-down stage S4, and the third stage shift register ASG3 enters the input stage S2 … …. By analogy, the multistage shift register 100 in the driving circuit 200 can sequentially output scanning signals to the corresponding gate lines along the direction from the first row of pixels to the last row of pixels, so as to realize forward progressive scanning of the pixel array.

Referring to fig. 15, when performing the reverse scan, the first voltage signal terminal FW and the third voltage signal terminal VGL may be controlled to provide a low level signal less than or equal to 0V, the fourth voltage signal terminal BW and the second voltage signal terminal VGH provide a high level signal greater than 0V, the reverse input signal terminal STVB is connected to the first shift register signal terminal Gn +1 of the shift register (for example, ASG4 in fig. 15) corresponding to the last row of pixels, and is used to trigger the stage of the shift register to enter the input stage S2, so that the multi-stage shift register 100 in the driving circuit 200 sequentially outputs the scan signals to the corresponding gate lines along the direction from the last row of pixels to the first row of pixels, thereby implementing the reverse progressive scan of the pixel array.

Based on the same inventive concept, an embodiment of the present invention further provides a display device, and fig. 17 is a schematic structural diagram of the display device provided in the embodiment of the present invention, where the display device 300 includes the driving circuits provided in any of the above embodiments, and the driving circuits may be located in the non-display areas on the left and right sides of the display area AA. The display device has the same beneficial effects as the driving circuit, and the same points can refer to the description of the display panel embodiment, and are not repeated herein. The display device 01 provided in the embodiment of the present invention may be a mobile phone shown in fig. 12, and may also be any electronic product with a display function, including but not limited to the following categories: the touch screen display system comprises a television, a notebook computer, a desktop display, a tablet computer, a digital camera, an intelligent bracelet, intelligent glasses, a vehicle-mounted display, medical equipment, industrial control equipment, a touch interaction terminal and the like, and the embodiment of the invention is not particularly limited in this respect.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.