1. A shift register is characterized by comprising a first control output module and a second control output module, wherein the first control output module comprises a first node and a first output end, and the first node is used for controlling the first output end to output a signal with a potential opposite to that of the first node; the second control output module comprises a second output end, and the second control output module is used for enabling the second output end to output a signal with the opposite potential to that of the first output end under the control of the first node and the first output end.

2. The shift register of claim 1, wherein the first control output module further comprises a second node, a first sub-module and a second sub-module, the first sub-module being electrically connected to the first node, the second node, a first power supply terminal and the first output terminal, the second sub-module being electrically connected to the second node, a second power supply terminal and the first output terminal; the first submodule is used for conducting the first power supply end and the first output end under the control of the first node, and the second submodule is used for conducting the second power supply end and the first output end under the control of the second node;

the second control output module further comprises a third submodule and a fourth submodule, the third submodule is electrically connected with the first node, the second power supply end, the first clock signal end and the second output end, and the fourth submodule is electrically connected with the first output end, the first power supply end and the second output end; the third sub-module is configured to conduct the second power source terminal and the second output terminal under the control of the second power source terminal, and the fourth sub-module is configured to conduct the first power source terminal and the second output terminal under the control of the first output terminal.

3. The shift register of claim 2, wherein the third submodule comprises: a first transistor, a second transistor, a third transistor, and a first capacitor;

a gate of the first transistor is electrically connected to the second power supply terminal, a first pole is electrically connected to the first node, and a second pole is electrically connected to a gate of the second transistor;

a first electrode of the second transistor is electrically connected with the first clock signal end, a second electrode of the second transistor is electrically connected with a first end of the first capacitor, and a second end of the first capacitor is connected between the second electrode of the first transistor and a grid electrode of the second transistor;

and the grid electrode of the third transistor is connected between the second pole of the first transistor and the grid electrode of the second transistor, the first pole is electrically connected with the second power supply end, and the second pole is electrically connected with the second output end.

4. The shift register of claim 3, wherein the fourth submodule comprises: a fourth transistor and a fifth transistor;

a gate of the fourth transistor is electrically connected to the first output terminal, a first electrode of the fourth transistor is electrically connected to the first power source terminal, and a second electrode of the fourth transistor is electrically connected to a gate of the third transistor;

and the grid electrode of the fifth transistor is electrically connected with the first output end, the first pole of the fifth transistor is electrically connected with the first power supply end, and the second pole of the fifth transistor is electrically connected with the second output end.

5. The shift register of claim 2, wherein the first submodule comprises: a sixth transistor, a seventh transistor, and a second capacitor;

a gate of the sixth transistor is electrically connected to the second node N1, a first pole is electrically connected to the first power supply terminal, and a second pole is electrically connected to the first node;

a gate of the seventh transistor is electrically connected to the first node, a first electrode of the seventh transistor is electrically connected to the first power supply terminal, and a second electrode of the seventh transistor is electrically connected to the first output terminal;

the first end of the second capacitor is electrically connected with the first node, and the second end of the second capacitor is electrically connected with the first power supply end.

6. The shift register of claim 5, wherein the second submodule comprises: an eighth transistor and a third capacitor;

a gate of the eighth transistor is electrically connected to the second node, a first electrode of the eighth transistor is electrically connected to the second power supply terminal, and a second electrode of the eighth transistor is electrically connected to the first output terminal;

and the first end of the third capacitor is electrically connected with the second clock signal end, and the second end of the third capacitor is electrically connected with the second node.

7. The shift register of claim 2, wherein the first control output module further comprises an input module and a node control module;

the input module is configured to provide a signal of a trigger signal terminal to a second node under the control of a first clock signal terminal;

the node control module is configured to provide a signal of the first clock signal terminal to a third node under the control of the trigger signal terminal, provide a signal of the first power terminal to the second node under the control of the third node and the second clock signal terminal, and provide a signal of the second clock signal terminal to the first node under the control of the third node and the second clock signal terminal.

8. The shift register of claim 7, wherein the input module comprises: a ninth transistor;

the gate of the ninth transistor is electrically connected to the first clock signal terminal, the first electrode is electrically connected to the trigger signal terminal, and the second electrode is electrically connected to the second node.

9. The shift register of claim 7, wherein the node control module comprises: a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a fourth capacitor;

a gate of the tenth transistor is electrically connected to the second node, a first electrode of the tenth transistor is electrically connected to the first clock signal terminal, and a second electrode of the tenth transistor is electrically connected to the third node;

a grid electrode of the eleventh transistor is electrically connected with the first clock signal end, a first electrode of the eleventh transistor is electrically connected with the second power supply end, and a second electrode of the eleventh transistor is electrically connected with the third node;

a gate of the twelfth transistor is electrically connected to the third node, a first electrode of the twelfth transistor is electrically connected to the first power supply terminal, and a second electrode of the twelfth transistor is electrically connected to the first electrode of the thirteenth transistor;

a gate of the thirteenth transistor is electrically connected to the second clock signal terminal, and a second electrode of the thirteenth transistor is electrically connected to the second node;

a gate of the fourteenth transistor is electrically connected to the third node, a first electrode of the fourteenth transistor is electrically connected to the second clock signal terminal, and a second electrode of the fourteenth transistor is electrically connected to the first electrode of the fifteenth transistor;

a gate of the fifteenth transistor is electrically connected to the second clock signal terminal, and a second pole is electrically connected to the first node;

a first end of the fourth capacitor is electrically connected to the third node, and a second end of the fourth capacitor is connected between the second pole of the fourteenth transistor and the first pole of the fifteenth transistor.

10. A display panel comprising a display region and a non-display region, the display region comprising a plurality of pixel circuits and a light emitting device electrically connected to the pixel circuits, the pixel circuits comprising an anode reset transistor electrically connected to an anode of the light emitting device; the non-display region comprises a gate driving circuit, wherein the gate driving circuit comprises a plurality of cascaded shift registers according to any one of claims 1 to 9; wherein the content of the first and second substances,

the signal input end of the first-stage shift register is electrically connected with the trigger signal end;

except the first stage of shift register, the signal input ends of the other shift registers at each stage are respectively and electrically connected with the first output end of the shift register at the previous stage;

and the second output end of each stage of the shift register is electrically connected with the grid electrode of the corresponding anode reset transistor.

11. A display device characterized by comprising the display panel according to claim 10.

Background

Among Gate driver On Array (GOA) circuits, there is a class of GOA circuits for controlling the light emitting time of a pixel, which is called an EMGOA circuit, and is usually implemented by using a plurality of cascaded shift registers.

Disclosure of Invention

Embodiments of the present invention provide a shift register, a display panel, and a display device, so as to solve the problem in the prior art that a pixel which should not emit light generates weak light.

The shift register provided by the embodiment of the disclosure comprises a first control output module and a second control output module, wherein the first control output module comprises a first node and a first output end, and the first node is used for controlling the first output end to output a signal with a potential opposite to that of the first node; the second control output module comprises a second output end, and the second control output module is used for enabling the second output end to output a signal with the opposite potential to that of the first output end under the control of the first node and the first output end.

Optionally, in the shift register provided in the embodiment of the present invention, the first control output module further includes a second node, a first sub-module and a second sub-module, the first sub-module is electrically connected to the first node, the second node, a first power source terminal and the first output terminal, and the second sub-module is electrically connected to the second node, a second power source terminal and the first output terminal; the first submodule is used for conducting the first power supply end and the first output end under the control of the first node, and the second submodule is used for conducting the second power supply end and the first output end under the control of the second node;

the second control output module further comprises a third submodule and a fourth submodule, the third submodule is electrically connected with the first node, the second power supply end, the first clock signal end and the second output end, and the fourth submodule is electrically connected with the first output end, the first power supply end and the second output end; the third sub-module is configured to conduct the second power source terminal and the second output terminal under the control of the second power source terminal, and the fourth sub-module is configured to conduct the first power source terminal and the second output terminal under the control of the first output terminal.

Optionally, in the shift register provided in the embodiment of the present invention, the third sub-module includes: a first transistor, a second transistor, a third transistor, and a first capacitor;

a gate of the first transistor is electrically connected to the second power supply terminal, a first pole is electrically connected to the first node, and a second pole is electrically connected to a gate of the second transistor;

a first electrode of the second transistor is electrically connected with the first clock signal end, a second electrode of the second transistor is electrically connected with a first end of the first capacitor, and a second end of the first capacitor is connected between the second electrode of the first transistor and a grid electrode of the second transistor;

and the grid electrode of the third transistor is connected between the second pole of the first transistor and the grid electrode of the second transistor, the first pole is electrically connected with the second power supply end, and the second pole is electrically connected with the second output end.

Optionally, in the shift register provided in the embodiment of the present invention, the fourth sub-module includes: a fourth transistor and a fifth transistor;

a gate of the fourth transistor is electrically connected to the first output terminal, a first electrode of the fourth transistor is electrically connected to the first power source terminal, and a second electrode of the fourth transistor is electrically connected to a gate of the third transistor;

and the grid electrode of the fifth transistor is electrically connected with the first output end, the first pole of the fifth transistor is electrically connected with the first power supply end, and the second pole of the fifth transistor is electrically connected with the second output end.

Optionally, in the shift register provided in the embodiment of the present invention, the first sub-module includes: a sixth transistor, a seventh transistor, and a second capacitor;

a gate of the sixth transistor is electrically connected to the second node N1, a first pole is electrically connected to the first power supply terminal, and a second pole is electrically connected to the first node;

a gate of the seventh transistor is electrically connected to the first node, a first electrode of the seventh transistor is electrically connected to the first power supply terminal, and a second electrode of the seventh transistor is electrically connected to the first output terminal;

the first end of the second capacitor is electrically connected with the first node, and the second end of the second capacitor is electrically connected with the first power supply end.

Optionally, in the shift register provided in the embodiment of the present invention, the second sub-module includes: an eighth transistor and a third capacitor;

a gate of the eighth transistor is electrically connected to the second node, a first electrode of the eighth transistor is electrically connected to the second power supply terminal, and a second electrode of the eighth transistor is electrically connected to the first output terminal;

and the first end of the third capacitor is electrically connected with the second clock signal end, and the second end of the third capacitor is electrically connected with the second node.

Optionally, in the shift register provided in the embodiment of the present invention, the first control output module further includes an input module and a node control module;

the input module is configured to provide a signal of a trigger signal terminal to a second node under the control of a first clock signal terminal;

the node control module is configured to provide a signal of the first clock signal terminal to a third node under the control of the trigger signal terminal, provide a signal of the first power terminal to the second node under the control of the third node and the second clock signal terminal, and provide a signal of the second clock signal terminal to the first node under the control of the third node and the second clock signal terminal.

Optionally, in the shift register provided in the embodiment of the present invention, the input module includes: a ninth transistor;

the gate of the ninth transistor is electrically connected to the first clock signal terminal, the first electrode is electrically connected to the trigger signal terminal, and the second electrode is electrically connected to the second node.

Optionally, in the shift register provided in the embodiment of the present invention, the node control module includes: a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a fourth capacitor;

a gate of the tenth transistor is electrically connected to the second node, a first electrode of the tenth transistor is electrically connected to the first clock signal terminal, and a second electrode of the tenth transistor is electrically connected to the third node;

a grid electrode of the eleventh transistor is electrically connected with the first clock signal end, a first electrode of the eleventh transistor is electrically connected with the second power supply end, and a second electrode of the eleventh transistor is electrically connected with the third node;

a gate of the twelfth transistor is electrically connected to the third node, a first electrode of the twelfth transistor is electrically connected to the first power supply terminal, and a second electrode of the twelfth transistor is electrically connected to the first electrode of the thirteenth transistor;

a gate of the thirteenth transistor is electrically connected to the second clock signal terminal, and a second electrode of the thirteenth transistor is electrically connected to the second node;

a gate of the fourteenth transistor is electrically connected to the third node, a first electrode of the fourteenth transistor is electrically connected to the second clock signal terminal, and a second electrode of the fourteenth transistor is electrically connected to the first electrode of the fifteenth transistor;

a gate of the fifteenth transistor is electrically connected to the second clock signal terminal, and a second pole is electrically connected to the first node;

a first end of the fourth capacitor is electrically connected to the third node, and a second end of the fourth capacitor is connected between the second pole of the fourteenth transistor and the first pole of the fifteenth transistor.

Accordingly, an embodiment of the present invention further provides a display panel including a display region and a non-display region, the display region including a plurality of pixel circuits and a light emitting device electrically connected to the pixel circuits, the pixel circuits including an anode reset transistor electrically connected to an anode of the light emitting device; the non-display area comprises a gate driving circuit, and the gate driving circuit comprises a plurality of cascaded shift registers; wherein the content of the first and second substances,

the signal input end of the first-stage shift register is electrically connected with the trigger signal end;

except the first stage of shift register, the signal input ends of the other shift registers at each stage are respectively and electrically connected with the first output end of the shift register at the previous stage;

and the second output end of each stage of the shift register is electrically connected with the grid electrode of the corresponding anode reset transistor.

Correspondingly, the embodiment of the invention also provides a display device which comprises the display panel.

The embodiment of the invention has the following beneficial effects:

the shift register comprises a first control output module and a second control output module, wherein the first control output module comprises a first node and a first output end, and the first node is used for controlling the first output end to output a signal with a potential opposite to that of the first node; the second control output module comprises a second output end, and the second control output module is used for enabling the second output end to output a signal with the opposite potential to the first output end under the control of the first node and the first output end. The shift register provided by the invention is provided with two output ends, the electric potentials of signals output by the second output end and the first output end are opposite, the first output end can be electrically connected with a light-emitting control end in the pixel circuit, and the second output end is electrically connected with a grid electrode of an anode reset transistor in the pixel circuit. In the pixel light-emitting stage, only the signal output by the first output end controls the light-emitting control transistor to be conducted so as to realize the light-emitting of the light-emitting device; in other non-light emitting stages, only the signal output by the second output end controls the anode reset transistor to be conducted so as to provide continuous initialization voltage for the anode of the light emitting device, so that extra current is not generated at two ends of the anode and the cathode of the light emitting device, and therefore, weak light emission of pixels which should not emit light can be avoided, and the optical evaluation result of the display panel is improved.

Drawings

Fig. 1 is a schematic structural diagram of a shift register according to an embodiment of the present invention;

fig. 2 is a circuit structure of a pixel circuit according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of another shift register according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a shift register according to an embodiment of the present invention;

FIG. 5 is a timing diagram of the input and output of the shift register shown in FIG. 4;

FIG. 6 is a simulated timing diagram of the shift register shown in FIG. 4;

fig. 7 is a schematic structural diagram of a gate driving circuit in a display panel according to an embodiment of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. And the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of the word "comprising" or "comprises", and the like, in this disclosure is intended to mean that the elements or items listed before that word, include the elements or items listed after that word, and their equivalents, without excluding other elements or items. The terms "connect" or "electrically connect," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "inner", "outer", "upper", "lower", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

It should be noted that the sizes and shapes of the various figures in the drawings are not to scale, but are merely intended to illustrate the present disclosure. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

Compared with the current mainstream Display technology Thin Film transistor Liquid Crystal Display (TFT-LCD), the Organic Light Emitting Display (OLED) has the advantages of wide viewing angle, high brightness, high contrast, low energy consumption, lighter and thinner volume, and the like, and is a focus of the current flat panel Display technology.

OLEDs include both Passive Matrix (PM) and Active Matrix (AM). Compared with passive matrix driving, active matrix driving (AMOLED) has the advantages of large display information amount, low power consumption, long service life of devices, high picture contrast and the like.

In the AMOLED panel industry, a plurality of pixel regions are included, each pixel region includes a pixel circuit and a light emitting device, the pixel circuit drives the light emitting device to emit light, however, some common layers in the light emitting device, such as an electron transport layer, may cause unnecessary current to be generated by other pixels adjacent to the light emitting pixel when the pixel emits light, so that the pixel which should not emit light generates weak light, thereby reducing the optical evaluation result of the panel.

In view of the above, the embodiment of the invention provides a shift register, as shown in fig. 1, including a first control output block 1 and a second control output block 2, where the first control output block 1 includes a first node N1 and a first output terminal OUT1, and the first node N1 is used for controlling the first output terminal OUT1 to output a signal with a potential opposite to that of the first node N1; the second control output module 2 comprises a second output terminal OUT2, and the second control output module 2 is configured to enable the second output terminal OUT2 to output a signal with a potential opposite to that of the first output terminal OUT1 under the control of the first node N1 and the first output terminal OUT 1.

A pixel circuit for driving a light emitting device to emit light is a 7T1C structure, as shown in fig. 2, including a reset transistor M1, a threshold compensation transistor M2, a driving transistor M3, a data writing transistor M4, a first light emitting control transistor M5, a second light emitting control transistor M6, an anode reset transistor M7, and a storage capacitor Cst. The 7T1C pixel circuit drives the light emitting device L to emit light, and the light emitting device L includes a cathode, an electron transport layer, a light emitting layer, a hole transport layer, a hole injection layer and an anode, which are stacked in sequence, for example, the electron transport layer corresponding to all pixel regions is generally a common layer, which may cause unnecessary current to be generated by other pixels adjacent to the light emitting pixel when some pixels emit light, so that the pixels that should not emit light emit weak light, thereby reducing the optical evaluation result of the panel. Therefore, the shift register provided by the embodiment of the present invention has two output terminals (the first output terminal OUT1 and the second output terminal OUT2), and the second output terminal OUT2 is opposite to the potential of the signal output by the first output terminal OUT1, and the first output terminal OUT1 can be electrically connected to the emission control terminal EM in the pixel circuit, and the second output terminal OUT2 is electrically connected to the gate of the anode reset transistor M7 in the pixel circuit. Thus, in the pixel lighting phase, only the signal output by the first output terminal OUT1 controls the lighting control transistor (T5 and T6) to be turned on to realize the lighting of the lighting device L; in the rest non-light emitting period, only the signal output by the second output terminal OUT2 controls the anode reset transistor M7 to be turned on to provide a continuous initialization voltage to the anode of the light emitting device L, so that no extra current is generated across the anode and the cathode of the light emitting device L, and therefore, the weak light emission of pixels which should not emit light can be avoided, and the optical evaluation result of the display panel is improved.

In addition, in the embodiment of the invention, the shift register can output two signals with completely opposite high and low potentials by adding the second output control module (namely, a mode of adding a small number of transistors and capacitors, which is described later) in the original shift register, so that the space is saved to a certain extent on the basis of improving the optical evaluation result of the display panel.

In practical implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 3, the first control output module 1 further includes a second node N2, a first submodule 11 and a second submodule 12, the first submodule 11 is electrically connected to the first node N1, the second node N2, the first power supply terminal VGH and the first output terminal OUT1, and the second submodule 12 is electrically connected to the second node N2, the second power supply terminal VGL and the first output terminal OUT 1; the first submodule 11 is used for conducting the first power supply terminal VGH and the first output terminal OUT1 under the control of a first node N1, and the second submodule 12 is used for conducting the second power supply terminal VGL and the first output terminal OUT1 under the control of a second node N2;

the second control output module 2 further comprises a third submodule 21 and a fourth submodule 22, the third submodule 21 is electrically connected with the first node N1, the second power terminal VGL, the first clock signal terminal CK and the second output terminal OUT2, and the fourth submodule 22 is electrically connected with the first output terminal OUT1, the first power terminal VGH and the second output terminal OUT 2; the third submodule 21 is configured to conduct the second power supply terminal VGL and the second output terminal OUT2 under the control of the second power supply terminal VGL, and the fourth submodule 22 is configured to conduct the first power supply terminal VGH and the second output terminal OUT2 under the control of the first output terminal OUT 1.

In order to better understand the structure and the operation principle of the shift register provided by the embodiment of the present invention, a detailed description is given below with respect to a specific embodiment.

Specifically, the structure shown in fig. 4 is a possible implementation manner of the shift register provided in the embodiment of the present invention.

Specifically, the signal of the first power source terminal VGH is generally a high potential signal, and the signal of the second power source terminal VGL is generally a low potential signal; the signal of the first clock signal terminal CK and the signal of the second clock signal terminal CB are pulse signals having the same period and opposite potentials.

In a specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 4, the third sub-module 21 includes: a first transistor T1, a second transistor T2, a third transistor T3, and a first capacitor C1;

a gate of the first transistor T1 is electrically connected to the second power source terminal VGL, a first pole is electrically connected to the first node N1, and a second pole is electrically connected to the gate of the second transistor T2;

a first pole of the second transistor T2 is electrically connected to the first clock signal terminal CK, a second pole is electrically connected to a first end of the first capacitor C1, and a second end of the first capacitor C1 is connected between the second pole of the first transistor T1 and the gate of the second transistor T2;

the third transistor T3 has a gate connected between the second pole of the first transistor T1 and the gate of the second transistor T2, a first pole electrically connected to the second power source terminal VGL, and a second pole electrically connected to the second output terminal OUT 2.

In a specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 4, the fourth sub-module 22 includes: a fourth transistor T4 and a fifth transistor T5;

a gate of the fourth transistor T4 is electrically connected to the first output terminal OUT1, a first pole is electrically connected to the first power source terminal VGH, and a second pole is electrically connected to the gate of the third transistor T3;

the fifth transistor T5 has a gate electrically connected to the first output terminal OUT1, a first pole electrically connected to the first power source terminal VGH, and a second pole electrically connected to the second output terminal OUT 2.

In a specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 4, the first sub-module 11 includes: a sixth transistor T6, a seventh transistor T7, and a second capacitor C2;

a gate of the sixth transistor T6 is electrically connected to the second node N1, a first pole is electrically connected to the first power source terminal, and a second pole is electrically connected to the first node;

a gate of the seventh transistor T7 is electrically connected to the first node N1, a first pole is electrically connected to the first power source terminal VGH, and a second pole is electrically connected to the first output terminal OUT 1;

a first terminal of the second capacitor C2 is electrically connected to the first node N1, and a second terminal thereof is electrically connected to the first power source terminal VGH.

In a specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 4, the second sub-module 22 includes: an eighth transistor T8 and a third capacitor C3;

a gate of the eighth transistor T8 is electrically connected to the second node N2, a first pole is electrically connected to the second power source terminal VGL, and a second pole is electrically connected to the first output terminal OUT 1;

the third capacitor C3 has a first terminal electrically connected to the second clock signal terminal CB and a second terminal electrically connected to the second node N2.

In specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 3, the first control output module 1 further includes an input module 13 and a node control module 14;

the input block 13 is configured to provide the signal of the trigger signal terminal STV to the second node N2 under the control of the first clock signal terminal CK;

the node control module 14 is configured to supply a signal of the first clock signal terminal CK to the third node N3 under the control of the trigger signal terminal STV, supply a signal of the first power supply terminal VGH to the second node N2 under the control of the third node N3 and the second clock signal terminal CB, and supply a signal of the second clock signal terminal CB to the first node N1 under the control of the third node N3 and the second clock signal terminal CB.

In a specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 4, the input module 13 includes: a ninth transistor T9;

the ninth transistor T9 has a gate electrically connected to the first clock signal terminal CK, a first pole electrically connected to the trigger signal terminal STV, and a second pole electrically connected to the second node N2.

In a specific implementation, in the shift register provided in the embodiment of the present invention, as shown in fig. 4, the node control module 14 includes: a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, and a fourth capacitor C4;

a gate of the tenth transistor T10 is electrically connected to the second node, a first electrode is electrically connected to the first clock signal terminal, and a second electrode is electrically connected to the third node;

a gate of the eleventh transistor T11 is electrically connected to the first clock signal terminal, a first electrode is electrically connected to the second power terminal, and a second electrode is electrically connected to the third node;

a gate of the twelfth transistor T12 is electrically connected to the third node, a first electrode thereof is electrically connected to the first power source terminal, and a second electrode thereof is electrically connected to the first electrode of the thirteenth transistor;

a gate of the thirteenth transistor T13 is electrically connected to the second clock signal terminal, and a second pole is electrically connected to the second node;

a gate of the fourteenth transistor T14 is electrically connected to the third node, a first electrode is electrically connected to the second clock signal terminal, and a second electrode is electrically connected to the first electrode of the fifteenth transistor;

a gate of the fifteenth transistor T15 is electrically connected to the second clock signal terminal, and a second pole is electrically connected to the first node;

a first terminal of the fourth capacitor C4 is electrically connected to the third node N3, and a second terminal thereof is connected between the second pole of the fourteenth transistor T14 and the first pole of the fifteenth transistor T15.

It should be noted that, the above is only an example to illustrate the specific structure of each module in the shift register provided in the embodiment of the present invention, and in the implementation, the specific structure of each module is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.

In addition, the first to fifteenth transistors T1 to T15 mentioned in the present invention may be Thin Film Transistors (TFTs) or metal oxide semiconductor field effect transistors (MOS), and are not limited herein. In a specific implementation, the first and second poles of these transistors are the drain and source, respectively, and their functions can be interchanged according to the transistor type and the input signal, and are not specifically distinguished here. Generally, when the transistor is a P-type transistor, the first electrode is a source electrode, and the second electrode is a drain electrode; when the transistor is an N-type transistor, the first electrode is a drain electrode, and the second electrode is a source electrode. The first to fifteenth transistors T1 to T15 may be all P-type transistors, or the first to fifteenth transistors T1 to T15 may be all N-type transistors, and the embodiment of the present invention is described by taking the first to fifteenth transistors T1 to T15 as P-type transistors, where the P-type transistors are turned on under the action of a low potential and turned off under the action of a high potential.

The operation of the shift register shown in fig. 4 will be described, wherein in the shift register shown in fig. 4, each transistor is a P-type transistor, which is turned on under the action of a low level and turned off under the action of a high level; the input/output timing diagram of the shift register is shown in fig. 5, and specifically eight stages t1-t8 in the input/output timing diagram shown in fig. 5 are selected.

At the stage T1, the trigger signal terminal STV is a low potential signal, the first node N1 is a high potential, the first clock signal terminal CK is a low potential signal, the second clock signal terminal CB is a high potential signal, so the ninth transistor T9 and the eleventh transistor T11 are turned on, the turned-on ninth transistor T9 transmits the low potential signal of the trigger signal terminal STV to the gate of the tenth transistor T10 and the second node N2, respectively, so the sixth transistor T6, the eighth transistor T8 and the tenth transistor T10 are all turned on, the low potential signal of the first clock signal terminal CK is transmitted to the third node N3, so the twelfth transistor T12 and the fourteenth transistor T14 are turned on, the thirteenth transistor T13 and the fifteenth transistor T15 are turned off by the high potential signal of the second clock signal terminal CB, and the high potential signal for the first power terminal VGH is transmitted to the gate of the seventh transistor T7 through the turned-on sixth transistor T6, accordingly, the seventeenth transistor T17 is turned off, the low potential signal of the second power source terminal VGL is transmitted to the first output terminal OUT1 through the turned-on eighth transistor T8, and thus both the fourth transistor T4 and the fifth transistor T5 are turned on, the high potential signal of the first power source terminal VGH is transmitted to the gate of the third transistor through the turned-on fourth transistor T4, the third transistor T3 is turned off, the high potential signal of the first power source terminal VGH is transmitted to the second output terminal OUT2 through the turned-on fifth transistor T5, the first transistor T1 is turned on by the low potential signal of the second power source terminal VGL, the signal of the high potential first node N1 is transmitted to the fourth node N4 through the turned-on first transistor T1, and the second transistor T2 is turned off, so that the first output terminal OUT1 outputs a low potential signal and the second output terminal OUT2 outputs a high potential signal during a period T1.

At the stage T2, the trigger signal terminal STV is a low-level signal, the first node N1 is a high-level signal, the first clock signal terminal CK is a high-level signal, and the second clock signal terminal CB is a low-level signal, so that the ninth transistor T9 and the eleventh transistor T11 are turned off, the second node N2 maintains a low level, the eighth transistor T8 is turned on, the low-level signal of the second power terminal VGL is transmitted to the first output terminal OUT1 through the turned-on eighth transistor T8, so that the fourth transistor T4 and the fifth transistor T5 are both turned on, the high-level signal of the first power terminal VGH is transmitted to the second output terminal OUT2 through the turned-on fifth transistor T5, so that at the stage T2, the first output terminal OUT1 outputs a low-level signal, and the second output terminal 2 outputs a high-level signal.

At a stage T3, the trigger signal terminal STV is a high potential signal, the eighth transistor T8 is gradually turned off due to the rising of the gate voltage, the first clock signal terminal CK is a low potential signal, the second clock signal terminal CB is a high potential signal, and the first node N1 is still maintained at a high potential, so the ninth transistor T9 and the eleventh transistor T11 are turned on, the turned-on ninth transistor T9 transmits the high potential signal of the trigger signal terminal STV to the gate of the tenth transistor T10 and the second node N2, respectively, so the sixth transistor T6, the eighth transistor T8 and the tenth transistor T10 are all turned off, the low potential signal of the second power terminal VGL is transmitted to the third node N3 through the eleventh transistor T11, so the fourteenth transistor T14 is turned on for CB ═ 1, so the first node N1 is still at a high potential, the seventh transistor T7 is turned off, the potential of the fourth node N4 is at a high potential, and the third transistor T2 and 3 are all turned off, therefore, during the period t3, the first output terminal OUT1 still outputs a low signal, and the second output terminal OUT2 still outputs a high signal.

At the stage t4, the STV is a high signal, the CK is a high signal, the CB is a low signal, therefore, the ninth transistor T9 and the eleventh transistor T11 are turned off, the third node N3 is maintained at the low potential, the second clock signal terminal CB is a low potential signal, and thus the first node N1 is at the low potential, thereby making the fourth node N4 also be at a low potential, when T2 and T3 are turned on, the first capacitor C1 is connected to the high potential signal of the first terminal written CK, the low potential signal of the second power terminal VGL is transmitted to the second output terminal OUT2 through the turned-on third transistor T3, since the first node N1 is at a low potential, the seventh transistor T7 is turned on, a high potential signal of the first power source terminal VGH is transmitted to the first output terminal OUT1 through the turned-on seventh transistor T7, therefore, in the period t4, the first output terminal OUT1 outputs a high signal, and the second output terminal OUT2 outputs a low signal.

At the stage T5, the trigger signal terminal STV is a high-level signal, the first clock signal terminal CK is a low-level signal, and the second clock signal terminal CB is a high-level signal, when CK becomes a low-level, the first terminal of the first capacitor C1 changes from a high-level to a low-level, and at this time, the potential of the fourth node N4 is pulled to a second-level low-voltage, so that the third transistor T3 is fully turned on, the low-level signal of the second power terminal VGL is transmitted to the second output terminal OUT2 through the turned-on third transistor T3, the first node N1 maintains the low-level, so that the seventh transistor T7 is turned on, the high-level signal of the first power terminal VGH is transmitted to the first output terminal OUT1 through the turned-on seventh transistor T7, and therefore, at the stage T5, the first output terminal 1 outputs a high-level signal, and the second output terminal OUT2 outputs a low-level signal.

At the stage T6, the trigger signal terminal STV is a low-potential signal, the first clock signal terminal CK is a high-potential signal, the second clock signal terminal CB is a low-potential signal, the first node N1 maintains a low-potential level, the first terminal of the first capacitor C1 writes a high potential, so that the voltage at the point N4 of the fourth node N4 becomes a low-potential level, the third transistor T3 is still turned on, the low-potential signal of the second power terminal VGL is transmitted to the second output terminal OUT2 through the turned-on third transistor T3, the first node N1 still maintains a low potential, so that the seventh transistor T7 is turned on, the high-potential signal of the first power terminal VGH is transmitted to the first output terminal OUT1 through the turned-on seventh transistor T7, so that at the stage T5, the first output terminal OUT1 outputs a high-potential signal, and the second output terminal OUT2 outputs a low-potential signal.

At the stage t7, the trigger signal terminal STV is a low-potential signal, the first clock signal terminal CK is a low-potential signal, the second clock signal terminal CB is a high-potential signal, the fourth node N4 becomes a high-potential signal, and the second output terminal OUT2 outputs a high-potential signal; the first node N1 becomes a high potential, but since the gate-source voltage Vgs of the seventh transistor T7 is 0 at this time, the potential output from the first output terminal OUT1 is slowly decreased from the potential at the stage of T6.

At the stage T8, the trigger signal terminal STV is a low-level signal, the first clock signal terminal CK is a high-level signal, and the second clock signal terminal CB is a low-level signal, at this time, the second node N2 is pulled to a second-level low level, the eighth transistor T8 is fully turned on, the first output terminal OUT1 outputs a low-level signal, the fourth transistor T4 is also fully turned on, and the second output terminal OUT2 outputs a high-level signal.

In order to verify that the first output terminal OUT1 and the second output terminal OUT2 of the shift register shown in fig. 4 provided by the embodiment of the present invention can output signals with opposite potentials, the embodiment of the present invention performs simulation of input and output timings on the shift register shown in fig. 4, as shown in fig. 6, it can be seen that the simulation result is consistent with the timing diagram shown in fig. 5 of the present application, and therefore the first output terminal OUT1 and the second output terminal OUT2 of the shift register provided by the embodiment of the present invention can output signals with opposite potentials.

In summary, the first output terminal OUT1 and the second output terminal OUT2 in the shift register shown in fig. 4 can output signals with opposite potentials, so that the first output terminal OUT1 is electrically connected to the emission control terminal EM in the pixel circuit of fig. 2, and the second output terminal OUT2 is electrically connected to the gate of the anode reset transistor M7 in the pixel circuit of fig. 2. Thus, in the pixel lighting phase, the low-potential signal output by the first output terminal OUT1 controls the lighting control transistors (M5 and M6) to be turned on to realize the lighting of the lighting device L; in the rest non-light emitting period, the high potential signal output by the second output terminal OUT2 controls the anode reset transistor M7 in fig. 2 to be turned on to provide a continuous initialization voltage to the anode of the light emitting device L, so that no extra current is generated across the anode and the cathode of the light emitting device L, and therefore, weak light emission of pixels which should not emit light can be avoided, and the optical evaluation result of the display panel is improved.

Based on the same inventive concept, an embodiment of the present invention provides a display panel including a display area and a non-display area, the display area including a plurality of pixel circuits and a light emitting device electrically connected to the pixel circuits, the pixel circuits including an anode reset transistor electrically connected to an anode of the light emitting device; the non-display area comprises a grid driving circuit, and the grid driving circuit comprises a plurality of cascaded shift registers; wherein the content of the first and second substances,

the signal input end of the first-stage shift register is electrically connected with the trigger signal end;

except the first stage of shift register, the signal input ends of the other shift registers at each stage are respectively and electrically connected with the first output end of the shift register at the previous stage;

and the second output end of each stage of shift register is respectively and electrically connected with the grid electrode of the corresponding anode reset transistor.

For convenience of description, fig. 7 shows only eight shift registers in the gate driving circuit, which are the 1 st stage shift register, the 2 nd stage shift register, the 3 rd stage shift register, the 4 th stage shift register, the N-3 rd stage shift register, the N-2 nd stage shift register, the N-1 st stage shift register, and the N th stage shift register. Except for the 1 st-stage shift register, the signal input ends of the shift registers of the other stages are respectively and electrically connected with the first output end OUT1 of the shift register of the previous stage, and the second output end OUT2 of the shift register of each stage is respectively and electrically connected with the gate of the corresponding anode reset transistor (M7 in fig. 2).

Specifically, since the principle of the display panel to solve the problem is similar to that of the shift register, the implementation of the display panel can refer to the implementation of the shift register, and repeated descriptions are omitted.

Based on the same inventive concept, an embodiment of the present invention provides a display device, including the display panel provided in the embodiment of the present invention. The display device can be applied to any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Since the principle of the display device to solve the problem is similar to that of the display panel, the display device can be implemented by the display panel, and repeated descriptions are omitted.

The shift register comprises a first control output module and a second control output module, wherein the first control output module comprises a first node and a first output end, and the first node is used for controlling the first output end to output a signal with a potential opposite to that of the first node; the second control output module comprises a second output end, and the second control output module is used for enabling the second output end to output a signal with the opposite potential to the first output end under the control of the first node and the first output end. The shift register provided by the invention is provided with two output ends, the second output end outputs a signal with a potential opposite to that of the signal output by the first output end, the first output end can be electrically connected with a light-emitting control end in the pixel circuit, and the second output end is electrically connected with a grid electrode of an anode reset transistor in the pixel circuit. In the pixel light-emitting stage, only the signal output by the first output end controls the light-emitting control transistor to be conducted so as to realize the light-emitting of the light-emitting device; in other non-light emitting stages, only the signal output by the second output end controls the anode reset transistor to be conducted so as to provide continuous initialization voltage for the anode of the light emitting device, so that extra current is not generated at two ends of the anode and the cathode of the light emitting device, and therefore, weak light emission of pixels which should not emit light can be avoided, and the optical evaluation result of the display panel is improved.

While preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the disclosure.

It will be apparent to those skilled in the art that various changes and modifications may be made to the disclosed embodiments without departing from the spirit and scope of the disclosed embodiments. Thus, if such modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to encompass such modifications and variations.