1. A reference current generating circuit for generating a reference current required for a memory cell operation for Nor Flash, comprising:

a precharge circuit (1) with a changeover switch for supplying a precharge signal and outputting a reference voltage signal generated based on the precharge signal;

the reference current generating circuit (2) is used for adjusting output current by a plurality of first storage units, is electrically connected with the pre-charging circuit (1), and is used for receiving a reference voltage signal and outputting an initial reference current signal;

the comparison circuit (3) with a change-over switch is electrically connected with the reference current generation circuit (2) and is used for receiving the initial reference current signal and outputting a final reference current signal acting on the target storage unit;

the reference current reading circuit (4) is electrically connected with the reference current generating circuit (2) and is used for receiving an initial reference current signal and outputting a final reference current signal;

the pre-charge circuit (1) may adjust the final reference current signal by a reference voltage signal adjusting the threshold voltage of the first memory cell in the reference current generation circuit (2) to change the initial reference current signal.

2. A reference current generating circuit according to claim 1, wherein said pre-charge circuit (1) comprises:

the pre-charging power supply with a change-over switch is used for sending out a pre-charging signal;

the second storage units are electrically connected with the pre-charging power supply through bit lines and used for receiving pre-charging signals and outputting reference voltage signals;

the number of the second storage units is consistent with that of the first storage units, the second storage units are connected with the first storage units through word lines, and a reference voltage signal can be generated by matching with a pre-charging signal sent by a pre-charging power supply so as to adjust the threshold voltage of the first storage units and change the magnitude of a reference current signal generated after the second storage units receive the reference voltage signal.

3. A reference current generating circuit according to claim 2, further comprising a bit line current reading circuit (5) electrically connected to the pre-charge circuit (1) and the reference current generating circuit (2) for reading and outputting a sum of the bit line current of the first memory cell, the bit line current of the second memory cell, and the bit line currents of the first memory cell and the second memory cell.

4. The circuit of claim 2, wherein the reference voltage signal is a drain voltage of the second memory cell.

5. The reference current generating circuit according to claim 1, wherein the reference voltage generating circuit comprises:

the first storage units are electrically connected with the pre-charging circuit (1) through word line terminals;

the operational amplifier is electrically connected with the pre-charging circuit (1) and the first storage unit and is used for clamping and adjusting the threshold voltage of the first storage unit so that the first storage unit outputs an initial current signal;

and the first PMOS tubes are electrically connected with the operational amplifier and the first storage unit and used for receiving the initial current signal and outputting an initial reference current signal.

6. A reference current generating circuit according to claim 1, wherein said comparing circuit (3) comprises:

the change-over switch is electrically connected with the reference current generating circuit (2) and is used for controlling whether an initial reference current signal is conducted or not;

and the second PMOS tubes are electrically connected with the transfer switch and the bit line of the target memory cell and used for receiving the initial reference current signal, outputting a final reference current signal and comparing the final reference current signal with the bit line current signal of the target memory cell to generate a reference voltage signal.

7. A reference current generating circuit according to claim 6, characterized in that the reference current reading circuit (4) comprises a number of third PMOS transistors electrically connected to the reference current generating circuit (2).

8. A reference current generating method based on the reference current generating circuit of any one of claims 1 to 7, for generating the reference current required for the operation of the memory cell for Nor Flash, comprising the steps of:

s1, according to the operation instruction, opening the pre-charging circuit (1) to output a pre-charging signal and a reference voltage signal generated based on the pre-charging signal;

s2, adjusting the threshold voltage of the first storage unit by using the reference voltage signal to enable the reference current generation circuit (2) to output an initial reference current signal;

s3, reading and calculating whether the initial reference current signal can generate the expected final reference current signal through the reference current reading circuit (4);

s4, if yes, the change-over switch of the comparison circuit (3) is opened to generate and output the final reference current signal, if not, the pre-charge signal is adjusted, and the steps S2-S4 are executed again.

9. An electronic device comprising a processor and a memory, the memory storing computer readable instructions which, when executed by the processor, perform the steps of the method of claim 8.

10. A test fixture comprising a reference current generating circuit according to any one of claims 1-7.

Background

In the Nor Flash read operation, a feedback voltage Vsen is generally formed by comparing the bit line currents Icell and Isen of the target memory cell, and then amplified and outputted by a sense amplifier, and data reading and current regulation are performed by using the feedback voltage Vsen, and the conventional reference current generating circuit is shown in fig. 1.

As can be seen from fig. 1, the reference current in such a reference current circuit can be calculated by the following conversion equation:

。

according to the conversion formula, the reference current generated by the circuit is directly related to the resistance RES and the reference voltage Vref, and the Vref is generally a band gap reference voltage which basically does not change along with the process/voltage/temperature; however, during the read operation of Nor Flash, since the word line terminal RD _ WL of the target memory cell is generally generated by a charge pump, the voltage value thereof may float within a certain range in different processes/voltages/temperatures, causing the bit line current Icell to float, and since the memory cell is a real transistor, the feedback voltage Vsen may also affect the bit line current Icell.

Assuming that Q/(N × M) is a proportionality constant that is not affected by process/voltage/temperature, Vref is a bandgap reference in the formula, which is not affected by process/voltage/temperature, the resistance RES will be floated within a certain range by the process/voltage/temperature, and the floating variation is not consistent with the floating variation corresponding to the memory cell, so that many factors in the bit line current Icell and the reference current Isen will vary with the process/voltage/temperature, and the variation range and range thereof cannot be mutually cancelled at all.

In view of the above problems, no effective technical solution exists at present.

Disclosure of Invention

An object of the embodiments of the present application is to provide a reference current generating circuit, a method, an electronic device, and a test fixture, which enable the floating of the generated reference current to be consistent with the floating of the bit line current of a target memory cell, so as to improve the precision of a read operation.

In a first aspect, an embodiment of the present application provides a reference current generating circuit for generating a reference current required by a memory cell operation for Nor Flash, including:

a precharge circuit with a transfer switch for supplying a precharge signal and outputting a reference voltage signal generated based on the precharge signal;

the reference current generating circuit is electrically connected with the pre-charging circuit and used for receiving a reference voltage signal and outputting an initial reference current signal;

the comparison circuit with the change-over switch is electrically connected with the reference current generating circuit and is used for receiving the initial reference current signal and outputting a final reference current signal acting on the target storage unit;

the reference current reading circuit is electrically connected with the reference current generating circuit and is used for receiving an initial reference current signal and outputting a final reference current signal;

the pre-charge circuit may adjust the final reference current signal by adjusting a threshold voltage of a first memory cell in the reference current generation circuit with the reference voltage signal to change the initial reference current signal.

The reference current generating circuit, wherein the pre-charging circuit comprises:

the pre-charging power supply with a change-over switch is used for sending out a pre-charging signal;

the second storage units are electrically connected with the pre-charging power supply through bit lines and used for receiving pre-charging signals and outputting reference voltage signals;

the number of the second storage units is consistent with that of the first storage units, the second storage units are connected with the first storage units through word lines, and a reference voltage signal can be generated by matching with a pre-charging signal sent by a pre-charging power supply so as to adjust the threshold voltage of the first storage units and change the magnitude of a reference current signal generated after the second storage units receive the reference voltage signal.

The reference current generating circuit further comprises a bit line current reading circuit electrically connected to the pre-charging circuit and the reference current generating circuit, and configured to read and output a sum of a bit line current of the first memory cell, a bit line current of the second memory cell, and a bit line current of the first memory cell and a bit line current of the second memory cell.

In the reference current generating circuit, the reference voltage signal is a drain voltage of the second storage unit.

The reference current generating circuit, wherein the reference voltage generating circuit comprises:

the first storage units are electrically connected with the pre-charging circuit through word line terminals;

the operational amplifier is electrically connected with the pre-charging circuit and the first storage unit and is used for clamping and adjusting the threshold voltage of the first storage unit so as to enable the first storage unit to output an initial current signal;

and the first PMOS tubes are electrically connected with the operational amplifier and the first storage unit and used for receiving the initial current signal and outputting an initial reference current signal.

The reference current generating circuit, wherein the comparing circuit comprises:

the change-over switch is electrically connected with the reference current generating circuit and is used for controlling whether an initial reference current signal is conducted or not;

and the second PMOS tubes are electrically connected with the transfer switch and the bit line of the target memory cell and used for receiving the initial reference current signal, outputting a final reference current signal and comparing the final reference current signal with the bit line current signal of the target memory cell to generate a reference voltage signal.

The reference current generation circuit comprises a plurality of third PMOS tubes electrically connected with a reference current generation circuit.

In a second aspect, an embodiment of the present application further provides a reference current generating method based on the above reference current generating circuit, for generating a reference current required by a memory cell operation for Nor Flash, including the following steps:

s1, according to the operation instruction, opening a pre-charging circuit to output a pre-charging signal and a reference voltage signal generated based on the pre-charging signal;

s2, adjusting the threshold voltage of the first storage unit by using the reference voltage signal to enable the reference current generation circuit to output an initial reference current signal;

s3, reading and calculating whether the initial reference current signal can generate the expected final reference current signal through the reference current reading circuit;

s4, if yes, the change-over switch of the comparison circuit is opened to generate and output the final reference current signal, if not, the pre-charge signal is adjusted, and steps S2-S4 are executed again.

In a third aspect, an embodiment of the present application further provides an electronic device, including a processor and a memory, where the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the steps in the method as provided in the first aspect are executed.

In a fourth aspect, an embodiment of the present application further provides a test fixture, which includes the reference current generating circuit.

As can be seen from the above, the reference current generating circuit, the method, the electronic device and the test fixture provided in the embodiments of the present application, wherein a final reference current signal generated by the circuit is generated based on the first storage unit, and the first storage unit and the target storage unit are both storage units and have the same electrical performance, so that the reference current generated in the embodiments of the present application is more accurate, and represents a current value that the target storage unit should output under the same operating parameter.

Drawings

Fig. 1 is a schematic structural diagram of a conventional reference current generating circuit.

Fig. 2 is a schematic structural diagram of a reference current generating circuit according to an embodiment of the present disclosure.

Fig. 3 is a flowchart of a reference current generating method according to an embodiment of the present disclosure.

Fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Reference numerals: 1. a precharge circuit; 2. a reference current generation circuit; 3. a comparison circuit; 4. a reference current reading circuit; 5. a bit line current reading circuit.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

In a first aspect, referring to fig. 2, fig. 2 is a reference current generating circuit for generating a reference current required for a memory cell operation in Nor Flash according to some embodiments of the present application, including:

a precharge circuit 1 with a changeover switch for supplying a precharge signal and outputting a reference voltage signal generated based on the precharge signal;

the reference current generating circuit 2 is electrically connected with the pre-charging circuit 1 and used for receiving a reference voltage signal and outputting an initial reference current signal;

a comparison circuit 3 with a change-over switch, electrically connected to the reference current generation circuit 2, for receiving the initial reference current signal and outputting a final reference current signal acting on the target memory cell;

the reference current reading circuit 4 is electrically connected to the reference current generating circuit 2 and is used for receiving the initial reference current signal and outputting a final reference current signal;

the precharge circuit 1 may adjust the final reference current signal by the reference voltage signal adjusting the threshold voltage of the first memory cell in the reference current generation circuit 2 to change the initial reference current signal.

Specifically, the final reference current signal is conducted with the bit line voltage of the target memory cell to generate the feedback voltage information.

In the reference current generating circuit of the embodiment of the application, an initial reference current signal is generated by matching a pre-charging circuit 1 with a reference current generating circuit 2 with a first memory cell, and a final reference current signal is generated by a comparison circuit 3 and is used for comparing with a bit line current of a target memory cell to generate a feedback voltage signal; the final reference current signal generated by the circuit is generated based on the adjustment of the first storage unit, the first storage unit and the target storage unit are both memory cells (memory cells) and have the same electrical performance, so that the reference current generated by the embodiment of the application is more accurate and represents the current value which should be output by the target storage unit under the same operation parameter.

More specifically, the embodiment of the present application is particularly suitable for a read operation based on that the final reference current signal generated by the first memory cell is matched to the target current of the target cell with the floating effect of the same process/voltage/temperature when performing the corresponding operation, so that the target memory cell can be adjusted based on the reference current including the relevant floating effect to accurately achieve the current required by the read operation and accurately complete the read operation.

More specifically, the embodiment of the present application performs a write operation on the first memory cell of the reference current generation circuit 2 by the precharge circuit 1 to change the threshold voltage of the first memory cell, and then the reference current generation circuit 2 can accurately output the initial reference current signal based on the first memory cell after the threshold voltage is written and adjusted.

Specifically, in the embodiment of the present application, a reference current generating circuit is connected to a master controller, and a comparing circuit 3 is connected to a target memory cell; according to the instruction given by the main controller, the change-over switch of the pre-charging circuit 1 can be opened to start the generation of the initial reference current signal; and secondly, the main controller can calculate and obtain final reference current information in real time through the reference current reading circuit 4, and based on the fact that the final reference current information reaches the preset reference current information, a change-over switch in the comparison circuit 3 is opened to control the final reference current signal and the conduction of the bit line current of the target storage unit so as to obtain feedback voltage signals generated by the conduction of the two circuits.

Specifically, in order to clearly show the component layout structure of the reference current generation circuit according to the embodiment of the present application, the components in fig. 1 are simplified, that is, multiple components that are connected in series and repeated are combined into one component for expression, for example, only one first memory cell Fcell1 is drawn in the drawing for expression as N first memory cells Fcell1, and is labeled as Fecll1 × N, where N is the number corresponding to the first memory cell Fcell 1.

In some preferred embodiments, the precharge circuit 1 includes:

the pre-charging power supply with a change-over switch is used for sending out a pre-charging signal;

the second storage units are electrically connected with the pre-charging power supply through bit lines and used for receiving pre-charging signals and outputting reference voltage signals;

the number of the second storage units is consistent with that of the first storage units, the second storage units are connected with the first storage units through word lines, and a reference voltage signal can be generated by matching with a pre-charging signal sent by a pre-charging power supply so as to adjust the threshold voltage of the first storage units and change the magnitude of a reference current signal generated after the second storage units receive the reference voltage signal.

Specifically, the second storage unit is charged after the transfer switch of the power supply is precharged, and the bit line terminal of the charged second storage unit can apply a corresponding reference voltage signal to the reference current generation circuit 2 according to the charged amount.

More specifically, the number of the second memory cells is set to be the same as that of the first memory cells, so that the two memory cells can correspond to each other one by one and are connected through a word line, and the reference voltage signal can be copied to the drain of the first memory cell by using the structure of the reference current generating circuit 2 to generate corresponding current information.

The supply of reference voltage information is realized to the combined circuit structure that adopts precharge power supply cooperation second memory cell in this application embodiment to can exert the reference voltage information of demand to first memory cell accurately, have the regulation precision height, adjust convenient characteristics.

More specifically, the precharge power supply performs a write operation on the second memory cell using the precharge signal so that the second memory cell outputs reference voltage information, and the reference current generation circuit 2 acquires the reference voltage information and performs a write operation on the first memory cell by copying the reference voltage information applied to the first memory cell therein to change the threshold voltage of the first memory cell, thereby allowing the reference current generation circuit 2 to accurately output a desired initial reference current signal based on the first memory cell.

In some preferred embodiments, the memory further includes a bit line current reading circuit 5 electrically connected to the precharge circuit 1 and the reference current generating circuit 2, and configured to read and output a sum of the bit line current of the first memory cell, the bit line current of the second memory cell, and the bit line currents of the first memory cell and the second memory cell.

Specifically, the embodiment of the present application may output the bit line current of the first memory cell or the bit line current of the second memory cell or the sum of the bit line currents of the first memory cell and the second memory cell through the bit line current reading circuit 5, the output current value is generally received by the master controller, and the master controller may control the adjustment of the precharge signal according to the current values, that is, the bit line current on the corresponding bit line is obtained at the stage of the write operation of the first memory cell or the second memory cell, so as to change the precharge signal output by the precharge power supply to change the programming data of the first memory cell and/or the second memory cell, thereby implementing the precise adjustment of the threshold voltage of the second memory cell at the stage of the write operation.

More specifically, the bit line current reading circuit 5 includes two reading switches connected in parallel and electrically connected to the bit line of the first memory cell and the bit line of the second memory cell, respectively.

In some preferred embodiments, the reference voltage signal is a drain voltage of the second memory cell.

In some preferred embodiments, the reference voltage generating circuit includes:

the first storage units are electrically connected with the pre-charging circuit 1 through word line terminals;

the operational amplifier is electrically connected with the pre-charging circuit 1 and the first storage unit and is used for clamping and adjusting the threshold voltage of the first storage unit so as to enable the first storage unit to output an initial current signal;

and the first PMOS tubes are electrically connected with the operational amplifier and the first storage unit and used for receiving the initial current signal and outputting an initial reference current signal.

Specifically, the operational amplifier is electrically connected to the drain of the first memory cell, so that the leakage voltage, which is the reference voltage signal output by the second memory cell, can be copied to the drain of the first memory cell, and thus the threshold voltage, i.e., the read voltage, of the first memory cell can be indirectly adjusted and changed according to the precharge signal.

More specifically, the gate, the drain, and the source of the adjusted first memory cell are all identical to the bias condition of the target memory cell, and the first memory cell and the target memory cell are subjected to the same process/voltage/temperature floating effect, so that the adjusted first memory cell can be used as a technical guarantee for generating an accurate read current, i.e., an accurate final reference current signal.

More specifically, the initial current signal output by the first storage unit utilizes a plurality of first PMOS tubes to control drain-source current through gate-source voltage, so that the initial current signal is subjected to noise reduction and is stably output as an initial reference current signal.

More specifically, the second memory cell can be replaced by any current source mode with less floating, because the difference of the bit line current caused by the floating of the drain voltage of the target memory cell in the NOR flash is not obvious when the target memory cell is read in the saturation region.

In some preferred embodiments, the comparison circuit 3 includes:

the change-over switch is electrically connected with the reference current generating circuit 2 and is used for controlling whether the initial reference current signal is conducted or not;

and the second PMOS tubes are electrically connected with the transfer switch and the bit line of the target memory cell and used for receiving the initial reference current signal, outputting a final reference current signal and comparing the final reference current signal with the bit line current signal of the target memory cell to generate a reference voltage signal.

More specifically, since the target memory cell is generally a memory array, the number of the target memory cell is different from that of the second memory cell, and the initial reference current signal output after passing through the first PMOS transistor is smaller than the initial current signal, the initial reference current signal needs to be amplified by the second PMOS transistor, so that the initial reference current signal is amplified to be the final reference current signal, and can be used for generating the feedback voltage signal.

Specifically, the changeover switch may be switched based on the master based on the information read by the reference current reading circuit 4 to control whether or not the final reference current signal is on.

In some preferred embodiments, the reference current reading circuit 4 includes several third PMOS transistors electrically connected to the reference current generating circuit 2.

Specifically, the initial reference current signal is converted and output by using the third PMOS transistor, so that the main controller can directly or indirectly obtain the final reference current signal, when the number of the third PMOS transistor is consistent with that of the second PMOS transistor, the signal output by the reference current reading circuit 4 can be directly regarded as the final reference current signal, and when the number of the third PMOS transistor is inconsistent with that of the second PMOS transistor, the final reference current signal can be indirectly calculated according to the number ratio of the third PMOS transistor to the second PMOS transistor, and then the final reference current signal is output.

Example 1

As shown in fig. 2, the pre-charge power SA pre-charge is electrically connected to N second memory cells Fcell2, the N second memory cells Fcell2 are electrically connected to N first memory cells Fcell1 through word lines RD _ WL, the operational amplifier OP and the positive and negative electrodes are respectively connected to the drains of the second memory cells Fcell2 and the first memory cells Fcell1, the first memory cells Fcell1 are connected to M first PMOS transistors P1, the gate of the first PMOS transistor P1 is connected to the output terminal of the operational amplifier OP and to the gates of Q second PMOS transistors P2, the second PMOS transistor P2 is connected to the bit line of the target memory cell, the gate of the third PMOS transistor P3 is connected to the gate of the first PMOS transistor P1, the switches S1 and S2 are respectively connected to the first memory cells Fcell1 and the second memory cells Fcell2, and the switch SA is hidden in the figure.

After sending a precharge signal, the precharge power supply SA pre-charge performs a write operation on the second memory cell Fcell2, so that the drain of the second memory cell outputs reference voltage information Vbl1, the operational amplifier OP acquires the reference voltage information Vbl1, copies the reference voltage information Vbl1 and applies the copied reference voltage information to the first memory cell Fcell1, and closes the switches S1 and S2 respectively to read the bit line currents of the bit lines of the first memory cell Fcell1 and the second memory cell Fcell2 respectively, so that the threshold voltage Vt of the first memory cell Fcell1 can be changed through the write operation; after the threshold voltage of the first memory cell is adjusted, stable power supply is performed through a pre-charge power supply SA pre-charge, each first memory cell Fcell1 outputs a read current Ifcell, N output read currents Ifcell are overlapped to generate an initial current signal, an initial reference current signal is generated after M first PMOS (P-channel metal oxide semiconductor) tubes PI are passed through, and a final reference current signal Isen is generated after the initial reference current signal passes through Q second MOS tubes, so that the calculation formula of the final reference current signal Isen is as follows:

。

it can be seen that the final reference current signal Isen is correlated to the read current Ifcell output by the first memory cell Fcell1, so that the reference current generated by the embodiment of the present application is affected by the same process/voltage/temperature fluctuations experienced by the target memory cell.

Referring to fig. 3, in a second aspect, fig. 3 is a reference current generating method based on the above reference current generating circuit for generating a reference current required by a memory cell operation for Nor Flash according to some embodiments of the present application, including the following steps:

s1, according to the operation instruction, opening the precharge circuit 1 to output a precharge signal and a reference voltage signal generated based on the precharge signal;

specifically, according to the operation command, a transfer switch of the pre-charge power supply is opened, so that the pre-charge power supply generates a pre-charge signal, and the second storage unit receives the pre-charge signal to generate a reference voltage signal.

S2, using the reference voltage signal to adjust the threshold voltage of the first memory cell to make the reference current generation circuit 2 output the initial reference current signal,

specifically, the reference voltage signal is copied to the drain of the first storage unit by using the reference voltage signal in cooperation with the bit line current reading circuit 5 and the operational amplifier to adjust the threshold voltage of the first storage unit, then stable power supply is performed to enable the second storage unit to output a stable initial current signal, and the first PMOS transistor is used for outputting the stable initial reference current signal after controlling the current of the initial current signal.

S3, reading and calculating whether the initial reference current signal can generate the expected final reference current signal by the reference current reading circuit 4;

s4, if yes, the change-over switch of the comparison circuit 3 is opened to generate and output the final reference current signal, and if not, the precharge signal is adjusted, and steps S2-S4 are executed again.

In the reference current generation method of the embodiment of the application, an initial reference current signal is generated by matching a pre-charging circuit 1 with a reference current generation circuit 2 with a first memory cell, and a final reference current signal is generated by a comparison circuit 3 and is used for comparing with a bit line current of a target memory cell to generate a feedback voltage signal; the final reference current signal generated by the circuit is generated based on the first storage unit adjustment, and compared with the reference current generated based on the reference voltage and the resistor in the traditional method, the problem that the reading operation precision is inaccurate due to the fact that the reference current generated by the reference voltage and the resistor cannot be well and accurately matched with the current output by the target storage unit due to the floating influence of the manufacturing process, the voltage and the temperature is solved.

In a third aspect, referring to fig. 4, fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application, and the present application provides an electronic device 300, including: the processor 301 and the memory 302, the processor 301 and the memory 302 being interconnected and communicating with each other via a communication bus 303 and/or other form of connection mechanism (not shown), the memory 302 storing a computer program executable by the processor 301, the processor 301 executing the computer program when the computing device is running to perform the method of any of the alternative implementations of the embodiments described above.

In a fourth aspect, an embodiment of the present application further provides a test fixture, which includes the reference current generating circuit; the test tool comprises the reference current generating circuit, and the structure of the reference current generating circuit of the test tool can refer to the embodiment and is not repeated again; it can be understood that, since the test fixture of the embodiment of the present application adopts the above-mentioned technical solution of the reference current generating circuit, the test fixture has all the above-mentioned beneficial effects.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.