1. A display panel driving circuit for driving a plurality of sub-pixels of a display panel, the display panel driving circuit comprising:

a compensation circuit for converting a first input gray scale data into a first output gray scale data corresponding to a first data signal of a first sub-pixel of the plurality of sub-pixels, wherein the first sub-pixel is located in a first region of the plurality of regions of the display panel, and a first difference between the first input gray scale data and the first output gray scale data is associated with a first voltage polarity of the first data signal or the first region.

2. The display panel driving circuit according to claim 1, wherein the first difference is different from a second difference between a second input gray scale data and a second output gray scale data converted by the compensation circuit, wherein the first voltage polarity of the first data signal corresponding to the first output gray scale data is opposite to the second voltage polarity of the second data signal corresponding to the second output gray scale data, wherein the first input gray scale data is equal to the second input gray scale data.

3. The display panel driving circuit according to claim 1, wherein the first difference is equal to zero when the first region is located near a center of the display panel, and wherein the first difference is not zero when the first region is located near four outermost sides of the display panel.

4. The display panel driving circuit according to claim 1, wherein a sub-pixel voltage of the first sub-pixel is deviated from the first data signal by a voltage associated with the first difference between the first input gray scale data and the first output gray scale data.

5. The display panel driving circuit according to claim 1, wherein the first difference between the first input gray scale data and the first output gray scale data is associated with a previous voltage of the first data signal, the first output gray scale data is associated with a current voltage of the first data signal, the previous voltage of the first data signal is transmitted to a second subpixel of the plurality of subpixels, and the second subpixel is disposed adjacent to the first subpixel.

6. The display panel driving circuit according to claim 1, wherein the compensation circuit is provided in a timing controller.

7. The display panel driving circuit according to claim 1, wherein the display panel is divided into the plurality of regions, each of the plurality of regions having at least one of the plurality of sub-pixels arranged therein.

8. The display panel driving circuit according to claim 1, wherein a first size of the first region is different from a second size of a second region of the plurality of regions.

9. The display panel driving circuit according to claim 1, wherein the first input gray scale data is converted into the first output gray scale data according to a first negative compensation look up table of at least one negative compensation look up table corresponding to a negative voltage polarity or a first positive compensation look up table of at least one positive compensation look up table corresponding to a positive voltage polarity, wherein one of the at least one negative compensation look up table and one of the at least one positive compensation look up table are associated with one of the plurality of regions.

10. The display panel driving circuit according to claim 1, wherein the first difference between the first input gray scale data and the first output gray scale data is associated with a present voltage of the first data signal, and the first output gray scale data is associated with a present voltage of the first data signal.

11. A display panel driving method for driving a plurality of sub-pixels of a display panel, the display panel driving method comprising:

converting a first input gray scale data into a first output gray scale data corresponding to a first data signal of a first sub-pixel of the plurality of sub-pixels, wherein the first sub-pixel is located in a first area of a plurality of areas of the display panel, and a first difference between the first input gray scale data and the first output gray scale data is associated with a first voltage polarity of the first data signal or the first area.

12. The display panel driving method of claim 11, wherein the first difference is different from a second difference between a second input gray scale data and a second output gray scale data converted by the compensation circuit, wherein the first voltage polarity of the first data signal corresponding to the first output gray scale data is opposite to the second voltage polarity of the second data signal corresponding to the second output gray scale data, wherein the first input gray scale data is equal to the second input gray scale data.

13. The display panel driving method according to claim 11, wherein the first difference is equal to zero when the first region is located near a center of the display panel, and wherein the first difference is not zero when the first region is located near the outermost four side edges of the display panel.

14. The display panel driving method of claim 11, wherein a sub-pixel voltage of the first sub-pixel deviates from the first data signal by a voltage associated with the first difference between the first input gray scale data and the first output gray scale data.

15. The display panel driving method of claim 11, wherein the first difference between the first input gray scale data and the first output gray scale data is associated with a previous voltage of the first data signal, the first output gray scale data is associated with a current voltage of the first data signal, the previous voltage of the first data signal is transmitted to a second subpixel of the plurality of subpixels, and the second subpixel is disposed adjacent to the first subpixel.

16. The display panel driving method of claim 11, wherein the display panel driving method is performed by a timing controller.

17. The display panel driving method according to claim 11, wherein the display panel is divided into the plurality of regions, each of the plurality of regions having at least one of the plurality of sub-pixels arranged therein.

18. The display panel driving method according to claim 11, wherein a first size of the first region is different from a second size of a second region of the plurality of regions.

19. The method of claim 11, wherein the first input gray scale data is converted into the first output gray scale data according to a first negative compensation lookup table of at least one negative compensation lookup table corresponding to a negative voltage polarity or a first positive compensation lookup table of at least one positive compensation lookup table corresponding to a positive voltage polarity, wherein one of the at least one negative compensation lookup table and one of the at least one positive compensation lookup table are associated with one of the plurality of regions.

20. The display panel driving method of claim 11, wherein the first difference between the first input gray scale data and the first output gray scale data is associated with a present voltage of the first data signal, and the first output gray scale data is associated with a present voltage of the first data signal.

Background

Different alignment of the liquid crystals (alignment) results in different polarization and refraction effects on the light passing through the liquid crystals. Therefore, light transmittance in the liquid crystal display device can be controlled by adjusting the alignment of the liquid crystal. On the other hand, the liquid crystal must be driven by a sub-pixel voltage with periodically alternating voltage polarity (voltage polarity), i.e., voltage polarity inversion driving, to avoid the liquid crystal from being permanently damaged by deformation and influence caused by ion trapping (ion trapping) and direct current residue (direct current residue). .

In the liquid crystal display device, although the common voltage (common voltage) is located in the middle of the voltage range between the data signal having the negative voltage polarity and the data signal having the positive voltage polarity, for any one sub-pixel (sub), a difference between the sub-pixel voltage having the negative voltage polarity and the common voltage is different from a difference between the sub-pixel voltage having the positive voltage polarity and the common voltage due to a punch-through phenomenon (feed through phenomenon). The sub-pixel voltage of the sub-pixel may be offset from the data signal by a punch-through voltage (feed through voltage). When the sub-pixels are subjected to sub-pixel voltages periodically alternating between positive and negative voltage polarities, but the common voltage is not equal to the average value between the sub-pixel voltage having the positive voltage polarity and the sub-pixel voltage having the negative voltage polarity, flicker occurs and causes display quality to be degraded.

The manufacturing process may result in different punch-through voltages for sub-pixels located at different positions. Since the punch-through voltage varies for different sub-pixels, flicker may be difficult to eliminate. Even if the common voltage of all the sub-pixels is equal to the average value of the sub-pixel voltage having the positive voltage polarity and the sub-pixel voltage having the negative voltage polarity of the sub-pixel located at the center of the liquid crystal display device, the punch-through phenomenon cannot be uniformly eliminated within the liquid crystal display device. The display quality at the other regions may be poor compared to the display quality at the middle region, resulting in non-uniform display quality.

Please refer to fig. 1. Fig. 1 is a schematic view of a current-voltage characteristic curve (current-voltage characteristics curve) of a tft in the prior art. The current-voltage characteristic curve shows the relationship between the drain-to-source current (Ids) flowing through the tft and the gate-to-source voltage (Vgs) across the Ids. As shown in fig. 1, the gate-source voltage Vgs may affect the turn-on of the thin film transistor. In this case, the difference between the sub-pixel voltage having the negative voltage polarity and the common voltage is different from the difference between the sub-pixel voltage having the positive voltage polarity and the common voltage for any one of the sub-pixels in accordance with the on capability of the thin film transistor. The liquid crystal display device may have a line afterimage due to the imbalance of the sub-pixel voltages with respect to the common voltage. Accordingly, there is a need in the art for improvements.

Disclosure of Invention

Therefore, it is a primary objective of the claimed invention to provide a display panel driving method and a display panel driving circuit thereof, which can eliminate flicker or line sticking and ensure high display quality.

The invention discloses a display panel driving circuit which is used for driving a plurality of sub-pixels of a display panel. The display panel driving circuit includes a compensation circuit for converting a first input gray scale data into a first output gray scale data corresponding to a first data signal of a first sub-pixel of the plurality of sub-pixels, wherein the first sub-pixel is located in a first region of the plurality of regions of the display panel, and a first difference between the first input gray scale data and the first output gray scale data is associated with a first voltage polarity of the first data signal or the first region.

The invention also discloses a display panel driving method for driving a plurality of sub-pixels of a display panel. The display panel driving method includes converting a first input gray scale data into a first output gray scale data corresponding to a first data signal of a first sub-pixel of the plurality of sub-pixels, wherein the first sub-pixel is located in a first area of the plurality of areas of the display panel, and a first difference between the first input gray scale data and the first output gray scale data is associated with a first voltage polarity of the first data signal or the first area.

Drawings

Fig. 1 is a schematic diagram of a current-voltage characteristic curve of a tft in the prior art.

Fig. 2 is a schematic diagram of a display module according to an embodiment of the invention.

Fig. 3 is a flowchart of a driving method of an embodiment of the present invention.

FIG. 4 is a timing diagram of polarity signals, gate driving signals, data signals and sub-pixel voltages according to the driving method of the display panel.

Fig. 5 is a diagram illustrating a relationship between a gray scale voltage and a gray scale of a compensated data signal according to an embodiment of the present invention.

Fig. 6 is a schematic diagram of a timing controller according to an embodiment of the invention.

Fig. 7, 9 and 11 are schematic diagrams of sub-pixel voltages of sub-pixels at time intervals according to an embodiment of the invention.

FIG. 8 is a timing diagram of polarity signals, gate drive signals, data signals, and sub-pixel voltages corresponding to FIG. 7.

Fig. 10 is a timing diagram of polarity signals, gate drive signals, data signals, and sub-pixel voltages corresponding to fig. 9.

Fig. 12 is a timing diagram of polarity signals, gate drive signals, data signals, and sub-pixel voltages corresponding to fig. 11.

Wherein the reference numerals are as follows:

10 display module

30 driving method

100 display panel

120 drive circuit

124 gate drive circuit

126 data driving circuit

1221 compensation circuit

122. Timing controller 622 timing controller

300 to 304 steps

CS, CL capacitor

D1-Dm, D1c data signals

DgI1 input gray scale data

DgO1 output gray scale data

DL 1-DLm data line

FP1a, FP2a, FP1b, FP2b frame periods

G1-Gn gate drive signals

GL 1-GLn gate line

LUT lookup table

PX 11-PXnm sub-pixel

Spl polarity signal

TRS transistor

TT1a, TT2a, TT1b, TT2b, TT1c, TT2c, TT1d, TT2d time intervals

VCOM common voltage

Vp1, Vp2, Vn1, Vn2 gray scale voltages

Vpx21, Vpxx1, Vpxx1c, Vpx (n-1)1c sub-pixel voltages

ZN 11-ZNij region

Detailed Description

Certain terms are used throughout the description and claims to refer to particular components, but those skilled in the art will appreciate that a manufacturer may refer to a component by different names, and that throughout the description and claims, a distinction is not made between components by a difference in name but a distinction is made between components in general terms. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. The term "coupled" is intended to mean either an indirect or direct electrical connection. In the following description and in the claims, the terms "first," "second," and the like are used for distinguishing between different elements and not necessarily for limiting as to the priority or order of the elements.

Please refer to fig. 2. Fig. 2 is a schematic diagram of a display module 10 according to an embodiment of the invention. The display module 10 may be a thin-film transistor (TFT) Liquid Crystal Display (LCD) device, which may be applied to electronic products such as laptop calculators and smart phones that can display images. The display module 10 includes a display panel (panel)100 and a driving circuit 120 (also referred to as a display panel driving circuit 120). The display panel 100 includes a plurality of gate lines GL 1-GLn, a plurality of data lines DL 1-DLm, and a plurality of subpixels PX 11-PXnm arranged in an array, wherein m and n are positive integers. Each of the subpixels PX 11-PXnm includes a capacitor CS, CL and a transistor TRS coupled between one of the gate lines GL 1-GLn and one of the data lines DL 1-DLm. Each capacitor CL represents an equivalent capacitor of one of the sub-pixels PX11 to PXnm of the display panel 100. Each capacitor CS is a storage capacitor.

The driving circuit 120 for driving the sub-pixels PX 11-PXnm may include a timing controller 122, a gate driving circuit 124, and a data driving circuit 126. The timing controller 122 is coupled to the gate driving circuit 124 and the data driving circuit 126. The timing controller 122 is used for providing operation signals (e.g., a polarity signal or a plurality of timing signals) to the gate driving circuit 124 and the data driving circuit 126 to control the operations of the gate driving circuit 124 and the data driving circuit 126. The gate driving circuit 124 serves to generate a plurality of gate driving signals G1-Gn according to a part of the operation signals and transmit the gate driving signals G1-Gn to the gate lines GL 1-GLn to enable (enable) the transistors TRS of the sub-pixels PX 11-PXnm on a row-by-row basis. The data driving circuit 126 serves to transmit the data signals D1-Dm to the data lines DL 1-DLm according to the partial operation signals to transmit the data signals D1-Dm to the corresponding sub-pixels PX 11-PXnm.

Referring to fig. 3, fig. 3 is a flowchart of a driving method 30 (also referred to as a display panel driving method 30) according to an embodiment of the invention. Specifically, the operation of the display panel driving circuit 120 to update the voltages of the sub-pixels PX 11-PXnm can be summarized as the driving method 30. The driving method 30 includes the steps of:

step 300: and starting.

Step 302: first input gray level data is converted into first output gray level data corresponding to a first data signal of a first subpixel of the plurality of subpixels, wherein the first subpixel is located in a first region of the plurality of regions of the display panel, and a first difference between the first input gray level data and the first output gray level data is associated with a first voltage polarity or the first region of the first data signal.

Step 304: and (6) ending.

In brief, the timing controller 122 may include a compensation circuit 1221. The compensation circuit 1221 is used to convert the input gray scale data DgI1 into output gray scale data DgO1, the output gray scale data DgO1 corresponding to a data signal (e.g., data signal D1) for a certain sub-pixel (e.g., sub-pixel PX21) located in a certain region (e.g., region ZN11) in the display panel 100. The difference (which may also be referred to as a compensation difference) between input gray level data DgI1 and output gray level data DgO1 is associated with a voltage polarity of a data signal (e.g., data signal D1 having a negative voltage polarity or a positive voltage polarity) or a region thereof (e.g., region ZN 11). In other words, the compensation differences of the sub-pixels PX11 PXnm are a function of the positions of the sub-pixels PX11 PXnm, respectively. The compensation difference value of one sub-pixel (e.g., the sub-pixel PX21) may vary according to whether the data signal (e.g., the data signal D1) of the sub-pixel (e.g., the sub-pixel PX21) has a negative voltage polarity or a positive voltage polarity.

For a detailed operation of the driving method 30 shown in fig. 3, please refer to fig. 4. FIG. 4 is a timing diagram of the polarity signal Spl, the gate driving signal G2, the data signal D1 and the sub-pixel voltage Vpx21 according to the display panel driving method 30 of the embodiment of the invention. In fig. 4, a thick solid line represents the sub-pixel voltage Vpx21, the sub-pixel voltage Vpx21 corresponds to the electric charges accumulated in the sub-pixel PX21, and a thin solid line represents the data signal D1. For convenience of illustration, in fig. 4, the display module 10 shown in fig. 2 is driven by a frame inversion method (frame inversion method), but the invention is not limited thereto. The frame inversion method means that the voltage polarities of the data signals D1-Dm with respect to the common voltage VCOM (hereinafter, referred to as the voltage polarities of the data signals D1-Dm) are inverted every frame (frame) according to the polarity signal Spl. Therefore, the data signals D1-Dm have the same voltage polarity (e.g., positive voltage polarity) in one frame (e.g., in frame period FP1a), while the data signals D1-Dm have the opposite voltage polarity (e.g., negative voltage polarity) in the next frame (e.g., in frame period FP2 a).

Take sub-pixel PX21 as an example. In the frame period FP1a, the data line DL1 transmits a data signal D1 having a gray scale voltage Vp1 from the data driving circuit 126 to the sub-pixels PX11 to PXn 1. The gray scale voltage Vp1 is higher than the common voltage VCOM, so that the voltage polarity of the data signal D1 is positive. When the gate line GL2 is selected by the gate driving signal G2 at the time interval TT1a, the sub-pixels PX21 to PX2m connected to the gate line GL2 are simultaneously turned on. The sub-pixel voltage Vpx21 of the sub-pixel PX21 reaches the gray level voltage Vp1 within the time interval TT1a, but drops to the gray level voltage Vp2 after the time interval TT1a due to the punchthrough phenomenon. Similarly, in the frame period FP2a, the data line DL1 transmits a data signal D1 having a gray scale voltage Vn1 from the data driving circuit 126 to the sub-pixels PX11 to PXn 1. The gray scale voltage Vn1 is lower than the common voltage VCOM so that the voltage polarity of the data signal D1 is negative. When the gate line GL2 is selected by the gate driving signal G2 at the time interval TT2a, the sub-pixels PX21 to PX2m connected to the gate line GL2 are simultaneously turned on. The sub-pixel voltage Vpx21 of the sub-pixel PX21 reaches the gray-level voltage Vn1 within the time interval TT2a, but falls to the gray-level voltage Vn2 after the time interval TT2a due to the punch-through phenomenon.

With respect to the sub-pixel voltage Vpx21 shown in fig. 4, the difference between the gray scale voltage Vn2 having a negative voltage polarity of the sub-pixel PX21 and the common voltage VCOM is equal to or at least approximate to the difference between the gray scale voltage Vp2 having a positive voltage polarity of the sub-pixel PX21 and the common voltage VCOM. When the voltage polarity of the sub-pixel voltage Vpx21 is switched in response to the polarity signal Spl, the sub-pixel voltage Vpx21 is averaged to a voltage level close to the common voltage VCOM. In other words, the waveform of the sub-pixel voltage Vpx21 of the sub-pixel PX21 is symmetrical or balanced with respect to the common voltage VCOM, thereby eliminating flicker. In order to balance the waveforms of the sub-pixel voltages Vpx21, a difference between the gray scale voltage Vn1 of the data signal D1 and the common voltage VCOM is different from a difference between the gray scale voltage Vp1 of the data signal D1 and the common voltage VCOM. Accordingly, the compensation circuit 1221 may convert input gray scale data (which may also be referred to as first input gray scale data) (e.g., input gray scale data DgI1) corresponding to the gray scale voltage Vp2 into output gray scale data (which may also be referred to as first output gray scale data) (e.g., output gray scale data DgO1) of the data signal D1 corresponding to the gray scale voltage Vp 1. In addition, the compensation circuit 1221 may convert (may also be referred to as second input gray scale data) input gray scale data corresponding to the gray scale voltage Vn2 into output gray scale data (may also be referred to as second output gray scale data) of the data signal D1 corresponding to the gray scale voltage Vn 1. In other words, the sub-pixel voltage Vpx21 (e.g., the gray scale voltage Vp2 or Vn2) of the sub-pixel PX21 is offset from the data signal D1 (e.g., the gray scale voltage Vp1 or Vn1) by a voltage associated with a compensation difference corresponding to a positive voltage polarity (which may also be referred to as a first compensation difference) and/or a compensation difference corresponding to a negative voltage polarity (which may also be referred to as a second compensation difference).

The (first) input gray scale data relates to a gray scale corresponding to a data signal to be adjusted (e.g., the uncompensated data signal D1) or a gray scale corresponding to a sub-pixel voltage (e.g., the sub-pixel voltage Vpx21) adjusted by the compensation circuit 1221. The (first) output gray scale data relates to a gray scale corresponding to the data signal adjusted by the compensation circuit 1221 (i.e., the current gray scale voltage of the data signal D1). When the data signal D1 having a positive voltage polarity is changed from the gray scale voltage Vp2 to the gray scale voltage Vp1, the gray scale increases. Accordingly, the (first) input gray scale data is added to the (first) output gray scale data. Likewise, the (second) input gray scale data relates to a gray scale corresponding to the data signal to be adjusted (e.g., the uncompensated data signal D1) or a gray scale corresponding to the sub-pixel voltage (e.g., the sub-pixel voltage Vpx21) adjusted by the compensation circuit 1221. The (second) output gray scale data relates to a gray scale corresponding to the data signal adjusted by the compensation circuit 1221 (i.e., the current gray scale voltage of the data signal D1). When the data signal D1 having a negative voltage polarity is changed from the gray scale voltage Vn2 to the gray scale voltage Vn1, the gray scale falls. Accordingly, the (second) input gray scale data is dropped to the (second) output gray scale data. The first input gray scale data may be equal to the second input gray scale data, however, the first output gray scale data and the second output gray scale data are separately compensated.

That is, since the voltage polarity of the data signal D1 (regarded as a first data signal) corresponding to the gray scale voltage Vp1 of the (first) output gray scale data is opposite to the voltage polarity of the data signal D1 (regarded as a second data signal) corresponding to the gray scale voltage Vn1 of the (second) output gray scale data, the (first) compensation difference between the (first) output gray scale data corresponding to the positive voltage polarity and the (first) input gray scale data is different from the (second) compensation difference between the (second) output gray scale data corresponding to the negative voltage polarity and the (second) input gray scale data. Accordingly, the (first) compensation difference or/and the (second) compensation difference is/are associated with the voltage polarity of the data signal D1, thereby improving the display quality.

It is noted that the driving method 30 is an embodiment of the present invention, and those skilled in the art can make various changes and modifications. For example, the (first) compensation difference corresponding to the positive voltage polarity or/and the (second) compensation difference corresponding to the negative voltage polarity may be equal to a current voltage (which may also be referred to as a current gray scale voltage) of the data signal (i.e., the data signal D1) (i.e., the gray scale voltage Vp1 or Vn 1). This is because the current gray level may affect the punch-through voltage. Therefore, the data signal (e.g., the data signal D1) can be adjusted according to its current voltage (also referred to as current gray scale voltage), so that, after the compensation circuit 1221 compensates, the average value of the sub-pixel voltage (e.g., the gray scale voltage Vp2) of the sub-pixel (e.g., the sub-pixel PX21) with positive voltage polarity and the average value of the sub-pixel voltage (e.g., the gray scale voltage Vn2) of the sub-pixel (e.g., the sub-pixel PX21) with negative voltage polarity at each gray scale level are equal to the average value thereof at another gray scale level (i.e., the average value of the sub-pixel voltage of the sub-pixel with positive voltage polarity and the sub-pixel voltage of the sub-pixel with negative voltage polarity at another gray scale level). Regardless of the gray level at which the sub-pixel (e.g., sub-pixel PX21) is located, the (first) output gray level data or the (second) output gray level data associated with the current (gray level) voltage (e.g., gray level voltage Vp1 or Vn1) of the data signal (e.g., data signal D1) is converted from the (first) input gray level data or the (second) input gray level data according to the current (gray level) voltage (i.e., gray level voltage Vp1 or Vn1) of the data signal (i.e., data signal D1), thereby improving the display quality.

In some embodiments, the (first) compensation difference corresponding to the positive voltage polarity or/and the (second) compensation difference corresponding to the negative voltage polarity may be associated with a region (e.g., region ZN11) in which the sub-pixel (e.g., sub-pixel PX21) is located. Please refer to fig. 2 and fig. 5 together. Fig. 5 is a diagram illustrating a relationship between a gray scale voltage and a gray scale of a compensated data signal according to an embodiment of the present invention. As shown in fig. 2, the display panel 100 may be divided into a plurality of regions ZN11 to ZNij, where i and j are positive integers. Each of the regions ZN 11-ZNij has at least one of the sub-pixels PX 11-PXnm arranged therein. For example, four sub-pixels PX11 to PX22 may be arranged in the region ZN 11. The size of one zone (e.g., zone ZN11) may be the same as or different from the size of another zone (e.g., zone ZNij). For example, in some embodiments, there may be only one subpixel PXnm in region ZNij.

As shown in FIG. 2, the capacitors CS and CL of one of the sub-pixels PX 11-PXnm may be coupled between its sub-pixel voltage and the common voltage VCOM of the display module 10. As shown in FIG. 5, there may be only one common voltage, and all the sub-pixels PX 11-PXnm are applied with the same common voltage VCOM. In some embodiments, the common voltage VCOM of all the sub-pixels is equal to an average of the sub-pixel voltage having the positive voltage polarity and the sub-pixel voltage having the negative voltage polarity of the sub-pixel located at the center among the sub-pixels PX11 to PXnm of the display panel 100. In some embodiments, the common voltage VCOM of all the sub-pixels is equal to an average of the sub-pixel voltage having the positive voltage polarity and the sub-pixel voltage having the negative voltage polarity of the sub-pixels located in a region (e.g., region ZN11) near the center of the display panel 100. In the case where different common voltages are not configured for different sub-pixels PX11 to PXnm of different regions ZN11 to ZNij of the display panel 100, there is no need to configure an additional common voltage component. Further, a circuit or wiring can be simplified and an area thereof can be minimized.

If the waveforms of the sub-pixel voltages of all the sub-pixels PX 11-PXnm are to be symmetrical or balanced with respect to the common voltage VCOM, the compensation circuit 1221 must convert input gray scale data (e.g., input gray scale data DgI1) corresponding to the sub-pixel voltages of the sub-pixels PX 11-PXnm into output gray scale data (e.g., output gray scale data DgO1) corresponding to the data signals of all the sub-pixels PX 11-PXnm. Since the manufacturing process may cause the punch-through voltages of the sub-pixels PX11 to PXnm to be different from each other, the (first) compensation difference corresponding to the positive voltage polarity or/and the (second) compensation difference corresponding to the negative voltage polarity may be associated with the regions ZN11 to ZNij where the sub-pixels PX11 to PXnm are located.

For example, if the region ZNkc is located at (or near) the center of the display panel 100, a (first) compensation difference corresponding to a positive voltage polarity or/and a (second) compensation difference corresponding to a negative voltage polarity may be equal to or close to zero at the region ZNkc. This is because the common voltage VCOM of all the sub-pixels PX11 to PXnm is set to the middle of the sub-pixel voltage having the positive voltage polarity and the sub-pixel voltage having the negative voltage polarity of the sub-pixel in the region ZNkc. In fig. 5, a dotted line represents a gamma curve of gray level versus gray level voltage at the region ZNkc after compensation. According to fig. 5, the gamma curve of the region ZNkc located near the center of the display panel 100 is symmetrical or balanced with respect to a virtual straight line (virtual straight line) of the common voltage VCOM, which is parallel to the x-axis and spaced apart from the x-axis by a distance (i.e., the common voltage VCOM). It is not necessary to adjust the gray scale voltage of the data line near the center of the display panel 100. Therefore, the compensation circuit 1221 may not convert the (first) input gray scale data into the (first) output gray scale data.

On the other hand, if the regions (e.g., the region ZN11 or ZNij) are near the four outermost sides of the display panel 100, the (first) compensation difference corresponding to the positive voltage polarity or/and the (second) compensation difference corresponding to the negative voltage polarity may not be zero. In fig. 5, thick and thin solid lines respectively represent gamma curves between the compensated gray scale and gray scale voltages in the regions ZN11 and ZNij. Referring to fig. 5, for the outermost regions ZN11 and ZNij adjacent to the display panel 100, the gamma curve is asymmetric with respect to a virtual straight line of the common voltage VCOM. The gray scale voltage of the data line far from the center of the display panel 100 must be adjusted. Further, the gray level corresponding to the positive voltage polarity in region ZN11 is higher than the gray level corresponding to the positive voltage polarity in region ZNij, and the gray level corresponding to the negative voltage polarity in region ZN11 is lower than the gray level corresponding to the negative voltage polarity in region ZNij. Accordingly, the (first) compensation difference corresponding to the positive voltage polarity or/and the (second) compensation difference corresponding to the negative voltage polarity may be associated with the region where the sub-pixel is located, thereby improving display quality. The (first) compensation difference corresponding to the positive voltage polarity and the (second) compensation difference corresponding to the negative voltage polarity are set independently and differently, respectively.

In some embodiments, the timing controller 122 is adapted to adjust the compensation process of the compensation circuit 1221. Please refer to fig. 6, table 1 and table 2. Fig. 6 is a schematic diagram of a timing controller 622 according to an embodiment of the invention. Table 1 and table 2 list possible elements of the look-up table LUT, respectively. The timing controller 622 of fig. 6 is similar to the timing controller 122 of fig. 2, so the same components are denoted by the same symbols and are not described again. Unlike the timing controller 122, the timing controller 622 also includes a look-up table (LUT). The look-up table LUT stores data related to compensation from the (first) input gray scale data or the (second) input gray scale data to the (first) output gray scale data or the (second) output gray scale data. The data may be stored in a digital (digital) form (or analog) form). In some embodiments, the timing controller 622 may include a memory circuit such as a Read Only Memory (ROM) to store the look-up table LUT.

(Table 1)

Inputting gray scale data	0	1	…	254	255
						Compensating for differences	CDF(0)	CDF(1)	…	CDF(254)	CDF(255)

(Table 2)

Inputting gray scale data	0-31	32-63	…	192-223	224-255
						Compensating for differences	CDR(0)	CDR(32)	…	CDR(192)	CDR(224)

In some embodiments, the look-up table LUT may store a (first) compensation difference for a data signal having a positive voltage polarity (e.g., data signal D1) and a (second) compensation difference for a data signal having a negative voltage polarity (i.e., data signal D1). Accordingly, the exact values of the compensation differences CDF (0) to CDF (255) listed in table 1 and the exact values of the compensation differences CDF (0) to CDF (224) listed in table 2 may be determined according to the voltage polarity. In some embodiments, the look-up table LUT may store a (first) compensation difference value of the data signal (i.e., the data signal D1) having the positive voltage polarity but different gray levels, and store a (second) compensation difference value of the data signal (i.e., the data signal D1) having the negative voltage polarity but different gray levels. Accordingly, the exact values of the compensation differences CDF (0) -CDF (255) listed in row 2 of table 1 can be determined from the input gray scale data listed in row 1 of table 1. The gray scale level can be 256 levels (gradation) for rendering an image by the display module 10, but is not limited thereto. In some embodiments, the lookup table LUT may store (first) compensation differences for data signals (i.e., data signal D1) having positive voltage polarity but different gray scale ranges (e.g., 0-31, 32-63,. -, 224-. Accordingly, the exact values of the compensation differences CDF (0) -CDF (224) listed in row 2 of table 2 can be determined according to the gray scale range of the input gray scale data listed in row 1 of table 2.

In some embodiments, the look-up table LUT may store the (first) compensation difference values and the (second) compensation difference values for all of the zones ZN11 ZNij. Accordingly, the exact values of the compensation differences CDF (0) to CDF (255) listed in table 1 and the exact values of the compensation differences CDF (0) to CDF (224) listed in table 2 may be determined according to the region (e.g., region ZN11) in which the sub-pixel (e.g., sub-pixel PX21) is located. In some embodiments, the timing controller 122 can respectively identify which regions each of the sub-pixels PX 11-PXnm is located in and which voltage polarity each of the sub-pixels PX 11-PXnm corresponds to according to the operation signals (such as the polarity signal Spl and the timing signal). In some embodiments, the (first) input grey level data is converted into the (first) output grey level data according to one of the positive compensation look-up tables for positive voltage polarity in the look-up table LUT. The (second) input grey scale data is converted into the (second) output grey scale data according to one of the negative compensation look-up tables for negative voltage polarities in the look-up table LUT. One of the negative compensation lookup tables and one of the positive compensation lookup tables are associated with one of the zones ZN 11-ZNij.

When the (first) input gray scale data or the (second) input gray scale data is converted into the (first) output gray scale data or the (second) output gray scale data according to the look-up table LUT, the flicker disappears.

To eliminate line ghosting, in some embodiments, the look-up table LUT may store a (first) compensation difference and a (second) compensation difference corresponding to a previous input gray level data. In other words, the (first) compensation difference corresponding to the positive voltage polarity or/and the (second) compensation difference corresponding to the negative voltage polarity may be associated with a previous voltage (which may also be referred to as a previous gray scale voltage) of the data signal (e.g., data signal D1). Please refer to table 3 and table 4. Table 3 and table 4 list possible elements of the look-up table LUT, respectively. The exact values of the compensation differences CDF (0,0) -CDF (255) listed in table 3 can be determined from the next input gray scale data listed in the top row of table 3 and the previous input gray scale data listed in the left most column of table 3. Compensation differences CDF (0,0) E

The exact value of the CDFs (224) may be determined based on the gray scale range of the next input gray scale data listed in the top row of table 4 and the gray scale range of the previous input gray scale data listed in the left most column of table 4. As described above, the exact values of the compensation differences CDF (0,0) to CDF (255) listed in table 3 and the exact values of the compensation differences CDF (0,0) to CDF (224) listed in table 2 may be determined according to the voltage polarity.

(Table 3)

(Table 4)

The exact values of the compensation differences CDF (0,0) to CDF (255) listed in table 3 and the exact values of the compensation differences CDF (0,0) to CDF (224) listed in table 4 may be determined according to the region (e.g., region ZN11) in which the sub-pixel (e.g., sub-pixel PX21) is located. Specifically, please refer to fig. 7 to 12. Fig. 7, 9 and 11 are schematic diagrams of the voltages of the sub-pixels PX 11-PXnm respectively at the time intervals TT1b, TT1c and TT1d (or the time intervals TT2b, TT2c and TT2d) according to the embodiment of the invention. In fig. 7, 9 and 11, different diagonal stripe patterns represent different sub-pixel voltages. Fig. 8 is a timing diagram corresponding to the polarity signal Spl, the gate driving signal G2, the data signal D1, and the sub-pixel voltage Vpx21 of fig. 7. Fig. 10 is a timing diagram corresponding to the polarity signal Spl, the gate driving signal Gx, the data signals D1, D1c, and the sub-pixel voltages Vpxx1, Vpxx1c of fig. 9. FIG. 12 is a timing diagram of the polarity signal Spl, the gate drive signal Gn-1, the data signals D1, D1c, and the sub-pixel voltages Vpx (n-1)1, Vpx (n-1)1c corresponding to FIG. 11. In fig. 8, 10, and 12, a thin solid line indicates the data signal D1, a thin broken line indicates the compensated data signal D1c, and a thick solid line indicates the sub-pixel voltages Vpx21, Vpxx1, and Vpx (n-1)1, where the sub-pixel voltages Vpx21, Vpxx1, and Vpx (n-1)1 correspond to the charges accumulated in the sub-pixels PX21, PXx1, and PX (n-1)1, respectively. The thick dotted lines indicate sub-pixel voltages Vpxx1c and Vpx (n-1)1c, which correspond to the charges accumulated in the compensated sub-pixels PX21, PXx1 and PX (n-1)1, respectively, and Vpxx1c and Vpx (n-1)1 c.

As shown in fig. 7 and 8, the sub-pixels PX11 to PXnm are sequentially activated one row at a time in the frame period FP1b by sequentially turning on the gate lines GL1 to GLn. The data lines DL1 to DLm transmit data signals D1 to Dm of the gray scale voltage Vpl from the data driving circuit 126 to the sub-pixels PX11 to PX1m before a time interval TT1b within the frame period FP1 b. The data signals D1 to Dm transmitted to the sub-pixels PX21 to PX2m adjacent to the sub-pixels PX11 to PX1m are increased from the gray level voltage Vpl (which may also be referred to as a previous voltage) to the gray level voltage Vph (which may also be referred to as a current voltage) at a time interval TT1b within the frame period FP1b, for example, the sub-pixels are changed from black to white. After a time interval TT1b within the frame period FP1b, the data lines DL1 to DLm transmit data signals D1 to Dm of the gray scale voltage Vph to the subpixels PX31 to PXnm. Since the sub-pixel voltage Vpx21 of the sub-pixel PX21 reaches the gray-level voltage Vph at the time interval TT1b and makes the luminance of the sub-pixel PX21 as intended, it is not necessary to compensate the sub-pixel voltage Vpx 21. That is, with respect to the region ZN11 where the subpixel PX21 is located and the previous gray scale voltage Vpl of the data signal D1, the (first) compensation difference between the (first) input gray scale data corresponding to the positive voltage polarity and the (first) output gray scale data corresponding to the current gray scale voltage Vph of the data signal D1 may be equal to or close to zero. Alternatively, the compensation circuit 1221 may not convert the (first) input gray scale data into the (first) output gray scale data.

Similarly, at time interval TT2b within the frame period FP2b, the data signals D1-Dm sent to the subpixels PX 21-PX 2m decrease from the gray scale voltage Vnl (also referred to as the previous voltage) for the adjacent subpixels PX 11-PX 1m to the gray scale voltage Vnh (also referred to as the current voltage), e.g., the subpixels transition from black to white. Since the sub-pixel voltage Vpx21 of the sub-pixel PX21 reaches the gray-level voltage Vnh at the time interval TT2b and makes the luminance of the sub-pixel PX21 as intended, it is not necessary to compensate the sub-pixel voltage Vpx 21. That is, as for the region ZN11 where the sub-pixel PX21 is located and the previous gray-scale voltage Vnl of the data signal D1, the (second) compensation difference between the (second) input gray-scale data corresponding to the negative voltage polarity and the (second) output gray-scale data corresponding to the current gray-scale voltage Vnh of the data signal D1 may be equal to or close to zero. Alternatively, the compensation circuit 1221 may not convert the (second) input gray scale data into the (second) output gray scale data.

As shown in fig. 9 and 10, the sub-pixels PX11 to PXnm are sequentially activated one row at a time in the frame period FP1b by sequentially turning on the gate lines GL1 to GLn. The data lines DL1 to DLm transmit data signals D1 to Dm of the gray scale voltages Vpl from the data driving circuit 126 to the sub-pixels PX11 to PX (x-1) m before a time interval TT1c within the frame period FP1 b. The data signals D1 to Dm transmitted to the sub-pixels PXx1 to PXxm adjacent to the sub-pixels PX11 to PX (x-1) m are increased from the gray level voltage Vpl (which may also be referred to as a previous voltage) to the gray level voltage Vph (which may also be referred to as a current voltage) at the time interval TT1c within the frame period FP1 b. After a time interval TT1c within the frame period FP1b, the data lines DL1 to DLm transmit data signals D1 to Dm of the gray scale voltage Vph to the sub-pixels PX (x +1)1 to PXnm. Since the sub-pixel voltage Vpxx1 of the sub-pixel PXx1 reaches the gray-scale voltage Vph at the time interval TT1c and makes the luminance of the sub-pixel PXx1 as expected, the sub-pixel voltage Vpxx1 does not need to be compensated. That is, as for the region ZNk1 where the sub-pixel PXx1 is located and the previous gray scale voltage Vpl of the data signal D1, the (first) compensation difference between the (first) input gray scale data corresponding to the positive voltage polarity and the (first) output gray scale data corresponding to the current gray scale voltage Vph of the data signal D1 may be equal to or close to zero. Alternatively, the compensation circuit 1221 may not convert the (first) input gray scale data into the (first) output gray scale data.

On the other hand, at the time interval TT2c within the frame period FP2b, the data signals D1 to Dm transmitted to the sub-pixels PXx1 to PXxm are reduced from the gray-scale voltage Vnl (which may also be referred to as a previous voltage) for the adjacent sub-pixels PX11 to PX (x-1) m to one gray-scale voltage (which may also be referred to as a current voltage) larger than the gray-scale voltage Vnh. The sub-pixels PXx1 to PXxm are disposed farther from the data driving circuit 126 than the sub-pixels PX21 to PX2 m. As shown in fig. 10, the sub-pixel voltage Vpxx1 of the sub-pixel PXx1 does not reach the gray scale voltage Vnh at the time interval TT2c and cannot achieve the desired brightness, so the sub-pixel voltage Vpxx1 and the data signal D1 need to be compensated, and the sub-pixel voltage Vpxx1 and the data signal D1 are adjusted to the sub-pixel voltage Vpxx1c and the data signal D1c, respectively. As such, the waveform of the sub-pixel voltage Vpxx1 of the sub-pixel PXx1 with positive voltage polarity and the waveform of the sub-pixel voltage Vpxx1c of the sub-pixel PXx1 with negative voltage polarity are symmetrical or balanced with respect to the common voltage VCOM. That is, as for the region ZNk1 where the sub-pixel PXx1 is located and the previous gray scale level voltage Vnl of the data signal D1, the (second) compensation difference between the (second) input gray scale level data corresponding to the negative voltage polarity and the (second) output gray scale level data corresponding to the current gray scale level voltage Vnh of the data signal D1 may be non-zero. The compensation circuit 1221 converts the (second) input gray scale data into the (second) output gray scale data according to the region ZNk1 where the sub-pixel PXx1 is located, the voltage polarity of the data signal D1, and the previous gray scale voltage Vnl of the data signal D1 to remove the line afterimage.

As shown in fig. 11 and 12, the sub-pixels PX11 to PXnm are sequentially activated one row at a time in the frame period FP1b by sequentially turning on the gate lines GL1 to GLn. The data lines DL1 to DLm transmit data signals D1 to Dm of the gray scale voltages Vpl from the data driving circuit 126 to the sub-pixels PX11 to PX (n-2) m before a time interval TT1D within the frame period FP1 b. The data signals D1-Dm transmitted to the sub-pixels PX (n-1)1-PX (n-1) m adjacent to the sub-pixels PX 11-PX (n-2) m are increased from the gray-level voltage Vpl (which may also be referred to as a previous voltage) to the gray-level voltage Vph (which may also be referred to as a present voltage) at the time interval TT1D within the frame period FP1 b. After a time interval TT1D within the frame period FP1b, the data lines DL1 to DLm transmit data signals D1 to Dm of the gray scale voltage Vph to the subpixels PXn1 to PXnm. Since the sub-pixel voltage Vpx (n-1)1 of the sub-pixel PX (n-1)1 reaches the gray-scale voltage Vph at the time interval TT1d and makes the luminance of the sub-pixel PX (n-1)1 as intended, the sub-pixel voltage Vpx (n-1)1 does not need to be compensated. That is, with respect to the region ZNi1 where the sub-pixel PX (n-1)1 is located and the previous gray-level voltage Vpl of the data signal D1, the (first) compensation difference between the (first) input gray-level data corresponding to the positive voltage polarity and the (first) output gray-level data corresponding to the current gray-level voltage Vph of the data signal D1 may be equal to or close to zero. Alternatively, the compensation circuit 1221 may not convert the (first) input gray scale data into the (first) output gray scale data.

On the other hand, at the time interval TT2D within the frame period FP2b, the data signals D1 to Dm transmitted to the sub-pixels PX (n-1)1 to PX (n-1) m are reduced from the gray-level voltage Vnl (which may also be referred to as a previous voltage) for the adjacent sub-pixels PX11 to PX (n-2) m to one gray-level voltage (which may also be referred to as a present voltage) much larger than the gray-level voltage Vnh. The sub-pixels PX (n-1)1-PX (n-1) m are disposed farther from the data driving circuit 126 than the sub-pixels PX 21-PX 2 m. As shown in fig. 12, the sub-pixel voltage Vpx (n-1)1 of the sub-pixel PX (n-1)1 does not reach the gray scale voltage Vnh at the time interval TT2D and cannot achieve the desired luminance, so the sub-pixel voltage Vpx (n-1)1 and the data signal D1 need to be compensated, and the sub-pixel voltage Vpx (n-1)1 and the data signal D1 are adjusted to the sub-pixel voltage Vpx (n-1)1c and the data signal D1c, respectively. In this way, the waveform of the sub-pixel voltage Vpx (n-1)1 having the positive voltage polarity of the sub-pixel PX (n-1)1 and the waveform of the sub-pixel voltage Vpx (n-1)1c having the negative voltage polarity of the sub-pixel PX (n-1)1 are symmetrical or balanced with respect to the common voltage VCOM. That is, with respect to the region ZNi1 where the sub-pixel PX (n-1)1 is located and the previous gray scale voltage Vnl of the data signal D1, the (second) compensation difference between the (second) input gray scale data corresponding to the negative voltage polarity and the (second) output gray scale data corresponding to the current gray scale voltage Vnh of the data signal D1 may be much larger than zero. The compensation circuit 1221 converts the (second) input gray scale data into the (second) output gray scale data to eliminate the line residual image according to the region ZNi1 where the sub-pixel PX (n-1)1 is located, the voltage polarity of the data signal D1, and the previous gray scale voltage Vnl of the data signal D1.

In summary, the compensation difference for a sub-pixel may be a function of the position of the sub-pixel. The compensation difference of the sub-pixel may be affected by the current (gray level) voltage of the data signal of the sub-pixel. To eliminate flicker, the compensation difference value of the sub-pixel may vary depending on whether the data signal of the sub-pixel has a negative voltage polarity or a positive voltage polarity. The compensated difference value of the sub-pixel may be associated with a previous (gray scale) voltage of the data signal of another sub-pixel adjacent thereto to remove a line afterimage.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.