1. A method for increasing the speed of a data channel is characterized by comprising the following steps:

receiving data to be transmitted;

selecting data with corresponding length from the data to be transmitted according to a data selection signal at a first clock rising edge in one period of a first clock signal, and transmitting the data to a data input end of a trigger;

transmitting the data of the corresponding length from the data input end of the flip-flop to the data output end of the flip-flop for output on a second clock rising edge in one period of a second clock signal;

converting the data of the corresponding length from parallel transmission to serial transmission;

transmitting the data of the corresponding length transmitted in series to the data output interface at a second clock falling edge in one period of the first clock signal;

at the rising edge of a third clock in one period of the first clock signal, serially outputting the data with the corresponding length through a data output interface;

the first clock signal and the second clock signal have the same clock period, and the second clock signal is the clock signal obtained by delaying the first clock signal for a set time.

2. The method according to claim 1, wherein the first clock rising edge in one period of the first clock signal selects data with a corresponding length from the data to be transmitted according to the data selection signal, and transmits the data to the data input terminal of the flip-flop, and the specific process is as follows: and at the first clock rising edge in one period of the first clock signal, the data selector generates a data selection signal, selects data with corresponding length from the data to be transmitted, and transmits the data with corresponding length to the data input end of the trigger.

3. The method for increasing data channel speed according to claim 2, wherein the data selector is a 2-from-1 data selector, a 4-from-1 data selector or an 8-from-1 data selector.

4. The method of claim 1, wherein the flip-flop is a class D flip-flop.

5. The method of claim 1, wherein the data of the corresponding length is converted from parallel transmission to serial transmission by a shift register.

6. The method for increasing data channel speed according to claim 1, wherein the data input interface and the data output interface are implemented by IO interfaces.

7. The method according to claim 1, wherein the second clock signal is a clock signal delayed by a set time from the first clock signal, and the set time is specifically set as follows: the second clock rising edge in one period of the second clock signal needs to be set after the data of the corresponding length is transmitted to the data input end of the D-type flip-flop and before the data of the corresponding length transmitted in series is transmitted to the data output interface.

8. An apparatus for increasing the speed of a data channel, comprising:

the data receiving module is used for receiving data needing to be transmitted;

the data selection module selects data with corresponding length from the data to be transmitted according to the data selection signal at a first clock rising edge in one period of the first clock signal, and transmits the data to the data input end of the trigger;

the data transmission module transmits the data with the corresponding length from the data input end of the trigger to the data output end of the trigger on the rising edge of a second clock in one period of a second clock signal;

the conversion module is used for converting the data with the corresponding length from parallel transmission to serial transmission;

the interface transmission module is used for transmitting the data with the corresponding length which is transmitted in series to the data output interface at the falling edge of a second clock in one period of the first clock signal;

the data output module is used for outputting the data with the corresponding length in series through the data output interface at the rising edge of a third clock in one period of the first clock signal;

and the clock module generates the first clock signal and a second clock signal, wherein the second clock signal is the clock signal obtained by delaying the first clock signal for a set time.

9. A storage medium having stored thereon a computer program which, when run on a computer, causes the computer to perform the method of any one of claims 1 to 7.

10. A terminal, characterized in that it comprises a processor and a memory, in which a computer program is stored, the processor being adapted to carry out the method of any one of claims 1 to 7 by calling the computer program stored in the memory.

Background

A common data stream channel is shown in fig. 1, and a data stream timing sequence is shown in fig. 2. Generating a byte sel signal on the first clock rising edge, selecting 1 from 4byte sel signals, selecting 1byte data, and transmitting the data to the input end of the DFF; the DFF transfers the data from the input end to the output end at the rising edge of the second clock, and converts the parallel data into serial data through a series of shift register operations. Transmitting the data at the output end of the DFF to IO at the falling edge of the second clock; and on the rising edge of the third clock, the user samples data, and the data are output in series.

To ensure that the user and the internal DFF sample the correct data, the data after byte select is transferred to the input of the DFF before the rising edge of the second clock. Due to the complexity of the internal circuitry, there is a delay from the byte sel signal generation to the data update and transfer to the DFF input, which limits the maximum speed of data transfer. Under the condition of faster clock requirement, this delay can easily cause the DFF to sample wrong data (the DFF may collect data of the previous byte), as shown in fig. 3. And in order to ensure the accuracy of data acquisition, only the transmission speed of the data can be sacrificed.

Therefore, the prior art still needs to be improved and developed.

Disclosure of Invention

The present invention is directed to a method, an apparatus, a storage medium, and a terminal for increasing a data channel speed, and aims to solve one or more problems in the prior art.

The technical scheme of the invention is as follows: the technical scheme provides a method for increasing the speed of a data channel, which specifically comprises the following steps:

receiving data to be transmitted;

selecting data with corresponding length from the data to be transmitted according to a data selection signal at a first clock rising edge in one period of a first clock signal, and transmitting the data to a data input end of a trigger;

transmitting the data of the corresponding length from the data input end of the flip-flop to the data output end of the flip-flop for output on a second clock rising edge in one period of a second clock signal;

converting the data of the corresponding length from parallel transmission to serial transmission;

transmitting the data of the corresponding length transmitted in series to the data output interface at a second clock falling edge in one period of the first clock signal;

at the rising edge of a third clock in one period of the first clock signal, serially outputting the data with the corresponding length through a data output interface;

the first clock signal and the second clock signal have the same clock period, and the second clock signal is the clock signal obtained by delaying the first clock signal for a set time.

Further, the first clock rising edge in one period of the first clock signal selects data of a corresponding length from the data to be transmitted according to the data selection signal, and transmits the data to the data input end of the flip-flop, which specifically includes the following steps: and at the first clock rising edge in one period of the first clock signal, the data selector generates a data selection signal, selects data with corresponding length from the data to be transmitted, and transmits the data with corresponding length to the data input end of the trigger.

Further, the data selector adopts a 2-to-1 data selector, a 4-to-1 data selector or an 8-to-1 data selector.

Further, the trigger adopts a D-type trigger.

Further, the data of the corresponding length is converted from parallel transmission to serial transmission by a shift register.

Further, the data input interface and the data output interface are realized by adopting an IO interface.

Further, the second clock signal is a clock signal obtained by delaying the first clock signal for a set time, and the setting of the delay set time is specifically as follows: the second clock rising edge in one period of the second clock signal needs to be set after the data of the corresponding length is transmitted to the data input end of the D-type flip-flop and before the data of the corresponding length transmitted in series is transmitted to the data output interface.

This technical scheme still provides a device that promotes data channel speed, includes:

the data receiving module is used for receiving data needing to be transmitted;

the data selection module selects data with corresponding length from the data to be transmitted according to the data selection signal at a first clock rising edge in one period of the first clock signal, and transmits the data to the data input end of the trigger;

the data transmission module transmits the data with the corresponding length from the data input end of the trigger to the data output end of the trigger on the rising edge of a second clock in one period of a second clock signal;

the conversion module is used for converting the data with the corresponding length from parallel transmission to serial transmission;

the interface transmission module is used for transmitting the data with the corresponding length which is transmitted in series to the data output interface at the falling edge of a second clock in one period of the first clock signal;

the data output module is used for outputting the data with the corresponding length in series through the data output interface at the rising edge of a third clock in one period of the first clock signal;

and the clock module generates the first clock signal and a second clock signal, wherein the second clock signal is the clock signal obtained by delaying the first clock signal for a set time.

The present invention also provides a storage medium, in which a computer program is stored, and when the computer program runs on a computer, the computer is caused to execute any one of the methods described above.

The technical solution also provides a terminal, which includes a processor and a memory, wherein the memory stores a computer program, and the processor is used for executing any one of the methods by calling the computer program stored in the memory.

According to the technical scheme, the second clock signal is obtained after the first clock signal is delayed for the set time, the D-type trigger is operated by the second clock signal in the data transmission process, and the first clock signal is still used in other operations of data transmission, so that the data can be adapted to any required transmission speed, and the problem that the acquired data are wrong due to the delay existing from the selection of the data to the data input end of the D-type trigger is solved.

Drawings

Fig. 1 is a schematic diagram of a process of transmitting data streams in a channel in the prior art.

Fig. 2 is a timing diagram illustrating data stream transmission in the prior art.

Fig. 3 is a diagram illustrating DFF sampling to erroneous data under conditions of faster clock requirements in the prior art.

FIG. 4 is a flow chart of the steps of the method for increasing the speed of a data channel according to the present invention.

FIG. 5 is a schematic diagram of an apparatus for increasing the speed of a data channel according to the present invention.

Fig. 6 is a schematic diagram of a terminal in the present invention.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

As shown in fig. 4, a method for increasing the speed of a data channel specifically includes the following steps:

s1: and receiving data to be transmitted.

The length of the data to be transmitted may be set according to actual needs, such as 32 bytes of data, 64 bytes of data, and the like.

The data to be transmitted is received through the data input interface.

S2: and selecting data with corresponding length from the data to be transmitted according to the data selection signal at the rising edge of the first clock in one period of the first clock signal, and transmitting the data to the data input end of the D-type trigger.

The data selector generates a data selection signal at a first clock rising edge in a period of a first clock signal, selects data with a corresponding length from the data to be transmitted, and transmits the data with the corresponding length to the data input end of the D-type trigger.

Correspondingly, the data selector can adopt different types according to actual needs, such as a 2-to-1 data selector, a 4-to-1 data selector and an 8-to-1 data selector.

S3: and transmitting the data with the corresponding length from the data input end of the D-type trigger to the data output end of the D-type trigger at the second clock rising edge in one period of a second clock signal.

S4: and converting the data with the corresponding length from parallel transmission to serial transmission.

The D-type flip-flop (the D-type flip-flop is an information storage device with a memory function and two stable states, is the most basic logic unit which forms a plurality of sequential circuits, and is also an important unit circuit in a digital logic circuit) transmits the data with the corresponding length from a data input end to a data output end at the second clock rising edge in one period of a second clock signal, the data with the corresponding length enters a shift register, and the shift register converts the data with the corresponding length from parallel transmission to serial transmission.

S5: and transmitting the data with the corresponding length transmitted in series to the data output interface at a second clock falling edge in one period of the first clock signal.

The data input interface and the data output interface are realized by adopting IO interfaces.

S6: and at the third clock rising edge in one period of the first clock signal, serially outputting the data with the corresponding length through a data output interface.

Wherein, the one period refers to one clock period.

Specifically, the first clock signal and the second clock signal are clock signals generated by the same clock, so that the first clock signal and the second clock signal have the same clock period, and the second clock signal is a clock signal obtained by delaying the first clock signal by a set time: namely, the clock firstly generates a first clock signal, and then generates a second clock signal after delaying for a set time.

The second clock signal is a clock signal obtained by delaying the first clock signal for a set time, and the setting of the delayed set time is as follows: the second clock rising edge in one period of the second clock signal (c) needs to be set after the data of the corresponding length is transmitted to the data input terminal of the class D flip-flop (the time point after the data of the corresponding length is transmitted to the data input terminal of the class D flip-flop can be determined by calculating the time length during which the data of the corresponding length is transmitted from the data selector to the data input terminal of the class D flip-flop), and before the data of the corresponding length that is serially transmitted is transmitted to the data output interface (i.e., before the second clock falling edge in one period of the first clock signal (c)), the second clock rising edge in one period of the second clock signal (c) can be set to any time point in this period.

The method for increasing the speed of the data channel described above is described by referring to the following embodiments:

the Sclk _ fast _ delay (i.e., the second clock signal) is a clock signal delayed by the Sclk _ fast (i.e., the first clock signal) for a period of time, the Sclk _ fast _ delay clock is only transmitted to the DFF (i.e., the class D flip-flop) for use, and the Sclk _ fast is used for the rest operations (e.g., data selection, transmission of serially transmitted data to the data output interface, output of data through the IO interface, etc.).

In the technical scheme, the data flow time sequence is as follows: generating a byte sel signal on the rising edge of a first clock (Sclk _ fast), selecting 1 from the byte sel signal 4, selecting 1byte data (selecting 1byte (namely 8 bit) data from the 4 bytes), and transmitting the data to an input end (namely a D-type trigger); the DFF transmits the data of the input end to the output end at the rising edge of a second clock (Sclk _ fast _ delay), and converts the parallel data into serial data through a series of shift register operations; transmitting the serial data to the IO interface at the falling edge of the second clock (Sclk _ fast); and at the rising edge (r) of the third clock (Sclk _ fast), the user samples data, and the data are serially output through the IO interface.

As shown in fig. 5, an apparatus for increasing a speed of a data channel includes:

a data receiving module 101, which receives data to be transmitted;

the data selection module 102 selects data with a corresponding length from the data to be transmitted according to a data selection signal at a first clock rising edge in one period of a first clock signal, and transmits the data to a data input end of the flip-flop;

the data transmission module 103 is used for transmitting the data with the corresponding length from the data input end of the flip-flop to the data output end of the flip-flop on a second clock rising edge in one period of a second clock signal;

the conversion module 104 is used for converting the data with the corresponding length from parallel transmission to serial transmission;

the interface transmission module 105 transmits the data with the corresponding length transmitted in series to the data output interface at a second clock falling edge in one period of the first clock signal;

the data output module 106 is configured to output the data with the corresponding length serially through the data output interface on a third clock rising edge in one period of the first clock signal;

the clock module 107 generates the first clock signal and a second clock signal, where the second clock signal is a clock signal obtained by delaying the first clock signal by a set time.

Referring to fig. 6, an embodiment of the present invention further provides a terminal. As shown, the terminal 300 includes a processor 301 and a memory 302. The processor 301 is electrically connected to the memory 302. The processor 301 is a control center of the terminal 300, connects various parts of the entire terminal using various interfaces and lines, and performs various functions of the terminal and processes data by running or calling a computer program stored in the memory 302 and calling data stored in the memory 302, thereby performing overall monitoring of the terminal 300.

In this embodiment, the processor 301 in the terminal 300 loads instructions corresponding to one or more processes of the computer program into the memory 302 according to the following steps, and the processor 301 runs the computer program stored in the memory 302, so as to implement various functions: receiving data to be transmitted; selecting data with corresponding length from the data to be transmitted according to a data selection signal at a first clock rising edge in one period of a first clock signal, and transmitting the data to a data input end of a trigger; transmitting the data of the corresponding length from the data input end of the flip-flop to the data output end of the flip-flop for output on a second clock rising edge in one period of a second clock signal; converting the data of the corresponding length from parallel transmission to serial transmission; transmitting the data of the corresponding length transmitted in series to the data output interface at a second clock falling edge in one period of the first clock signal; at the rising edge of a third clock in one period of the first clock signal, serially outputting the data with the corresponding length through a data output interface; the first clock signal and the second clock signal have the same clock period, and the second clock signal is the clock signal obtained by delaying the first clock signal for a set time.

Memory 302 may be used to store computer programs and data. The memory 302 stores computer programs containing instructions executable in the processor. The computer program may constitute various functional modules. The processor 301 executes various functional applications and data processing by calling a computer program stored in the memory 302.

An embodiment of the present application provides a storage medium, and when being executed by a processor, the computer program performs a method in any optional implementation manner of the foregoing embodiment to implement the following functions: receiving data to be transmitted; selecting data with corresponding length from the data to be transmitted according to a data selection signal at a first clock rising edge in one period of a first clock signal, and transmitting the data to a data input end of a trigger; transmitting the data of the corresponding length from the data input end of the flip-flop to the data output end of the flip-flop for output on a second clock rising edge in one period of a second clock signal; converting the data of the corresponding length from parallel transmission to serial transmission; transmitting the data of the corresponding length transmitted in series to the data output interface at a second clock falling edge in one period of the first clock signal; at the rising edge of a third clock in one period of the first clock signal, serially outputting the data with the corresponding length through a data output interface; the first clock signal and the second clock signal have the same clock period, and the second clock signal is the clock signal obtained by delaying the first clock signal for a set time. The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.