1. A method for multiplexing a few-pin interface and a universal asynchronous receiver/transmitter interface, comprising:

the central processing unit sends the few-pin type signals and/or the universal asynchronous receiving and sending signals to the complex programmable logic device;

the connector generates a control signal and determines that the complex programmable logic device switches the few-pin type interface or the universal asynchronous receiver-transmitter interface according to the control signal;

and the complex programmable logic device is switched to a few-pin type interface or a universal asynchronous receiver-transmitter interface according to the control signal.

2. The method of claim 1, wherein the connector generates a control signal and determines the complex programmable logic device to switch between the few-pin interface or the universal asynchronous receiver/transmitter interface according to the control signal, comprising:

the connector generates a control signal by taking a pin on the connector as a self-defined control seat number, and determines that the complex programmable logic device switches a few-pin type interface or a universal asynchronous receiver/transmitter interface according to the control signal.

3. The method of claim 1, wherein the complex programmable logic device switches to the few-pin interface or the universal asynchronous receiver/transmitter interface according to the control signal, comprising:

and the complex programmable logic device detects the logic level of the control signal according to the control signal to judge, outputs a switching signal matched with the judgment, and switches to a few-pin type interface or a universal asynchronous receiver-transmitter interface according to the switching signal.

4. The method as claimed in claim 3, wherein the complex programmable logic device detects the logic level of the control signal according to the control signal to perform a determination, outputs a switching signal matching the determination, and switches to the less-pin interface or the UART interface according to the switching signal, comprising:

the complex programmable logic device detects the logic level of the control signal to judge according to the control signal in a mode of pulling the control signal up to a power supply voltage level through a resistor, outputs a switching signal matched with the judgment to turn on a first switch and turn off a second switch when the logic level is a high level, switches to a less-pin type interface according to the switching signal, outputs a switching signal matched with the judgment to turn on the second switch and turn off the first switch when the logic level is a low level, and switches to a universal asynchronous transceiver interface according to the switching signal.

5. The method of claim 1, wherein after the complex programmable logic device switches to the few-pin interface or the universal asynchronous receiver/transmitter interface according to the control signal, the method further comprises:

and the debugger debugs the server according to the signal output by the switched less-pin interface or the switched universal asynchronous receiver-transmitter interface.

6. A few pin interface and uart interface multiplexing device, comprising:

a central processing unit, a connector and a complex programmable logic device;

the central processing unit is used for sending the few-pin type signals and/or the universal asynchronous receiving and sending signals to the complex programmable logic device;

the connector is used for generating a control signal and determining that the complex programmable logic device switches the few-pin type interface or the universal asynchronous receiver/transmitter interface according to the control signal;

and the complex programmable logic device is used for switching to a few-pin type interface or a universal asynchronous receiver/transmitter interface according to the control signal.

7. The few-pin interface and UART interface multiplexing device of claim 6, wherein the connector is specifically configured to:

and generating a control signal by using a pin on the pin as a self-defined control seat number, and determining that the complex programmable logic device switches a few-pin type interface or a universal asynchronous receiver/transmitter interface according to the control signal.

8. The few-pin interface and UART interface multiplexing apparatus of claim 6, wherein the complex programmable logic device is specifically configured to:

and detecting the logic level of the control signal according to the control signal to judge, outputting a switching signal matched with the judgment, and switching to a few-pin interface or a universal asynchronous receiver/transmitter interface according to the switching signal.

9. The few-pin interface and UART interface multiplexing apparatus of claim 6, wherein the complex programmable logic device is specifically configured to:

and detecting the logic level of the control signal to judge according to the control signal in a mode of pulling the control signal up to a power supply voltage level through a resistor, outputting a switching signal matched with the judgment to turn on a first switch and turn off a second switch when the logic level is a high level, switching to a less-pin interface according to the switching signal, outputting a switching signal matched with the judgment to turn on the second switch and turn off the first switch when the logic level is a low level, and switching to a universal asynchronous transceiver interface according to the switching signal.

10. The few-pin interface and universal asynchronous receiver/transmitter interface multiplexing device according to claim 6, wherein said few-pin interface and universal asynchronous receiver/transmitter interface multiplexing device further comprises:

a debugger;

and the debugger is used for debugging the server according to the signals output by the switched few-pin type interface or the switched universal asynchronous transceiver interface.

Background

In the related art, a general server BIOS (Basic Input Output System) outputs boot information through a UART (Universal Asynchronous Receiver/Transmitter) interface, while System debugging is performed through a Low Pin Count (LPC) interface of a Central Processing Unit (CPU), and performs line switching through a Complex Programmable Logic Device (CPLD), so that the UART information and the LPC information can be switched and Output at the hardware interface.

However, most server manufacturers reserve a UART interface and an LPC interface on the Board for debugging convenience in the stage of developing the server, and due to the increase of the interfaces, the space cost of a PCB (Printed Circuit Board) is increased.

Disclosure of Invention

In view of the above, the present invention provides a method, an apparatus, and a device for multiplexing a few-pin interface and a universal asynchronous receiver/transmitter interface, which can realize that the multiplexing of the few-pin interface and the universal asynchronous receiver/transmitter interface is performed while the server is debugged conveniently, reduce the number of interfaces, and reduce the space cost of the printed circuit board.

According to an aspect of the present invention, there is provided a method for multiplexing a pin-less interface and a universal asynchronous receiver/transmitter interface, comprising: the central processing unit sends the few-pin type signals and/or the universal asynchronous receiving and sending signals to the complex programmable logic device; the connector generates a control signal and determines that the complex programmable logic device switches the few-pin type interface or the universal asynchronous receiver-transmitter interface according to the control signal; and the complex programmable logic device is switched to a few-pin type interface or a universal asynchronous receiver-transmitter interface according to the control signal.

Wherein the connector generates a control signal and determines whether the complex programmable logic device switches the few-pin interface or the UART interface according to the control signal, comprising: the connector generates a control signal by taking a pin on the connector as a self-defined control seat number, and determines that the complex programmable logic device switches a few-pin type interface or a universal asynchronous receiver/transmitter interface according to the control signal.

Wherein, the complicated programmable logic device switches to the few-pin type interface or the universal asynchronous receiver/transmitter interface according to the control signal, comprising: and the complex programmable logic device detects the logic level of the control signal according to the control signal to judge, outputs a switching signal matched with the judgment, and switches to a few-pin type interface or a universal asynchronous receiver-transmitter interface according to the switching signal.

The complex programmable logic device detects the logic level of the control signal according to the control signal to judge, outputs a switching signal matched with the judgment, and switches to a few-pin type interface or a universal asynchronous receiver/transmitter interface according to the switching signal, and the method comprises the following steps: the complex programmable logic device detects the logic level of the control signal to judge according to the control signal in a mode of pulling the control signal up to a power supply voltage level through a resistor, outputs a switching signal matched with the judgment to turn on a first switch and turn off a second switch when the logic level is a high level, switches to a less-pin type interface according to the switching signal, outputs a switching signal matched with the judgment to turn on the second switch and turn off the first switch when the logic level is a low level, and switches to a universal asynchronous transceiver interface according to the switching signal.

Wherein, after the complex programmable logic device switches to the few-pin interface or the universal asynchronous receiver/transmitter interface according to the control signal, the method further comprises: and the debugger debugs the server according to the signal output by the switched less-pin interface or the switched universal asynchronous receiver-transmitter interface.

According to another aspect of the present invention, there is provided a multiplexing apparatus for a pin-less interface and a universal asynchronous receiver/transmitter interface, comprising: a central processing unit, a connector and a complex programmable logic device; the central processing unit is used for sending the few-pin type signals and/or the universal asynchronous receiving and sending signals to the complex programmable logic device; the connector is used for generating a control signal and determining that the complex programmable logic device switches the few-pin type interface or the universal asynchronous receiver/transmitter interface according to the control signal; and the complex programmable logic device is used for switching to a few-pin type interface or a universal asynchronous receiver/transmitter interface according to the control signal.

Wherein, the connector is specifically used for: and generating a control signal by using a pin on the pin as a self-defined control seat number, and determining that the complex programmable logic device switches a few-pin type interface or a universal asynchronous receiver/transmitter interface according to the control signal.

The complex programmable logic device is specifically used for: and detecting the logic level of the control signal according to the control signal to judge, outputting a switching signal matched with the judgment, and switching to a few-pin interface or a universal asynchronous receiver/transmitter interface according to the switching signal.

The complex programmable logic device is specifically used for: and detecting the logic level of the control signal to judge according to the control signal in a mode of pulling the control signal up to a power supply voltage level through a resistor, outputting a switching signal matched with the judgment to turn on a first switch and turn off a second switch when the logic level is a high level, switching to a less-pin interface according to the switching signal, outputting a switching signal matched with the judgment to turn on the second switch and turn off the first switch when the logic level is a low level, and switching to a universal asynchronous transceiver interface according to the switching signal.

Wherein, the multiplexing device of the few-pin type interface and the universal asynchronous receiver-transmitter interface further comprises: a debugger; and the debugger is used for debugging the server according to the signals output by the switched few-pin type interface or the switched universal asynchronous transceiver interface.

According to yet another aspect of the present invention, there is provided a computer apparatus comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the pin-less interface and UART interface multiplexing method of any of the above.

According to yet another aspect of the present invention, there is provided a computer readable storage medium storing a computer program which, when executed by a processor, implements the method of multiplexing the low-pin interface and the universal asynchronous receiver/transmitter interface as described in any one of the above.

It can be found that, in the above scheme, the central processing unit can send the less pin type signal and/or the universal asynchronous receiving and transmitting signal to the complex programmable logic device, the connector can generate the control signal, and the complex programmable logic device is determined to switch the less pin type interface or the universal asynchronous receiving and transmitting interface according to the control signal, and the complex programmable logic device is switched to the less pin type interface or the universal asynchronous receiving and transmitting interface according to the control signal, so that the multiplexing of the less pin type interface and the universal asynchronous receiving and transmitting interface can be realized while the server is conveniently debugged, the number of interfaces is reduced, and the space cost of the printed circuit board is reduced.

Furthermore, according to the above scheme, the connector may generate the control signal by using the pin on the connector as a self-defined control socket number, and determine that the complex programmable logic device switches the few-pin interface or the universal asynchronous receiver/transmitter interface according to the control signal, so that the advantage of conveniently determining that the complex programmable logic device switches the few-pin interface or the universal asynchronous receiver/transmitter interface can be achieved, so as to conveniently achieve output of the few-pin signal or the universal asynchronous receiver/transmitter signal.

Furthermore, according to the scheme, the complex programmable logic device can detect the logic level of the control signal according to the control signal to judge, output the switching signal matched with the judgment, and switch to the fewer-pin type interface or the universal asynchronous transceiver interface according to the switching signal.

Furthermore, in the above scheme, the complex programmable logic device can detect the logic level of the control signal for judgment according to the control signal in a manner of pulling up the control signal to the power supply voltage level through a resistor, when the logic level is high level, the switching signal matched with the judgment is output to turn on the first switch and turn off the second switch, and the switching is switched to the less pin type interface according to the switching signal, when the logic level is at a low level, outputting a switching signal matching the judgment to open the second switch and close the first switch, according to the switching signal, the interface of the universal asynchronous receiver and transmitter is switched, which has the advantages that the debugging of the server is convenient, the method can multiplex the interfaces with few pins and the interfaces of the universal asynchronous receiver-transmitter, reduces the number of the interfaces and reduces the space cost of the printed circuit board.

Furthermore, according to the scheme, the debugger can debug the server according to the signals output by the switched few-pin type interfaces or the switched universal asynchronous receiver-transmitter interfaces, and the debugging method has the advantages that the multiplexing of the few-pin type interfaces and the universal asynchronous receiver-transmitter interfaces can be realized, the number of the interfaces is reduced, the space cost of the printed circuit board is reduced, and meanwhile the debugging server can be convenient.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a flow chart illustrating an embodiment of a method for multiplexing a few-pin interface and a UART interface according to the present invention;

FIG. 2 is a schematic diagram of an exemplary complex programmable logic device switching to a low pin interface or a UART interface according to a control signal;

FIG. 3 is a schematic diagram of another exemplary complex programmable logic device switching to a low pin interface or a UART interface according to a control signal;

FIG. 4 is a flow chart illustrating another embodiment of a method for multiplexing a few-pin interface and a UART interface according to the present invention;

FIG. 5 is a schematic structural diagram of an embodiment of a multiplexing apparatus for a few-pin interface and a UART interface according to the present invention;

FIG. 6 is a schematic structural diagram of another embodiment of a multiplexing apparatus for a few-pin interface and a UART interface according to the present invention;

FIG. 7 is a schematic structural diagram of an embodiment of the computer apparatus of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be noted that the following examples are only illustrative of the present invention, and do not limit the scope of the present invention. Similarly, the following examples are only some but not all examples of the present invention, and all other examples obtained by those skilled in the art without any inventive work are within the scope of the present invention.

The invention provides a method for multiplexing a few-pin type interface and a universal asynchronous receiver/transmitter interface, which can realize the multiplexing of the few-pin type interface and the universal asynchronous receiver/transmitter interface while facilitating the debugging of a server, reduce the number of interfaces and reduce the space cost of a printed circuit board.

Referring to fig. 1, fig. 1 is a flow chart illustrating an embodiment of a multiplexing method for a few-pin interface and a uart interface according to the present invention. It should be noted that the method of the present invention is not limited to the flow sequence shown in fig. 1 if the results are substantially the same. As shown in fig. 1, the method comprises the steps of:

s101: the central processing unit sends the few-pin type signals and/or the universal asynchronous receiving and sending signals to the complex programmable logic device.

In this embodiment, the central processing unit may send the few-pin signal and the uart signal to the complex programmable logic device synchronously, or may send the few-pin signal and the uart signal to the complex programmable logic device synchronously, respectively, and the like, which is not limited in the present invention.

S102: the connector generates a control signal and determines whether the complex programmable logic device switches the pin-less interface or the UART interface according to the control signal.

Wherein the connector generates a control signal and determines the complex programmable logic device to switch the low pin type interface or the UART interface according to the control signal, and may include:

the connector generates a control signal by taking an NC (NOT CONNECTED) pin on the connector as a self-defined control seat number, and determines that the complex programmable logic device switches the few-pin interface or the universal asynchronous receiver/transmitter interface according to the control signal, so that the advantage of conveniently determining that the complex programmable logic device switches the few-pin interface or the universal asynchronous receiver/transmitter interface can be realized, and the output of the few-pin signal or the universal asynchronous receiver/transmitter signal can be conveniently realized.

In this embodiment, the connector may be a TCM3/5 (secure chip mode) standard interface definition, or may be an interface definition of another mode, and the invention is not limited thereto.

S103: the complex programmable logic device switches to a few-pin type interface or a universal asynchronous receiver/transmitter interface according to the control signal.

Wherein, the switching to the less pin type interface or the UART interface by the PLC according to the control signal may include:

the complex programmable logic device detects the logic level of the control signal according to the control signal to judge, outputs a switching signal matched with the judgment, and switches to the fewer pin type interface or the universal asynchronous transceiver interface according to the switching signal.

The complex programmable logic device detects a logic level of the control signal according to the control signal to perform judgment, outputs a switching signal matching the judgment, and switches to the few-pin interface or the universal asynchronous receiver/transmitter interface according to the switching signal, which may include:

the complex programmable logic device detects the logic level of the control signal to judge by adopting a mode of pulling the control signal up to VCC (Volt Current Condense) level through a resistor according to the control signal, outputs a switching signal matched with the judgment to turn on a first switch and turn off a second switch when the logic level is high level, switches to a less pin type interface according to the switching signal, outputs a switching signal matched with the judgment to turn on the second switch and turn off the first switch when the logic level is low level, and switches to a universal asynchronous transceiver interface according to the switching signal.

In this embodiment, please refer to fig. 2 and 3, fig. 2 is an exemplary schematic diagram of the complex programmable logic device of the present invention switching to the less-pin interface or the uart interface according to the control signal, fig. 3 is another exemplary schematic diagram of the complex programmable logic device of the present invention switching to the less-pin interface or the uart interface according to the control signal, as shown in fig. 2 and 3, the complex programmable logic device detects the logic level of the control signal to perform the determination by pulling up the control signal to the VCC (supply voltage) level through a resistor according to the control signal, when the logic level is high, the switching signal matching the determination is outputted to turn on the first switch and turn off the second switch, according to the switching signal, the complex programmable logic device switches to the less-pin interface, when the logic level is low, the switching signal that this judgement is matchd in output is for opening the second switch and closing first switch, according to this switching signal, switches to general asynchronous receiver interface, and such advantage can realize when conveniently debugging the server, can multiplex to few stitch type interface and general asynchronous receiver interface, has reduced interface quantity, has reduced printed circuit board's space cost.

After the complex programmable logic device switches to the few-pin interface or the universal asynchronous receiver/transmitter interface according to the control signal, the method may further include:

the debugger debugs the server according to the signal output by the switched few-pin type interface or the universal asynchronous transceiver interface, and the debugging server has the advantages that the multiplexing of the few-pin type interface and the universal asynchronous transceiver interface can be realized, the number of interfaces is reduced, the space cost of the printed circuit board is reduced, and meanwhile, the debugging server can be convenient.

It can be found that, in this embodiment, the central processing unit may send the few-pin type signal and/or the uart signal to the complex programmable logic device, and the connector may generate the control signal, and determine that the complex programmable logic device switches the few-pin type interface or the uart interface according to the control signal, and the complex programmable logic device switches the few-pin type interface or the uart interface according to the control signal, so that the multiplexing of the few-pin type interface and the uart interface can be performed while the server is conveniently debugged, the number of interfaces is reduced, and the space cost of the pcb is reduced.

Further, in this embodiment, the connector may generate a control signal by using the pin thereon as a self-defined control socket number, and determine that the complex programmable logic device switches the few-pin interface or the universal asynchronous receiver/transmitter interface according to the control signal, which is advantageous in that it can conveniently determine that the complex programmable logic device switches the few-pin interface or the universal asynchronous receiver/transmitter interface, so as to conveniently implement output of the few-pin signal or the universal asynchronous receiver/transmitter signal.

Furthermore, in this embodiment, the complex programmable logic device may detect a logic level of the control signal according to the control signal to perform a judgment, output a switching signal matching the judgment, and switch to the fewer-pin interface or the universal asynchronous transceiver interface according to the switching signal.

Further, in this embodiment, the complex programmable logic device may detect the logic level of the control signal for determination according to the control signal by pulling up the control signal to the power supply voltage level through a resistor, when the logic level is high level, the switching signal matched with the judgment is output to turn on the first switch and turn off the second switch, and the switching is switched to the less pin type interface according to the switching signal, when the logic level is at a low level, outputting a switching signal matching the judgment to open the second switch and close the first switch, according to the switching signal, the interface of the universal asynchronous receiver and transmitter is switched, which has the advantages that the debugging of the server is convenient, the method can multiplex the interfaces with few pins and the interfaces of the universal asynchronous receiver-transmitter, reduces the number of the interfaces and reduces the space cost of the printed circuit board.

Referring to fig. 4, fig. 4 is a flow chart illustrating another embodiment of the multiplexing method for the low pin interface and the uart interface according to the present invention. In this embodiment, the method includes the steps of:

s401: the central processing unit sends the few-pin type signals and/or the universal asynchronous receiving and sending signals to the complex programmable logic device.

As described above in S101, further description is omitted here.

S402: the connector generates a control signal and determines whether the complex programmable logic device switches the pin-less interface or the UART interface according to the control signal.

As described above in S102, further description is omitted here.

S403: the complex programmable logic device switches to a few-pin type interface or a universal asynchronous receiver/transmitter interface according to the control signal.

As described above in S103, which is not described herein.

S404: the debugger debugs the server according to the signal output by the switched few-pin interface or the universal asynchronous receiver-transmitter interface.

It can be found that, in this embodiment, the debugger can debug the server according to the signal output by the switched few-pin interface or the switched universal asynchronous receiver/transmitter interface, which can realize multiplexing the few-pin interface and the universal asynchronous receiver/transmitter interface, reduce the number of interfaces, reduce the space cost of the printed circuit board, and simultaneously, can conveniently debug the server.

The invention also provides a device for multiplexing the few-pin type interface and the universal asynchronous receiver/transmitter interface, which can realize the multiplexing of the few-pin type interface and the universal asynchronous receiver/transmitter interface while facilitating the debugging of the server, reduce the number of interfaces and reduce the space cost of a printed circuit board.

Referring to fig. 5, fig. 5 is a schematic structural diagram of an embodiment of a multiplexing device for a few-pin interface and a uart interface according to the present invention. In this embodiment, the multiplexing device 50 for the pin-less interface and the UART interface comprises a central processing unit 51, a connector 52 and a complex programmable logic device 53.

The cpu 51 is used for transmitting the low pin signal and/or the uart signal to the complex programmable logic device 53.

The connector 52 is used for generating a control signal and determining the complex programmable logic device 53 to switch the pin-less interface or the UART interface according to the control signal.

The complex programmable logic device 53 is configured to switch to the low pin type interface or the universal asynchronous receiver/transmitter interface according to the control signal.

Alternatively, the connector 52 may be specifically configured to:

the control signal is generated by using the empty pin as the self-defined control seat number, and the complicated programmable logic device 53 is determined to switch the less pin type interface or the universal asynchronous receiver-transmitter interface according to the control signal.

Optionally, the complex programmable logic device 53 may be specifically configured to:

and detecting the logic level of the control signal according to the control signal to judge, outputting a switching signal matched with the judgment, and switching to a few-pin type interface or a universal asynchronous receiver/transmitter interface according to the switching signal.

Optionally, the complex programmable logic device 53 may be specifically configured to:

and when the logic level is low level, outputting a switching signal matched with the judgment to turn on the second switch and turn off the first switch, and switching to the interface of the universal asynchronous receiver-transmitter according to the switching signal.

Referring to fig. 6, fig. 6 is a schematic structural diagram of another embodiment of the multiplexing apparatus for a few-pin interface and a uart interface according to the present invention. Unlike the previous embodiment, the multiplexing apparatus 60 for pin-less interface and UART according to the present embodiment further includes a debugger 61.

The debugger 61 is configured to debug the server according to the signal output by the switched low pin type interface or the switched universal asynchronous receiver/transmitter interface.

The unit modules of the multiplexing device 50/60 for the low pin interface and the uart interface can respectively execute the corresponding steps in the above method embodiments, so that the detailed description of the corresponding steps is not repeated here.

The present invention further provides a computer device, as shown in fig. 7, comprising: at least one processor 71; and a memory 72 communicatively coupled to the at least one processor 71; the memory 72 stores instructions executable by the at least one processor 71, and the instructions are executable by the at least one processor 71 to enable the at least one processor 71 to perform the pin-less interface and the UART interface multiplexing method described above.

Where the memory 72 and the processor 71 are coupled in a bus, the bus may comprise any number of interconnected buses and bridges, the buses coupling together one or more of the various circuits of the processor 71 and the memory 72. The bus may also connect various other circuits such as peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further herein. A bus interface provides an interface between the bus and the transceiver. The transceiver may be one element or a plurality of elements, such as a plurality of receivers and transmitters, providing a means for communicating with various other apparatus over a transmission medium. The data processed by the processor 71 is transmitted over a wireless medium via an antenna, which further receives the data and transmits the data to the processor 71.

The processor 71 is responsible for managing the bus and general processing and may also provide various functions including timing, peripheral interfaces, voltage regulation, power management, and other control functions. And memory 72 may be used to store data used by processor 71 in performing operations.

The present invention further provides a computer-readable storage medium storing a computer program. The computer program realizes the above-described method embodiments when executed by a processor.

It can be found that, in the above scheme, the central processing unit can send the less pin type signal and/or the universal asynchronous receiving and transmitting signal to the complex programmable logic device, the connector can generate the control signal, and the complex programmable logic device is determined to switch the less pin type interface or the universal asynchronous receiving and transmitting interface according to the control signal, and the complex programmable logic device is switched to the less pin type interface or the universal asynchronous receiving and transmitting interface according to the control signal, so that the multiplexing of the less pin type interface and the universal asynchronous receiving and transmitting interface can be realized while the server is conveniently debugged, the number of interfaces is reduced, and the space cost of the printed circuit board is reduced.

Furthermore, according to the above scheme, the connector may generate the control signal by using the pin on the connector as a self-defined control socket number, and determine that the complex programmable logic device switches the few-pin interface or the universal asynchronous receiver/transmitter interface according to the control signal, so that the advantage of conveniently determining that the complex programmable logic device switches the few-pin interface or the universal asynchronous receiver/transmitter interface can be achieved, so as to conveniently achieve output of the few-pin signal or the universal asynchronous receiver/transmitter signal.

Furthermore, according to the scheme, the complex programmable logic device can detect the logic level of the control signal according to the control signal to judge, output the switching signal matched with the judgment, and switch to the fewer-pin type interface or the universal asynchronous transceiver interface according to the switching signal.

Furthermore, in the above scheme, the complex programmable logic device can detect the logic level of the control signal for judgment according to the control signal in a manner of pulling up the control signal to the power supply voltage level through a resistor, when the logic level is high level, the switching signal matched with the judgment is output to turn on the first switch and turn off the second switch, and the switching is switched to the less pin type interface according to the switching signal, when the logic level is at a low level, outputting a switching signal matching the judgment to open the second switch and close the first switch, according to the switching signal, the interface of the universal asynchronous receiver and transmitter is switched, which has the advantages that the debugging of the server is convenient, the method can multiplex the interfaces with few pins and the interfaces of the universal asynchronous receiver-transmitter, reduces the number of the interfaces and reduces the space cost of the printed circuit board.

Furthermore, according to the scheme, the debugger can debug the server according to the signals output by the switched few-pin type interfaces or the switched universal asynchronous receiver-transmitter interfaces, and the debugging method has the advantages that the multiplexing of the few-pin type interfaces and the universal asynchronous receiver-transmitter interfaces can be realized, the number of the interfaces is reduced, the space cost of the printed circuit board is reduced, and meanwhile the debugging server can be convenient.

In the several embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a module or a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be substantially or partially implemented in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The above description is only a part of the embodiments of the present invention, and not intended to limit the scope of the present invention, and all equivalent devices or equivalent processes performed by the present invention through the contents of the specification and the drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.