1. A synchronous-asynchronous conversion interface based on Mousetrap, wherein the interface is used with a Mousetrap controller, and the interface comprises:

the circuit comprises an AND module, an inversion module, an XOR module and a first latch;

the first input end of the AND module is used for inputting a synchronous clock signal, the second input end of the AND module is connected with the output end of the reverse module, the output end of the AND module is connected with the enable end of the first latch, the input end of the reverse module is connected with the output end of the XOR module, and the two input ends of the XOR module are respectively connected with the input end of the first latch and the output end of the first latch; the input end of the first latch and the output end of the first latch are both connected with the Mousetrap controller;

the AND module is used for AND-operating the synchronous clock signal and the null signal to generate a filling signal;

the first latch is used for generating a left request signal according to the filling signal and a left response signal output by the Mousetrap controller;

the exclusive OR module is used for carrying out exclusive OR operation on the left response signal and the left request signal to generate an exclusive OR signal;

and the inversion module is used for inverting the exclusive-or signal to obtain a null signal.

2. The Mousetrap-based synchronous-asynchronous conversion interface according to claim 1, wherein the and module is an and gate.

3. The Mousetrap-based synchronous-asynchronous conversion interface according to claim 1, wherein the reversing module is a reverser.

4. The Mousetrap-based synchronous-asynchronous conversion interface according to claim 1, wherein the xor module is an xor gate.

5. An apparatus for synchronous-asynchronous conversion, the apparatus comprising: the interface and the Mousetrap controller of any one of claims 1-4.

6. The synchronous-asynchronous conversion device of claim 5, wherein the Mousetrap controller comprises:

a second latch and an exclusive nor module; the output end of the exclusive-nor module is connected with the enable end of the second latch, the output end of the second latch is connected with the input end of the first latch, and the input end of the second latch is connected with the output end of the first latch;

the first input signal of the exclusive OR module is used for inputting a right response signal, the second input signal of the exclusive OR module is used for inputting a right request signal, and the exclusive OR module is used for exclusive OR operation of the right request signal and the right response signal to obtain an exclusive OR signal; the second latch is used for generating a left response signal and a right request signal according to the exclusive-nor signal and the left request signal.

7. The synchronous-asynchronous conversion device of claim 6, wherein the XNOR module is an XNOR gate.

Background

The conventional controller capable of controlling the pipeline cannot realize the conversion from the synchronous clock signal clk to the two-phase signal of the controller, and even cannot realize the work of the asynchronous signal of the controller in cooperation with the synchronous clock frequency under the synchronous clock signal, so how to set a conversion interface to realize the conversion of the two-phase signal and the cooperation of the asynchronous signal and the synchronous clock frequency becomes a technical problem to be solved urgently in the field.

Disclosure of Invention

The invention aims to provide a synchronous and asynchronous conversion interface and a synchronous and asynchronous conversion device based on Mousetrap, so that asynchronous control signals of a controller work in cooperation with synchronous clock frequency.

In order to achieve the above object, the present invention provides a synchronous/asynchronous conversion interface based on Mousetrap, where the interface is used with a Mousetrap controller, and the interface includes:

the circuit comprises an AND module, an inversion module, an XOR module and a first latch;

the first input end of the AND module is used for inputting a synchronous clock signal, the second input end of the AND module is connected with the output end of the reverse module, the output end of the AND module is connected with the enable end of the first latch, the input end of the reverse module is connected with the output end of the XOR module, and the two input ends of the XOR module are respectively connected with the input end of the first latch and the output end of the first latch; the input end of the first latch and the output end of the first latch are both connected with the Mousetrap controller;

the AND module is used for AND-operating the synchronous clock signal and the null signal to generate a filling signal;

the first latch is used for generating a left request signal according to the filling signal and a left response signal output by the Mousetrap controller;

the exclusive OR module is used for carrying out exclusive OR operation on the left response signal and the left request signal to generate an exclusive OR signal;

and the inversion module is used for inverting the exclusive-or signal to obtain a null signal.

Optionally, the and module is an and gate.

Optionally, the reversing module is a reverser.

Optionally, the xor module is an xor gate.

The present invention also provides a synchronous-asynchronous conversion apparatus, which is characterized in that the apparatus comprises: the interface and the Mousetrap controller.

Optionally, the Mousetrap controller comprises:

a second latch and an exclusive nor module; the output end of the exclusive-nor module is connected with the enable end of the second latch, the output end of the second latch is connected with the input end of the first latch, and the input end of the second latch is connected with the output end of the first latch;

the first input signal of the exclusive OR module is used for inputting a right response signal, the second input signal of the exclusive OR module is used for inputting a right request signal, and the exclusive OR module is used for exclusive OR operation of the right request signal and the right response signal to obtain an exclusive OR signal; the second latch is used for generating a left response signal and a right request signal according to the exclusive-nor signal and the left request signal.

Optionally, the exclusive nor module is an exclusive nor gate.

According to the specific embodiment provided by the invention, the invention discloses the following technical effects:

the invention discloses a synchronous and asynchronous conversion interface and a device based on Mousetrap, which realize the conversion from a synchronous clock signal to a controller binomial signal by setting the synchronous and asynchronous conversion interface and simultaneously realize the work of the asynchronous signal of the controller under a synchronous clock by matching with the frequency of the synchronous clock.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.

FIG. 1 is a structural diagram of a synchronous-asynchronous conversion device based on Mousetrap according to the present invention;

FIG. 2 is a simulation of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The invention aims to provide a synchronous and asynchronous conversion interface and a synchronous and asynchronous conversion device based on Mousetrap, so that asynchronous control signals of a controller work in cooperation with synchronous clock frequency.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.

Example 1

The invention discloses a synchronous and asynchronous conversion interface based on a Mousetrap, which is matched with a controller based on the Mousetrap for use, and comprises the following components: the circuit comprises an AND module, an inversion module, an XOR module and a first latch; the first input end of the AND module is used for inputting a synchronous clock signal, the second input end of the AND module is connected with the output end of the reverse module, the output end of the AND module is connected with the enable end of the first latch, the input end of the reverse module is connected with the output end of the XOR module, and the two input ends of the XOR module are respectively connected with the input end of the first latch and the output end of the first latch; the input end of the first latch and the output end of the first latch are both connected with the controller.

The AND module is used for AND-operating the synchronous clock signal and the null signal to generate a filling signal; the first latch is used for generating a left request signal according to the filling signal and a left response signal output by the controller; the exclusive OR module is used for carrying out exclusive OR operation on the left response signal and the left request signal to generate an exclusive OR signal; and the inversion module is used for inverting the exclusive-or signal to obtain a null signal.

As shown in fig. 1, the present invention sets the and module as and gate, the inversion module as inverter inv, and the xor module as xor gate xor _ R. A second input end of the and gate and is connected with an output end of the inverter inv, an output end of the and gate and is connected with an enable end of the first latch _ R, an input end of the inverter inv is connected with an output end of the xor gate xor _ R, and two input ends of the xor gate xor _ R are respectively connected with an input end of the first latch _ R and an output end of the first latch _ R; an input terminal of the first latch _ R and an output terminal of the first latch _ R are both connected to the controller 2.

The AND gate and performs AND operation on the synchronous clock signal clk and the empty signal empty to generate a filling signal fill; the first latch _ R generates a left request signal Req _ L according to the filling signal fill and a left response signal Ack _ L output by the Mouserrap controller; the exclusive-or gate xor _ R performs exclusive-or operation on the left response signal Ack _ L and the left request signal Req _ L to generate an exclusive-or signal; the inverter inv is configured to perform an inverting operation on the exclusive or signal to obtain a null signal empty.

According to the invention, the synchronous clock signal clk and the empty signal empty output by the inverter inv are enabled to output the fill signal and input into the enable end of the first latch _ R, so that the asynchronous control signal of the Mouserrap controller can work in coordination with the frequency of the synchronous clock clk under the synchronous clock clk.

In addition, the output end and the input end of the inverter inv are respectively connected with the input end of the and gate and the output end of the exclusive or gate xor _ R, the two input ends of the exclusive or gate xor _ R are respectively connected with the input end and the output end of the first latch _ R, and the input end and the output end of the first latch _ R are both connected with the controller 2, so that the conversion of the two-item handshake protocol from the synchronous clock clk to the Mousetrap controller is realized, as shown in fig. 2, when the Ack signal arrives and the rising edge of the clk arrives, the Req _ L is inverted once.

Example 2

As shown in fig. 1, the present invention provides a synchronous-asynchronous conversion apparatus, which includes: the interface and the Mousetrap controller in example 1. The Mousetrap controller comprises:

a second latch and XNOR block; the output end of the exclusive-nor module is connected with the enable end of the second latch, the output end of the second latch is connected with the input end of the first latch _ R, and the input end of the second latch is connected with the output end of the first latch _ R. In this embodiment, the exclusive nor module is an exclusive nor xor.

The first input signal of the exclusive-or gate xor is used for inputting a right response signal Ack _ R, the second input signal of the exclusive-or gate xor is used for inputting a right request signal Req _ R, and the exclusive-or gate xor is used for exclusive-oring the right request signal Req _ R and the right response signal Ack _ R to obtain an exclusive-or signal; the second latch is used for generating a left response signal Ack _ L and a right request signal Req _ R according to the exclusive-nor signal and the left request signal Req _ L.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to assist in understanding the core concepts of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.